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Last arm patches for rc3...
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit 72138f9bf5d8c316043b0d2cc7a674f70930cf95:
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging (2018-11-26 11:46:04 +0000)
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181126
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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for you to fetch changes up to 58102ce7fbb2362aa53984aabcf684d164da2d9d:
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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net: cadence_gem: Remove incorrect assert() (2018-11-26 13:41:42 +0000)
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm: Fix bug where we weren't initializing
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* some updates to MAINTAINERS file entries
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guarded bit state when combining S1/S2 attrs
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* cadence_gem: Remove an incorrect assert()
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----------------------------------------------------------------
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----------------------------------------------------------------
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Edgar E. Iglesias (1):
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Richard Henderson (2):
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net: cadence_gem: Remove incorrect assert()
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target/arm: PTE bit GP only applies to stage1
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target/arm: Copy guarded bit in combine_cacheattrs
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Eric Auger (1):
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target/arm/ptw.c | 11 ++++++-----
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MAINTAINERS: Add an ARM SMMU section
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1 file changed, 6 insertions(+), 5 deletions(-)
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Thomas Huth (1):
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MAINTAINERS: Assign some more files in the hw/arm/ directory
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hw/net/cadence_gem.c | 1 -
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MAINTAINERS | 23 +++++++++++++++++++++++
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2 files changed, 23 insertions(+), 1 deletion(-)
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diff view generated by jsdifflib
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From: Eric Auger <eric.auger@redhat.com>
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From: Richard Henderson <richard.henderson@linaro.org>
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2
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Add a new ARM SMMU section and set Eric Auger as the maintainer
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Only perform the extract of GP during the stage1 walk.
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for ARM SMMU emulation sources.
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4
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20181122180143.14237-1-eric.auger@redhat.com
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Suggested-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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---
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MAINTAINERS | 7 +++++++
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 7 insertions(+)
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/MAINTAINERS b/MAINTAINERS
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/MAINTAINERS
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--- a/target/arm/ptw.c
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+++ b/MAINTAINERS
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ F: disas/arm.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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F: disas/arm-a64.cc
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result->f.attrs.secure = false;
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F: disas/libvixl/
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}
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+ARM SMMU
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+M: Eric Auger <eric.auger@redhat.com>
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+L: qemu-arm@nongnu.org
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+S: Maintained
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- }
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+F: hw/arm/smmu*
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-
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+F: include/hw/arm/smmu*
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+
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CRIS
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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S: Maintained
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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--
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2.19.1
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2.34.1
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diff view generated by jsdifflib
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From: Thomas Huth <thuth@redhat.com>
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From: Richard Henderson <richard.henderson@linaro.org>
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2
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I apparently missed some more files and even a complete machine (the
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The guarded bit comes from the stage1 walk.
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"imx25-pdk") in my previous patch... but now we should hopefully have
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a completely coverage for all available ARM boards.
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4
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Fixes: 95a5db3ae5698b49c63144610ad02913e780c828
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Fixes: Coverity CID 1507929
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Signed-off-by: Thomas Huth <thuth@redhat.com>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 1542782568-20059-1-git-send-email-thuth@redhat.com
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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---
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MAINTAINERS | 16 ++++++++++++++++
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target/arm/ptw.c | 1 +
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1 file changed, 16 insertions(+)
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1 file changed, 1 insertion(+)
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diff --git a/MAINTAINERS b/MAINTAINERS
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
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--- a/MAINTAINERS
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--- a/target/arm/ptw.c
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+++ b/MAINTAINERS
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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S: Odd Fixes
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F: hw/arm/gumstix.c
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+i.MX25 PDK
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+ ret.guarded = s1.guarded;
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+M: Peter Maydell <peter.maydell@linaro.org>
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+R: Jean-Christophe Dubois <jcd@tribudubois.net>
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if (s1.attrs == 0xf0) {
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+L: qemu-arm@nongnu.org
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tagged = true;
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+S: Odd Fixes
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+F: hw/arm/fsl-imx25.c
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+F: hw/arm/imx25_pdk.c
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+F: hw/misc/imx25_ccm.c
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+F: include/hw/arm/fsl-imx25.h
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+F: include/hw/misc/imx25_ccm.h
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+
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i.MX31 (kzm)
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M: Peter Chubb <peter.chubb@nicta.com.au>
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M: Peter Maydell <peter.maydell@linaro.org>
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@@ -XXX,XX +XXX,XX @@ R: Andrew Baumann <Andrew.Baumann@microsoft.com>
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R: Philippe Mathieu-Daudé <f4bug@amsat.org>
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L: qemu-arm@nongnu.org
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S: Odd Fixes
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+F: hw/arm/raspi.c
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F: hw/arm/raspi_platform.h
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F: hw/*/bcm283*
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F: include/hw/arm/raspi*
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@@ -XXX,XX +XXX,XX @@ F: hw/arm/spitz.c
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F: hw/arm/tosa.c
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F: hw/arm/z2.c
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F: hw/*/pxa2xx*
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+F: hw/display/tc6393xb.c
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+F: hw/gpio/max7310.c
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+F: hw/gpio/zaurus.c
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F: hw/misc/mst_fpga.c
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F: include/hw/arm/pxa.h
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+F: include/hw/arm/sharpsl.h
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SABRELITE / i.MX6
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M: Peter Maydell <peter.maydell@linaro.org>
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--
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--
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2.19.1
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2.34.1
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diff view generated by jsdifflib