1 | Last arm patches for rc3... | 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: |
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2 | we were using uninitialized data for the guarded bit when | ||
3 | combining stage 1 and stage 2 attrs. | ||
2 | 4 | ||
3 | thanks | 5 | thanks |
4 | -- PMM | 6 | -- PMM |
5 | 7 | ||
6 | The following changes since commit 72138f9bf5d8c316043b0d2cc7a674f70930cf95: | 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: |
7 | 9 | ||
8 | Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging (2018-11-26 11:46:04 +0000) | 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) |
9 | 11 | ||
10 | are available in the Git repository at: | 12 | are available in the Git repository at: |
11 | 13 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181126 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 |
13 | 15 | ||
14 | for you to fetch changes up to 58102ce7fbb2362aa53984aabcf684d164da2d9d: | 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: |
15 | 17 | ||
16 | net: cadence_gem: Remove incorrect assert() (2018-11-26 13:41:42 +0000) | 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) |
17 | 19 | ||
18 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
19 | target-arm queue: | 21 | target-arm: Fix bug where we weren't initializing |
20 | * some updates to MAINTAINERS file entries | 22 | guarded bit state when combining S1/S2 attrs |
21 | * cadence_gem: Remove an incorrect assert() | ||
22 | 23 | ||
23 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
24 | Edgar E. Iglesias (1): | 25 | Richard Henderson (2): |
25 | net: cadence_gem: Remove incorrect assert() | 26 | target/arm: PTE bit GP only applies to stage1 |
27 | target/arm: Copy guarded bit in combine_cacheattrs | ||
26 | 28 | ||
27 | Eric Auger (1): | 29 | target/arm/ptw.c | 11 ++++++----- |
28 | MAINTAINERS: Add an ARM SMMU section | 30 | 1 file changed, 6 insertions(+), 5 deletions(-) |
29 | |||
30 | Thomas Huth (1): | ||
31 | MAINTAINERS: Assign some more files in the hw/arm/ directory | ||
32 | |||
33 | hw/net/cadence_gem.c | 1 - | ||
34 | MAINTAINERS | 23 +++++++++++++++++++++++ | ||
35 | 2 files changed, 23 insertions(+), 1 deletion(-) | ||
36 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
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2 | 2 | ||
3 | Add a new ARM SMMU section and set Eric Auger as the maintainer | 3 | Only perform the extract of GP during the stage1 walk. |
4 | for ARM SMMU emulation sources. | ||
5 | 4 | ||
6 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20181122180143.14237-1-eric.auger@redhat.com | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | MAINTAINERS | 7 +++++++ | 11 | target/arm/ptw.c | 10 +++++----- |
12 | 1 file changed, 7 insertions(+) | 12 | 1 file changed, 5 insertions(+), 5 deletions(-) |
13 | 13 | ||
14 | diff --git a/MAINTAINERS b/MAINTAINERS | 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/MAINTAINERS | 16 | --- a/target/arm/ptw.c |
17 | +++ b/MAINTAINERS | 17 | +++ b/target/arm/ptw.c |
18 | @@ -XXX,XX +XXX,XX @@ F: disas/arm.c | 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
19 | F: disas/arm-a64.cc | 19 | result->f.attrs.secure = false; |
20 | F: disas/libvixl/ | 20 | } |
21 | 21 | ||
22 | +ARM SMMU | 22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ |
23 | +M: Eric Auger <eric.auger@redhat.com> | 23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { |
24 | +L: qemu-arm@nongnu.org | 24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ |
25 | +S: Maintained | 25 | - } |
26 | +F: hw/arm/smmu* | 26 | - |
27 | +F: include/hw/arm/smmu* | 27 | if (regime_is_stage2(mmu_idx)) { |
28 | result->cacheattrs.is_s2_format = true; | ||
29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
31 | assert(attrindx <= 7); | ||
32 | result->cacheattrs.is_s2_format = false; | ||
33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
28 | + | 34 | + |
29 | CRIS | 35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ |
30 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | 36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { |
31 | S: Maintained | 37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ |
38 | + } | ||
39 | } | ||
40 | |||
41 | /* | ||
32 | -- | 42 | -- |
33 | 2.19.1 | 43 | 2.34.1 |
34 | |||
35 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
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2 | 2 | ||
3 | I apparently missed some more files and even a complete machine (the | 3 | The guarded bit comes from the stage1 walk. |
4 | "imx25-pdk") in my previous patch... but now we should hopefully have | ||
5 | a completely coverage for all available ARM boards. | ||
6 | 4 | ||
7 | Fixes: 95a5db3ae5698b49c63144610ad02913e780c828 | 5 | Fixes: Coverity CID 1507929 |
8 | Signed-off-by: Thomas Huth <thuth@redhat.com> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Message-id: 1542782568-20059-1-git-send-email-thuth@redhat.com | 8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 10 | --- |
13 | MAINTAINERS | 16 ++++++++++++++++ | 11 | target/arm/ptw.c | 1 + |
14 | 1 file changed, 16 insertions(+) | 12 | 1 file changed, 1 insertion(+) |
15 | 13 | ||
16 | diff --git a/MAINTAINERS b/MAINTAINERS | 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/MAINTAINERS | 16 | --- a/target/arm/ptw.c |
19 | +++ b/MAINTAINERS | 17 | +++ b/target/arm/ptw.c |
20 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, |
21 | S: Odd Fixes | 19 | |
22 | F: hw/arm/gumstix.c | 20 | assert(!s1.is_s2_format); |
23 | 21 | ret.is_s2_format = false; | |
24 | +i.MX25 PDK | 22 | + ret.guarded = s1.guarded; |
25 | +M: Peter Maydell <peter.maydell@linaro.org> | 23 | |
26 | +R: Jean-Christophe Dubois <jcd@tribudubois.net> | 24 | if (s1.attrs == 0xf0) { |
27 | +L: qemu-arm@nongnu.org | 25 | tagged = true; |
28 | +S: Odd Fixes | ||
29 | +F: hw/arm/fsl-imx25.c | ||
30 | +F: hw/arm/imx25_pdk.c | ||
31 | +F: hw/misc/imx25_ccm.c | ||
32 | +F: include/hw/arm/fsl-imx25.h | ||
33 | +F: include/hw/misc/imx25_ccm.h | ||
34 | + | ||
35 | i.MX31 (kzm) | ||
36 | M: Peter Chubb <peter.chubb@nicta.com.au> | ||
37 | M: Peter Maydell <peter.maydell@linaro.org> | ||
38 | @@ -XXX,XX +XXX,XX @@ R: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
39 | R: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
40 | L: qemu-arm@nongnu.org | ||
41 | S: Odd Fixes | ||
42 | +F: hw/arm/raspi.c | ||
43 | F: hw/arm/raspi_platform.h | ||
44 | F: hw/*/bcm283* | ||
45 | F: include/hw/arm/raspi* | ||
46 | @@ -XXX,XX +XXX,XX @@ F: hw/arm/spitz.c | ||
47 | F: hw/arm/tosa.c | ||
48 | F: hw/arm/z2.c | ||
49 | F: hw/*/pxa2xx* | ||
50 | +F: hw/display/tc6393xb.c | ||
51 | +F: hw/gpio/max7310.c | ||
52 | +F: hw/gpio/zaurus.c | ||
53 | F: hw/misc/mst_fpga.c | ||
54 | F: include/hw/arm/pxa.h | ||
55 | +F: include/hw/arm/sharpsl.h | ||
56 | |||
57 | SABRELITE / i.MX6 | ||
58 | M: Peter Maydell <peter.maydell@linaro.org> | ||
59 | -- | 26 | -- |
60 | 2.19.1 | 27 | 2.34.1 |
61 | |||
62 | diff view generated by jsdifflib |