Hi; some minor changes for 6.2, which I think can be classified

as bug fixes and are OK for this point in the release cycle.

(Wouldn't be the end of the world if they slipped to 7.0.)

The following changes since commit 42f6c9179be4401974dd3a75ee72defd16b5092d:

Merge tag 'pull-ppc-20211112' of https://github.com/legoater/qemu into staging (2021-11-12 12:28:25 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211115-1

for you to fetch changes up to 1adf528ec3bdf62ea3b580b7ad562534a3676ff5:

hw/rtc/pl031: Send RTC_CHANGE QMP event (2021-11-15 18:53:00 +0000)

* Support multiple redistributor regions for TCG GICv3

* Send RTC_CHANGE QMP event from pl031

Eric Auger (1):

hw/rtc/pl031: Send RTC_CHANGE QMP event

Peter Maydell (3):

hw/intc/arm_gicv3: Move checking of redist-region-count to arm_gicv3_common_realize

hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1

hw/intc/arm_gicv3: Support multiple redistributor regions

include/hw/intc/arm_gicv3_common.h | 14 ++++++++--

hw/intc/arm_gicv3.c | 12 +-------

hw/intc/arm_gicv3_common.c | 56 ++++++++++++++++++++++++--------------

hw/intc/arm_gicv3_kvm.c | 10 ++-----

hw/intc/arm_gicv3_redist.c | 40 +++++++++++++++------------

hw/rtc/pl031.c | 10 ++++++-

hw/rtc/meson.build | 2 +-

7 files changed, 83 insertions(+), 61 deletions(-)

The GICv3 devices have an array property redist-region-count.

Currently we check this for errors (bad values) in

gicv3_init_irqs_and_mmio(), just before we use it. Move this error

checking to the arm_gicv3_common_realize() function, where we

sanity-check all of the other base-class properties. (This will

always be before gicv3_init_irqs_and_mmio() is called, because

that function is called in the subclass realize methods, after

they have called the parent-class realize.)

The motivation for this refactor is:

* we would like to use the redist_region_count[] values in

arm_gicv3_common_realize() in a subsequent patch, so we need

to have already done the sanity-checking first

* this removes the only use of the Error** argument to

gicv3_init_irqs_and_mmio(), so we can remove some error-handling

boilerplate

include/hw/intc/arm_gicv3_common.h | 2 +-

hw/intc/arm_gicv3.c | 6 +-----

hw/intc/arm_gicv3_common.c | 26 +++++++++++++-------------

hw/intc/arm_gicv3_kvm.c | 6 +-----

4 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h

--- a/include/hw/intc/arm_gicv3_common.h

+++ b/include/hw/intc/arm_gicv3_common.h

@@ -XXX,XX +XXX,XX @@ struct ARMGICv3CommonClass {

};

void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,

- const MemoryRegionOps *ops, Error **errp);

+ const MemoryRegionOps *ops);

#endif

diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gicv3.c

+++ b/hw/intc/arm_gicv3.c

@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)

return;

}

- gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops, &local_err);

- if (local_err) {

- error_propagate(errp, local_err);

- return;

- }

+ gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);

gicv3_init_cpuif(s);

}

diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gicv3_common.c

+++ b/hw/intc/arm_gicv3_common.c

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = {

};

void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,

- const MemoryRegionOps *ops, Error **errp)

+ const MemoryRegionOps *ops)

{

SysBusDevice *sbd = SYS_BUS_DEVICE(s);

- int rdist_capacity = 0;

int i;

- for (i = 0; i < s->nb_redist_regions; i++) {

- rdist_capacity += s->redist_region_count[i];

- }

- if (rdist_capacity < s->num_cpu) {

- error_setg(errp, "Capacity of the redist regions(%d) "

- "is less than number of vcpus(%d)",

- rdist_capacity, s->num_cpu);

- return;

- }

-

/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.

* GPIO array layout is thus:

* [0..N-1] spi

@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,

static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)

{

GICv3State *s = ARM_GICV3_COMMON(dev);

- int i;

+ int i, rdist_capacity;

/* revision property is actually reserved and currently used only in order

* to keep the interface compatible with GICv2 code, avoiding extra

@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)

return;

}

+ rdist_capacity = 0;

+ for (i = 0; i < s->nb_redist_regions; i++) {

+ rdist_capacity += s->redist_region_count[i];

+ }

+ if (rdist_capacity < s->num_cpu) {

+ error_setg(errp, "Capacity of the redist regions(%d) "

+ "is less than number of vcpus(%d)",

+ rdist_capacity, s->num_cpu);

+ return;

+ }

s->cpu = g_new0(GICv3CPUState, s->num_cpu);

for (i = 0; i < s->num_cpu; i++) {

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gicv3_kvm.c

+++ b/hw/intc/arm_gicv3_kvm.c

@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)

return;

}

- gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err);

- if (local_err) {

- error_propagate(errp, local_err);

- return;

- }

+ gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);

for (i = 0; i < s->num_cpu; i++) {

ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));

2.25.1

Our GICv3 QOM interface includes an array property

redist-region-count which allows board models to specify that the

registributor registers are not in a single contiguous range, but

split into multiple pieces. We implemented this for KVM, but

currently the TCG GICv3 model insists that there is only one region.

You can see the limit being hit with a setup like:

qemu-system-aarch64 -machine virt,gic-version=3 -smp 124

Add support for split regions to the TCG GICv3. To do this we switch

from allocating a simple array of MemoryRegions to an array of

GICv3RedistRegion structs so that we can use the GICv3RedistRegion as

the opaque pointer in the MemoryRegion read/write callbacks. Each

GICv3RedistRegion contains the MemoryRegion, a backpointer allowing

the read/write callback to get hold of the GICv3State, and an index

which allows us to calculate which CPU's redistributor is being

accessed.

Note that arm_gicv3_kvm always passes in NULL as the ops argument

to gicv3_init_irqs_and_mmio(), so the only MemoryRegion read/write

callbacks we need to update to handle this new scheme are the

gicv3_redist_read/write functions used by the emulated GICv3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

---

include/hw/intc/arm_gicv3_common.h | 12 ++++++++-

hw/intc/arm_gicv3.c | 6 -----

hw/intc/arm_gicv3_common.c | 15 ++++++++---

hw/intc/arm_gicv3_kvm.c | 4 +--

hw/intc/arm_gicv3_redist.c | 40 ++++++++++++++++--------------

5 files changed, 46 insertions(+), 31 deletions(-)

diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/intc/arm_gicv3_common.h

+++ b/include/hw/intc/arm_gicv3_common.h

@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {

bool seenbetter;

};

+/*

+ * The redistributor pages might be split into more than one region

+ * on some machine types if there are many CPUs.

+ */

+typedef struct GICv3RedistRegion {

+ GICv3State *gic;

+ MemoryRegion iomem;

+ uint32_t cpuidx; /* index of first CPU this region covers */

+} GICv3RedistRegion;

+

struct GICv3State {

/*< private >*/

SysBusDevice parent_obj;

/*< public >*/

MemoryRegion iomem_dist; /* Distributor */

- MemoryRegion *iomem_redist; /* Redistributor Regions */

+ GICv3RedistRegion *redist_regions; /* Redistributor Regions */

uint32_t *redist_region_count; /* redistributor count within each region */

uint32_t nb_redist_regions; /* number of redist regions */

diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gicv3.c

+++ b/hw/intc/arm_gicv3.c

@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)

return;

}

- if (s->nb_redist_regions != 1) {

- error_setg(errp, "VGICv3 redist region number(%d) not equal to 1",

- s->nb_redist_regions);

- return;

- }

-

gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);

gicv3_init_cpuif(s);

diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gicv3_common.c

+++ b/hw/intc/arm_gicv3_common.c

@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,

{

SysBusDevice *sbd = SYS_BUS_DEVICE(s);

int i;

+ int cpuidx;

/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.

* GPIO array layout is thus:

@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,

"gicv3_dist", 0x10000);

sysbus_init_mmio(sbd, &s->iomem_dist);

- s->iomem_redist = g_new0(MemoryRegion, s->nb_redist_regions);

+ s->redist_regions = g_new0(GICv3RedistRegion, s->nb_redist_regions);

+ cpuidx = 0;

for (i = 0; i < s->nb_redist_regions; i++) {

char *name = g_strdup_printf("gicv3_redist_region[%d]", i);

+ GICv3RedistRegion *region = &s->redist_regions[i];

- memory_region_init_io(&s->iomem_redist[i], OBJECT(s),

- ops ? &ops[1] : NULL, s, name,

+ region->gic = s;

+ region->cpuidx = cpuidx;

+ cpuidx += s->redist_region_count[i];

+

+ memory_region_init_io(&region->iomem, OBJECT(s),

+ ops ? &ops[1] : NULL, region, name,

s->redist_region_count[i] * GICV3_REDIST_SIZE);

- sysbus_init_mmio(sbd, &s->iomem_redist[i]);

+ sysbus_init_mmio(sbd, &region->iomem);

g_free(name);

}

}

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gicv3_kvm.c

+++ b/hw/intc/arm_gicv3_kvm.c

@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)

KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);

if (!multiple_redist_region_allowed) {

- kvm_arm_register_device(&s->iomem_redist[0], -1,

+ kvm_arm_register_device(&s->redist_regions[0].iomem, -1,

KVM_DEV_ARM_VGIC_GRP_ADDR,

KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);

} else {

@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)

uint64_t addr_ormask =

i | ((uint64_t)s->redist_region_count[i] << 52);

- kvm_arm_register_device(&s->iomem_redist[i], -1,

+ kvm_arm_register_device(&s->redist_regions[i].iomem, -1,

KVM_DEV_ARM_VGIC_GRP_ADDR,

KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION,

s->dev_fd, addr_ormask);

diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gicv3_redist.c

+++ b/hw/intc/arm_gicv3_redist.c

@@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset,

MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,

unsigned size, MemTxAttrs attrs)

{

- GICv3State *s = opaque;

+ GICv3RedistRegion *region = opaque;

+ GICv3State *s = region->gic;

GICv3CPUState *cs;

MemTxResult r;

int cpuidx;

assert((offset & (size - 1)) == 0);

- /* This region covers all the redistributor pages; there are

- * (for GICv3) two 64K pages per CPU. At the moment they are

- * all contiguous (ie in this one region), though we might later

- * want to allow splitting of redistributor pages into several

- * blocks so we can support more CPUs.

+ /*

+ * There are (for GICv3) two 64K redistributor pages per CPU.

+ * In some cases the redistributor pages for all CPUs are not

+ * contiguous (eg on the virt board they are split into two

+ * parts if there are too many CPUs to all fit in the same place

+ * in the memory map); if so then the GIC has multiple MemoryRegions

+ * for the redistributors.

*/

- cpuidx = offset / 0x20000;

- offset %= 0x20000;

- assert(cpuidx < s->num_cpu);

+ cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;

+ offset %= GICV3_REDIST_SIZE;

cs = &s->cpu[cpuidx];

@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,

MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,

unsigned size, MemTxAttrs attrs)

{

- GICv3State *s = opaque;

+ GICv3RedistRegion *region = opaque;

+ GICv3State *s = region->gic;

GICv3CPUState *cs;

MemTxResult r;

int cpuidx;

assert((offset & (size - 1)) == 0);

- /* This region covers all the redistributor pages; there are

- * (for GICv3) two 64K pages per CPU. At the moment they are

- * all contiguous (ie in this one region), though we might later

- * want to allow splitting of redistributor pages into several

- * blocks so we can support more CPUs.

+ /*

+ * There are (for GICv3) two 64K redistributor pages per CPU.

+ * In some cases the redistributor pages for all CPUs are not

+ * contiguous (eg on the virt board they are split into two

+ * parts if there are too many CPUs to all fit in the same place

+ * in the memory map); if so then the GIC has multiple MemoryRegions

+ * for the redistributors.

*/

- cpuidx = offset / 0x20000;

- offset %= 0x20000;

- assert(cpuidx < s->num_cpu);

+ cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;

+ offset %= GICV3_REDIST_SIZE;

cs = &s->cpu[cpuidx];

--

2.25.1

The PL031 currently is not able to report guest RTC change to the QMP

monitor as opposed to mc146818 or spapr RTCs. This patch adds the call

to qapi_event_send_rtc_change() when the Load Register is written. The

value which is reported corresponds to the difference between the guest

reference time and the reference time kept in softmmu/rtc.c.

For instance adding 20s to the guest RTC value will report 20. Adding

an extra 20s to the guest RTC value will report 20 + 20 = 40.

The inclusion of qapi/qapi-types-misc-target.h in hw/rtl/pl031.c

require to compile the PL031 with specific_ss.add() to avoid

./qapi/qapi-types-misc-target.h:18:13: error: attempt to use poisoned

"TARGET_<ARCH>".

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20210920122535.269988-1-eric.auger@redhat.com

hw/rtc/pl031.c | 10 +++++++++-

hw/rtc/meson.build | 2 +-

2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c

--- a/hw/rtc/pl031.c

+++ b/hw/rtc/pl031.c

@@ -XXX,XX +XXX,XX @@

#include "qemu/log.h"

#include "qemu/module.h"

#include "trace.h"

+#include "qapi/qapi-events-misc-target.h"

#define RTC_DR 0x00 /* Data read register */

#define RTC_MR 0x04 /* Match register */

@@ -XXX,XX +XXX,XX @@ static void pl031_write(void * opaque, hwaddr offset,

trace_pl031_write(offset, value);

switch (offset) {

- case RTC_LR:

+ case RTC_LR: {

+ struct tm tm;

s->tick_offset += value - pl031_get_count(s);

+

+ qemu_get_timedate(&tm, s->tick_offset);

+ qapi_event_send_rtc_change(qemu_timedate_diff(&tm));

+

pl031_set_alarm(s);

break;

+ }

case RTC_MR:

s->mr = value;

pl031_set_alarm(s);

diff --git a/hw/rtc/meson.build b/hw/rtc/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/rtc/meson.build

+++ b/hw/rtc/meson.build

@@ -XXX,XX +XXX,XX @@

softmmu_ss.add(when: 'CONFIG_DS1338', if_true: files('ds1338.c'))

softmmu_ss.add(when: 'CONFIG_M41T80', if_true: files('m41t80.c'))

softmmu_ss.add(when: 'CONFIG_M48T59', if_true: files('m48t59.c'))

-softmmu_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c'))

+specific_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c'))

softmmu_ss.add(when: 'CONFIG_TWL92230', if_true: files('twl92230.c'))

softmmu_ss.add(when: ['CONFIG_ISA_BUS', 'CONFIG_M48T59'], if_true: files('m48t59-isa.c'))

softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-rtc.c'))

2.25.1