1
Some Arm bugfixes for rc2...
1
The following changes since commit 3214bec13d8d4c40f707d21d8350d04e4123ae97:
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2
3
thanks
3
Merge tag 'migration-20250110-pull-request' of https://gitlab.com/farosas/qemu into staging (2025-01-10 13:39:19 -0500)
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-- PMM
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6
The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812:
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8
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000)
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4
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are available in the Git repository at:
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are available in the Git repository at:
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6
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250113
13
8
14
for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e:
9
for you to fetch changes up to 435d260e7ec5ff9c79e3e62f1d66ec82d2d691ae:
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10
16
MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000)
11
docs/system/arm/virt: mention specific migration information (2025-01-13 12:35:35 +0000)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* various MAINTAINERS file updates
15
* hw/arm_sysctl: fix extracting 31th bit of val
21
* hw/block/onenand: use qemu_log_mask() for reporting
16
* hw/misc: cast rpm to uint64_t
22
* hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
17
* tests/qtest/boot-serial-test: Improve ASM
23
on the n800 and n810 machine models
18
* target/arm: Move minor arithmetic helpers out of helper.c
24
* target/arm: fix smc incorrectly trapping to EL3 when secure is off
19
* target/arm: change default pauth algorithm to impdef
25
* hw/arm/stm32f205: Fix the UART and Timer region size
26
* target/arm: read ID registers for KVM guests so they can be
27
used to gate "is feature X present" checks
28
20
29
----------------------------------------------------------------
21
----------------------------------------------------------------
30
Luc Michel (1):
22
Anastasia Belova (1):
31
target/arm: fix smc incorrectly trapping to EL3 when secure is off
23
hw/arm_sysctl: fix extracting 31th bit of val
32
24
33
Peter Maydell (3):
25
Peter Maydell (2):
34
hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
26
target/arm: Move minor arithmetic helpers out of helper.c
35
hw/block/onenand: use qemu_log_mask() for reporting
27
tests/tcg/aarch64: force qarma5 for pauth-3 test
36
MAINTAINERS: list myself as maintainer for various Arm boards
37
28
38
Richard Henderson (4):
29
Philippe Mathieu-Daudé (4):
39
target/arm: Install ARMISARegisters from kvm host
30
tests/qtest/boot-serial-test: Improve ASM comments of PL011 tests
40
target/arm: Fill in ARMISARegisters for kvm64
31
tests/qtest/boot-serial-test: Reduce for() loop in PL011 tests
41
target/arm: Introduce read_sys_reg32 for kvm32
32
tests/qtest/boot-serial-test: Reorder pair of instructions in PL011 test
42
target/arm: Fill in ARMISARegisters for kvm32
33
tests/qtest/boot-serial-test: Initialize PL011 Control register
43
34
44
Seth Kintigh (1):
35
Pierrick Bouvier (3):
45
hw/arm/stm32f205: Fix the UART and Timer region size
36
target/arm: add new property to select pauth-qarma5
37
target/arm: change default pauth algorithm to impdef
38
docs/system/arm/virt: mention specific migration information
46
39
47
Thomas Huth (1):
40
Tigran Sogomonian (1):
48
MAINTAINERS: Add entries for missing ARM boards
41
hw/misc: cast rpm to uint64_t
49
42
50
target/arm/kvm_arm.h | 1 +
43
docs/system/arm/cpu-features.rst | 7 +-
51
hw/block/onenand.c | 24 +++++-----
44
docs/system/arm/virt.rst | 4 +
52
hw/char/stm32f2xx_usart.c | 2 +-
45
docs/system/introduction.rst | 2 +-
53
hw/timer/stm32f2xx_timer.c | 2 +-
46
target/arm/cpu.h | 4 +
54
target/arm/kvm.c | 1 +
47
hw/core/machine.c | 4 +-
55
target/arm/kvm32.c | 77 ++++++++++++++++++++------------
48
hw/misc/arm_sysctl.c | 2 +-
56
target/arm/kvm64.c | 90 +++++++++++++++++++++++++++++++++++++-
49
hw/misc/npcm7xx_mft.c | 5 +-
57
target/arm/op_helper.c | 54 +++++++++++++++++++----
50
target/arm/arm-qmp-cmds.c | 2 +-
58
MAINTAINERS | 106 +++++++++++++++++++++++++++++++++++++++------
51
target/arm/cpu.c | 2 +
59
9 files changed, 293 insertions(+), 64 deletions(-)
52
target/arm/cpu64.c | 38 ++-
53
target/arm/helper.c | 285 -----------------------
54
target/arm/tcg/arith_helper.c | 296 ++++++++++++++++++++++++
55
tests/qtest/arm-cpu-features.c | 15 +-
56
tests/qtest/boot-serial-test.c | 23 +-
57
target/arm/{op_addsub.h => tcg/op_addsub.c.inc} | 0
58
target/arm/tcg/meson.build | 1 +
59
tests/tcg/aarch64/Makefile.softmmu-target | 3 +
60
17 files changed, 377 insertions(+), 316 deletions(-)
61
create mode 100644 target/arm/tcg/arith_helper.c
62
rename target/arm/{op_addsub.h => tcg/op_addsub.c.inc} (100%)
60
63
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Anastasia Belova <abelova@astralinux.ru>
2
2
3
Assert that the value to be written is the correct size.
3
1 << 31 is casted to uint64_t while bitwise and with val.
4
No change in functionality here, just mirroring the same
4
So this value may become 0xffffffff80000000 but only
5
function from kvm64.
5
31th "start" bit is required.
6
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
This is not possible in practice because the MemoryRegionOps
8
Message-id: 20181113180154.17903-4-richard.henderson@linaro.org
8
uses the default max access size of 4 bytes and so none
9
of the upper bytes of val will be set, but the bitfield
10
extract API is clearer anyway.
11
12
Use the bitfield extract() API instead.
13
14
Found by Linux Verification Center (linuxtesting.org) with SVACE.
15
16
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
17
Message-id: 20241220125429.7552-1-abelova@astralinux.ru
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
[PMM: add clarification to commit message]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
21
---
12
target/arm/kvm32.c | 41 ++++++++++++++++-------------------------
22
hw/misc/arm_sysctl.c | 2 +-
13
1 file changed, 16 insertions(+), 25 deletions(-)
23
1 file changed, 1 insertion(+), 1 deletion(-)
14
24
15
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
25
diff --git a/hw/misc/arm_sysctl.c b/hw/misc/arm_sysctl.c
16
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/kvm32.c
27
--- a/hw/misc/arm_sysctl.c
18
+++ b/target/arm/kvm32.c
28
+++ b/hw/misc/arm_sysctl.c
19
@@ -XXX,XX +XXX,XX @@ static inline void set_feature(uint64_t *features, int feature)
29
@@ -XXX,XX +XXX,XX @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
20
*features |= 1ULL << feature;
30
* as zero.
21
}
31
*/
22
32
s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
23
+static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
33
- if (val & (1 << 31)) {
24
+{
34
+ if (extract64(val, 31, 1)) {
25
+ struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
35
/* Start bit set -- actually do something */
26
+
36
unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
27
+ assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
37
unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
28
+ return ioctl(fd, KVM_GET_ONE_REG, &idreg);
29
+}
30
+
31
bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
32
{
33
/* Identify the feature bits corresponding to the host CPU, and
34
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
35
* we have to create a scratch VM, create a single CPU inside it,
36
* and then query that CPU for the relevant ID registers.
37
*/
38
- int i, ret, fdarray[3];
39
+ int err = 0, fdarray[3];
40
uint32_t midr, id_pfr0, mvfr1;
41
uint64_t features = 0;
42
+
43
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
44
* we know these will only support creating one kind of guest CPU,
45
* which is its preferred CPU type.
46
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
47
QEMU_KVM_ARM_TARGET_NONE
48
};
49
struct kvm_vcpu_init init;
50
- struct kvm_one_reg idregs[] = {
51
- {
52
- .id = KVM_REG_ARM | KVM_REG_SIZE_U32
53
- | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0),
54
- .addr = (uintptr_t)&midr,
55
- },
56
- {
57
- .id = KVM_REG_ARM | KVM_REG_SIZE_U32
58
- | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0),
59
- .addr = (uintptr_t)&id_pfr0,
60
- },
61
- {
62
- .id = KVM_REG_ARM | KVM_REG_SIZE_U32
63
- | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
64
- .addr = (uintptr_t)&mvfr1,
65
- },
66
- };
67
68
if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
69
return false;
70
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
71
*/
72
ahcf->dtb_compatible = "arm,arm-v7";
73
74
- for (i = 0; i < ARRAY_SIZE(idregs); i++) {
75
- ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
76
- if (ret) {
77
- break;
78
- }
79
- }
80
+ err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
81
+ err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
82
+ err |= read_sys_reg32(fdarray[2], &mvfr1,
83
+ KVM_REG_ARM | KVM_REG_SIZE_U32 |
84
+ KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
85
86
kvm_arm_destroy_scratch_host_vcpu(fdarray);
87
88
- if (ret) {
89
+ if (err < 0) {
90
return false;
91
}
92
93
--
38
--
94
2.19.1
39
2.34.1
95
96
diff view generated by jsdifflib
1
From: Luc Michel <luc.michel@greensocs.com>
1
From: Tigran Sogomonian <tsogomonian@astralinux.ru>
2
2
3
This commit fixes a case where the CPU would try to go to EL3 when
3
The value of an arithmetic expression
4
executing an smc instruction, even though ARM_FEATURE_EL3 is false. This
4
'rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION' is a subject
5
case is raised when the PSCI conduit is set to smc, but the smc
5
to overflow because its operands are not cast to
6
instruction does not lead to a valid PSCI call.
6
a larger data type before performing arithmetic. Thus, need
7
to cast rpm to uint64_t.
7
8
8
QEMU crashes with an assertion failure latter on because of incoherent
9
Found by Linux Verification Center (linuxtesting.org) with SVACE.
9
mmu_idx.
10
10
11
This commit refactors the pre_smc helper by enumerating all the possible
11
Signed-off-by: Tigran Sogomonian <tsogomonian@astralinux.ru>
12
way of handling an scm instruction, and covering the previously missing
12
Reviewed-by: Patrick Leis <venture@google.com>
13
case leading to the crash.
13
Reviewed-by: Hao Wu <wuhaotsh@google.com>
14
14
Message-id: 20241226130311.1349-1-tsogomonian@astralinux.ru
15
The following minimal test would crash before this commit:
16
17
.global _start
18
.text
19
_start:
20
ldr x0, =0xdeadbeef ; invalid PSCI call
21
smc #0
22
23
run with the following command line:
24
25
aarch64-linux-gnu-gcc -nostdinc -nostdlib -Wl,-Ttext=40000000 \
26
-o test test.s
27
28
qemu-system-aarch64 -M virt,virtualization=on,secure=off \
29
-cpu cortex-a57 -kernel test
30
31
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
32
Message-id: 20181117160213.18995-1-luc.michel@greensocs.com
33
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
---
16
---
36
target/arm/op_helper.c | 54 +++++++++++++++++++++++++++++++++++-------
17
hw/misc/npcm7xx_mft.c | 5 +++--
37
1 file changed, 46 insertions(+), 8 deletions(-)
18
1 file changed, 3 insertions(+), 2 deletions(-)
38
19
39
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
20
diff --git a/hw/misc/npcm7xx_mft.c b/hw/misc/npcm7xx_mft.c
40
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/op_helper.c
22
--- a/hw/misc/npcm7xx_mft.c
42
+++ b/target/arm/op_helper.c
23
+++ b/hw/misc/npcm7xx_mft.c
43
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
24
@@ -XXX,XX +XXX,XX @@ static NPCM7xxMFTCaptureState npcm7xx_mft_compute_cnt(
44
ARMCPU *cpu = arm_env_get_cpu(env);
25
* RPM = revolution/min. The time for one revlution (in ns) is
45
int cur_el = arm_current_el(env);
26
* MINUTE_TO_NANOSECOND / RPM.
46
bool secure = arm_is_secure(env);
47
- bool smd = env->cp15.scr_el3 & SCR_SMD;
48
+ bool smd_flag = env->cp15.scr_el3 & SCR_SMD;
49
+
50
+ /*
51
+ * SMC behaviour is summarized in the following table.
52
+ * This helper handles the "Trap to EL2" and "Undef insn" cases.
53
+ * The "Trap to EL3" and "PSCI call" cases are handled in the exception
54
+ * helper.
55
+ *
56
+ * -> ARM_FEATURE_EL3 and !SMD
57
+ * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
58
+ *
59
+ * Conduit SMC, valid call Trap to EL2 PSCI Call
60
+ * Conduit SMC, inval call Trap to EL2 Trap to EL3
61
+ * Conduit not SMC Trap to EL2 Trap to EL3
62
+ *
63
+ *
64
+ * -> ARM_FEATURE_EL3 and SMD
65
+ * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
66
+ *
67
+ * Conduit SMC, valid call Trap to EL2 PSCI Call
68
+ * Conduit SMC, inval call Trap to EL2 Undef insn
69
+ * Conduit not SMC Trap to EL2 Undef insn
70
+ *
71
+ *
72
+ * -> !ARM_FEATURE_EL3
73
+ * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1
74
+ *
75
+ * Conduit SMC, valid call Trap to EL2 PSCI Call
76
+ * Conduit SMC, inval call Trap to EL2 Undef insn
77
+ * Conduit not SMC Undef insn Undef insn
78
+ */
79
+
80
/* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
81
* On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
82
* extensions, SMD only applies to NS state.
83
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
84
* doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
85
* so we need not special case this here.
86
*/
87
- bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure;
88
+ bool smd = arm_feature(env, ARM_FEATURE_AARCH64) ? smd_flag
89
+ : smd_flag && !secure;
90
91
if (!arm_feature(env, ARM_FEATURE_EL3) &&
92
cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
93
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
94
* to forbid its EL1 from making PSCI calls into QEMU's
95
* "firmware" via HCR.TSC, so for these purposes treat
96
* PSCI-via-SMC as implying an EL3.
97
+ * This handles the very last line of the previous table.
98
*/
27
*/
99
- undef = true;
28
- count = clock_ns_to_ticks(clock, (60 * NANOSECONDS_PER_SECOND) /
100
- } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
29
- (rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION));
101
+ raise_exception(env, EXCP_UDEF, syn_uncategorized(),
30
+ count = clock_ns_to_ticks(clock,
102
+ exception_target_el(env));
31
+ (uint64_t)(60 * NANOSECONDS_PER_SECOND) /
103
+ }
32
+ ((uint64_t)rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION));
104
+
105
+ if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
106
/* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
107
* We also want an EL2 guest to be able to forbid its EL1 from
108
* making PSCI calls into QEMU's "firmware" via HCR.TSC.
109
+ * This handles all the "Trap to EL2" cases of the previous table.
110
*/
111
raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
112
}
33
}
113
34
114
- /* If PSCI is enabled and this looks like a valid PSCI call then
35
if (count > NPCM7XX_MFT_MAX_CNT) {
115
- * suppress the UNDEF -- we'll catch the SMC exception and
116
- * implement the PSCI call behaviour there.
117
+ /* Catch the two remaining "Undef insn" cases of the previous table:
118
+ * - PSCI conduit is SMC but we don't have a valid PCSI call,
119
+ * - We don't have EL3 or SMD is set.
120
*/
121
- if (undef && !arm_is_psci_call(cpu, EXCP_SMC)) {
122
+ if (!arm_is_psci_call(cpu, EXCP_SMC) &&
123
+ (smd || !arm_feature(env, ARM_FEATURE_EL3))) {
124
raise_exception(env, EXCP_UDEF, syn_uncategorized(),
125
exception_target_el(env));
126
}
127
--
36
--
128
2.19.1
37
2.34.1
129
130
diff view generated by jsdifflib
1
From: Seth Kintigh <skintigh@gmail.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
The UART and timer devices for the stm32f205 were being created
3
Re-indent ASM comments adding the 'loop:' label.
4
with memory regions that were too large. Use the size specified
5
in the chip datasheet.
6
4
7
The old sizes were so large that the devices would overlap with
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
each other in the SoC memory map, so this fixes a bug that
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
caused odd behavior and/or crashes when trying to set up multiple
7
Reviewed-by: Fabiano Rosas <farosas@suse.de>
10
UARTs.
11
12
Signed-off-by: Seth Kintigh <skintigh@gmail.com>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
[PMM: rephrased commit message to follow our usual standard]
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
9
---
19
hw/char/stm32f2xx_usart.c | 2 +-
10
tests/qtest/boot-serial-test.c | 18 +++++++++---------
20
hw/timer/stm32f2xx_timer.c | 2 +-
11
1 file changed, 9 insertions(+), 9 deletions(-)
21
2 files changed, 2 insertions(+), 2 deletions(-)
22
12
23
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
13
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
24
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/char/stm32f2xx_usart.c
15
--- a/tests/qtest/boot-serial-test.c
26
+++ b/hw/char/stm32f2xx_usart.c
16
+++ b/tests/qtest/boot-serial-test.c
27
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_init(Object *obj)
17
@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_plml605[] = {
28
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
18
};
29
19
30
memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
20
static const uint8_t bios_raspi2[] = {
31
- TYPE_STM32F2XX_USART, 0x2000);
21
- 0x08, 0x30, 0x9f, 0xe5, /* ldr r3,[pc,#8] Get base */
32
+ TYPE_STM32F2XX_USART, 0x400);
22
- 0x54, 0x20, 0xa0, 0xe3, /* mov r2,#'T' */
33
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
23
- 0x00, 0x20, 0xc3, 0xe5, /* strb r2,[r3] */
34
}
24
- 0xfb, 0xff, 0xff, 0xea, /* b loop */
35
25
- 0x00, 0x10, 0x20, 0x3f, /* 0x3f201000 = UART0 base addr */
36
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
26
+ 0x08, 0x30, 0x9f, 0xe5, /* loop: ldr r3, [pc, #8] Get &UART0 */
37
index XXXXXXX..XXXXXXX 100644
27
+ 0x54, 0x20, 0xa0, 0xe3, /* mov r2, #'T' */
38
--- a/hw/timer/stm32f2xx_timer.c
28
+ 0x00, 0x20, 0xc3, 0xe5, /* strb r2, [r3] *TXDAT = 'T' */
39
+++ b/hw/timer/stm32f2xx_timer.c
29
+ 0xfb, 0xff, 0xff, 0xea, /* b -12 (loop) */
40
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_timer_init(Object *obj)
30
+ 0x00, 0x10, 0x20, 0x3f, /* UART0: 0x3f201000 */
41
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
31
};
42
32
43
memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
33
static const uint8_t kernel_aarch64[] = {
44
- "stm32f2xx_timer", 0x4000);
34
- 0x81, 0x0a, 0x80, 0x52, /* mov w1, #0x54 */
45
+ "stm32f2xx_timer", 0x400);
35
- 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 */
46
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
36
- 0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] */
47
37
- 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */
48
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
38
+ 0x81, 0x0a, 0x80, 0x52, /* loop: mov w1, #'T' */
39
+ 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */
40
+ 0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] *TXDAT = 'T' */
41
+ 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */
42
};
43
44
static const uint8_t kernel_nrf51[] = {
49
--
45
--
50
2.19.1
46
2.34.1
51
47
52
48
diff view generated by jsdifflib
1
From: Thomas Huth <thuth@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Add entries for the boards "mcimx6ul-evk", "mcimx7d-sabre", "raspi2",
3
Since registers are not modified, we don't need
4
"raspi3", "sabrelite", "vexpress-a15", "vexpress-a9" and "virt".
4
to refill their values. Directly jump to the previous
5
While we're at it, also adjust the "i.MX31" section a little bit,
5
store instruction to keep filling the TXDAT register.
6
so that the wildcards there do not match anymore for unrelated files
7
(e.g. the new hw/misc/imx6ul_ccm.c file).
8
6
9
Signed-off-by: Thomas Huth <thuth@redhat.com>
7
The equivalent C code remains:
10
Message-id: 1542184999-11145-1-git-send-email-thuth@redhat.com
8
9
while (true) {
10
*UART_DATA = 'T';
11
}
12
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Fabiano Rosas <farosas@suse.de>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
17
---
13
MAINTAINERS | 70 +++++++++++++++++++++++++++++++++++++++++++++++++----
18
tests/qtest/boot-serial-test.c | 12 ++++++------
14
1 file changed, 65 insertions(+), 5 deletions(-)
19
1 file changed, 6 insertions(+), 6 deletions(-)
15
20
16
diff --git a/MAINTAINERS b/MAINTAINERS
21
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/MAINTAINERS
23
--- a/tests/qtest/boot-serial-test.c
19
+++ b/MAINTAINERS
24
+++ b/tests/qtest/boot-serial-test.c
20
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
25
@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_plml605[] = {
21
S: Odd Fixes
26
};
22
F: hw/arm/gumstix.c
27
23
28
static const uint8_t bios_raspi2[] = {
24
-i.MX31
29
- 0x08, 0x30, 0x9f, 0xe5, /* loop: ldr r3, [pc, #8] Get &UART0 */
25
+i.MX31 (kzm)
30
+ 0x08, 0x30, 0x9f, 0xe5, /* ldr r3, [pc, #8] Get &UART0 */
26
M: Peter Chubb <peter.chubb@nicta.com.au>
31
0x54, 0x20, 0xa0, 0xe3, /* mov r2, #'T' */
27
L: qemu-arm@nongnu.org
32
- 0x00, 0x20, 0xc3, 0xe5, /* strb r2, [r3] *TXDAT = 'T' */
28
-S: Odd fixes
33
- 0xfb, 0xff, 0xff, 0xea, /* b -12 (loop) */
29
-F: hw/*/imx*
34
+ 0x00, 0x20, 0xc3, 0xe5, /* loop: strb r2, [r3] *TXDAT = 'T' */
30
-F: include/hw/*/imx*
35
+ 0xff, 0xff, 0xff, 0xea, /* b -4 (loop) */
31
+S: Odd Fixes
36
0x00, 0x10, 0x20, 0x3f, /* UART0: 0x3f201000 */
32
F: hw/arm/kzm.c
37
};
33
-F: include/hw/arm/fsl-imx31.h
38
34
+F: hw/*/imx_*
39
static const uint8_t kernel_aarch64[] = {
35
+F: hw/*/*imx31*
40
- 0x81, 0x0a, 0x80, 0x52, /* loop: mov w1, #'T' */
36
+F: include/hw/*/imx_*
41
+ 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */
37
+F: include/hw/*/*imx31*
42
0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */
38
43
- 0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] *TXDAT = 'T' */
39
Integrator CP
44
- 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */
40
M: Peter Maydell <peter.maydell@linaro.org>
45
+ 0x41, 0x00, 0x00, 0x39, /* loop: strb w1, [x2] *TXDAT = 'T' */
41
@@ -XXX,XX +XXX,XX @@ S: Maintained
46
+ 0xff, 0xff, 0xff, 0x17, /* b -4 (loop) */
42
F: hw/arm/integratorcp.c
47
};
43
F: hw/misc/arm_integrator_debug.c
48
44
49
static const uint8_t kernel_nrf51[] = {
45
+MCIMX6UL EVK / i.MX6ul
46
+M: Peter Maydell <peter.maydell@linaro.org>
47
+R: Jean-Christophe Dubois <jcd@tribudubois.net>
48
+L: qemu-arm@nongnu.org
49
+S: Odd Fixes
50
+F: hw/arm/mcimx6ul-evk.c
51
+F: hw/arm/fsl-imx6ul.c
52
+F: hw/misc/imx6ul_ccm.c
53
+F: include/hw/arm/fsl-imx6ul.h
54
+F: include/hw/misc/imx6ul_ccm.h
55
+
56
+MCIMX7D SABRE / i.MX7
57
+M: Peter Maydell <peter.maydell@linaro.org>
58
+R: Andrey Smirnov <andrew.smirnov@gmail.com>
59
+L: qemu-arm@nongnu.org
60
+S: Odd Fixes
61
+F: hw/arm/mcimx7d-sabre.c
62
+F: hw/arm/fsl-imx7.c
63
+F: include/hw/arm/fsl-imx7.h
64
+F: hw/pci-host/designware.c
65
+F: include/hw/pci-host/designware.h
66
+
67
MPS2
68
M: Peter Maydell <peter.maydell@linaro.org>
69
L: qemu-arm@nongnu.org
70
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
71
S: Maintained
72
F: hw/arm/palm.c
73
74
+Raspberry Pi
75
+M: Peter Maydell <peter.maydell@linaro.org>
76
+R: Andrew Baumann <Andrew.Baumann@microsoft.com>
77
+R: Philippe Mathieu-Daudé <f4bug@amsat.org>
78
+L: qemu-arm@nongnu.org
79
+S: Odd Fixes
80
+F: hw/arm/raspi_platform.h
81
+F: hw/*/bcm283*
82
+F: include/hw/arm/raspi*
83
+F: include/hw/*/bcm283*
84
+
85
Real View
86
M: Peter Maydell <peter.maydell@linaro.org>
87
L: qemu-arm@nongnu.org
88
@@ -XXX,XX +XXX,XX @@ F: hw/*/pxa2xx*
89
F: hw/misc/mst_fpga.c
90
F: include/hw/arm/pxa.h
91
92
+SABRELITE / i.MX6
93
+M: Peter Maydell <peter.maydell@linaro.org>
94
+R: Jean-Christophe Dubois <jcd@tribudubois.net>
95
+L: qemu-arm@nongnu.org
96
+S: Odd Fixes
97
+F: hw/arm/sabrelite.c
98
+F: hw/arm/fsl-imx6.c
99
+F: hw/misc/imx6_src.c
100
+F: hw/ssi/imx_spi.c
101
+F: include/hw/arm/fsl-imx6.h
102
+F: include/hw/misc/imx6_src.h
103
+F: include/hw/ssi/imx_spi.h
104
+
105
Sharp SL-5500 (Collie) PDA
106
M: Peter Maydell <peter.maydell@linaro.org>
107
L: qemu-arm@nongnu.org
108
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
109
S: Maintained
110
F: hw/*/stellaris*
111
112
+Versatile Express
113
+M: Peter Maydell <peter.maydell@linaro.org>
114
+L: qemu-arm@nongnu.org
115
+S: Maintained
116
+F: hw/arm/vexpress.c
117
+
118
Versatile PB
119
M: Peter Maydell <peter.maydell@linaro.org>
120
L: qemu-arm@nongnu.org
121
@@ -XXX,XX +XXX,XX @@ S: Maintained
122
F: hw/*/versatile*
123
F: hw/misc/arm_sysctl.c
124
125
+Virt
126
+M: Peter Maydell <peter.maydell@linaro.org>
127
+L: qemu-arm@nongnu.org
128
+S: Maintained
129
+F: hw/arm/virt*
130
+F: include/hw/arm/virt.h
131
+
132
Xilinx Zynq
133
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
134
M: Alistair Francis <alistair@alistair23.me>
135
--
50
--
136
2.19.1
51
2.34.1
137
52
138
53
diff view generated by jsdifflib
1
An off-by-one error in a switch case in onenand_read() allowed
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
a misbehaving guest to read off the end of a block of memory.
3
2
4
NB: the onenand device is used only by the "n800" and "n810"
3
In the next commit we are going to use a different value
5
machines, which are usable only with TCG, not KVM, so this is
4
for the $w1 register, maintaining the same $x2 value. In
6
not a security issue.
5
order to keep the next commit trivial to review, set $x2
6
before $w1.
7
7
8
Reported-by: Thomas Huth <thuth@redhat.com>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Fabiano Rosas <farosas@suse.de>
12
Message-id: 20181115143535.5885-2-peter.maydell@linaro.org
13
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
hw/block/onenand.c | 2 +-
13
tests/qtest/boot-serial-test.c | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
18
15
19
diff --git a/hw/block/onenand.c b/hw/block/onenand.c
16
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/block/onenand.c
18
--- a/tests/qtest/boot-serial-test.c
22
+++ b/hw/block/onenand.c
19
+++ b/tests/qtest/boot-serial-test.c
23
@@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
20
@@ -XXX,XX +XXX,XX @@ static const uint8_t bios_raspi2[] = {
24
int offset = addr >> s->shift;
21
};
25
22
26
switch (offset) {
23
static const uint8_t kernel_aarch64[] = {
27
- case 0x0000 ... 0xc000:
24
- 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */
28
+ case 0x0000 ... 0xbffe:
25
0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */
29
return lduw_le_p(s->boot[0] + addr);
26
+ 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */
30
27
0x41, 0x00, 0x00, 0x39, /* loop: strb w1, [x2] *TXDAT = 'T' */
31
case 0xf000:    /* Manufacturer ID */
28
0xff, 0xff, 0xff, 0x17, /* b -4 (loop) */
29
};
32
--
30
--
33
2.19.1
31
2.34.1
34
32
35
33
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
The tests using the PL011 UART of the virt and raspi machines
4
Message-id: 20181113180154.17903-5-richard.henderson@linaro.org
4
weren't properly enabling the UART and its transmitter previous
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
to sending characters. Follow the PL011 manual initialization
6
recommendation by setting the proper bits of the control register.
7
8
Update the ASM code prefixing:
9
10
*UART_CTRL = UART_ENABLE | TX_ENABLE;
11
12
to:
13
14
while (true) {
15
*UART_DATA = 'T';
16
}
17
18
Note, since commit 51b61dd4d56 ("hw/char/pl011: Warn when using
19
disabled transmitter") incomplete PL011 initialization can be
20
logged using the '-d guest_errors' command line option.
21
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
25
---
8
target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++-----
26
tests/qtest/boot-serial-test.c | 7 ++++++-
9
1 file changed, 35 insertions(+), 5 deletions(-)
27
1 file changed, 6 insertions(+), 1 deletion(-)
10
28
11
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
29
diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
12
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/kvm32.c
31
--- a/tests/qtest/boot-serial-test.c
14
+++ b/target/arm/kvm32.c
32
+++ b/tests/qtest/boot-serial-test.c
15
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
33
@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_plml605[] = {
16
* and then query that CPU for the relevant ID registers.
34
};
17
*/
35
18
int err = 0, fdarray[3];
36
static const uint8_t bios_raspi2[] = {
19
- uint32_t midr, id_pfr0, mvfr1;
37
- 0x08, 0x30, 0x9f, 0xe5, /* ldr r3, [pc, #8] Get &UART0 */
20
+ uint32_t midr, id_pfr0;
38
+ 0x10, 0x30, 0x9f, 0xe5, /* ldr r3, [pc, #16] Get &UART0 */
21
uint64_t features = 0;
39
+ 0x10, 0x20, 0x9f, 0xe5, /* ldr r2, [pc, #16] Get &CR */
22
40
+ 0xb0, 0x23, 0xc3, 0xe1, /* strh r2, [r3, #48] Set CR */
23
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
41
0x54, 0x20, 0xa0, 0xe3, /* mov r2, #'T' */
24
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
42
0x00, 0x20, 0xc3, 0xe5, /* loop: strb r2, [r3] *TXDAT = 'T' */
25
43
0xff, 0xff, 0xff, 0xea, /* b -4 (loop) */
26
err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
44
0x00, 0x10, 0x20, 0x3f, /* UART0: 0x3f201000 */
27
err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
45
+ 0x01, 0x01, 0x00, 0x00, /* CR: 0x101 = UARTEN|TXE */
28
- err |= read_sys_reg32(fdarray[2], &mvfr1,
46
};
29
+
47
30
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
48
static const uint8_t kernel_aarch64[] = {
31
+ ARM_CP15_REG32(0, 0, 2, 0));
49
0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */
32
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
50
+ 0x21, 0x20, 0x80, 0x52, /* mov w1, 0x101 CR = UARTEN|TXE */
33
+ ARM_CP15_REG32(0, 0, 2, 1));
51
+ 0x41, 0x60, 0x00, 0x79, /* strh w1, [x2, #48] Set CR */
34
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
52
0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */
35
+ ARM_CP15_REG32(0, 0, 2, 2));
53
0x41, 0x00, 0x00, 0x39, /* loop: strb w1, [x2] *TXDAT = 'T' */
36
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
54
0xff, 0xff, 0xff, 0x17, /* b -4 (loop) */
37
+ ARM_CP15_REG32(0, 0, 2, 3));
38
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
39
+ ARM_CP15_REG32(0, 0, 2, 4));
40
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
41
+ ARM_CP15_REG32(0, 0, 2, 5));
42
+ if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
43
+ ARM_CP15_REG32(0, 0, 2, 7))) {
44
+ /*
45
+ * Older kernels don't support reading ID_ISAR6. This register was
46
+ * only introduced in ARMv8, so we can assume that it is zero on a
47
+ * CPU that a kernel this old is running on.
48
+ */
49
+ ahcf->isar.id_isar6 = 0;
50
+ }
51
+
52
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
53
+ KVM_REG_ARM | KVM_REG_SIZE_U32 |
54
+ KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
55
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
56
KVM_REG_ARM | KVM_REG_SIZE_U32 |
57
KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
58
+ /*
59
+ * FIXME: There is not yet a way to read MVFR2.
60
+ * Fortunately there is not yet anything in there that affects migration.
61
+ */
62
63
kvm_arm_destroy_scratch_host_vcpu(fdarray);
64
65
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
66
if (extract32(id_pfr0, 12, 4) == 1) {
67
set_feature(&features, ARM_FEATURE_THUMB2EE);
68
}
69
- if (extract32(mvfr1, 20, 4) == 1) {
70
+ if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
71
set_feature(&features, ARM_FEATURE_VFP_FP16);
72
}
73
- if (extract32(mvfr1, 12, 4) == 1) {
74
+ if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
75
set_feature(&features, ARM_FEATURE_NEON);
76
}
77
- if (extract32(mvfr1, 28, 4) == 1) {
78
+ if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
79
/* FMAC support implies VFPv4 */
80
set_feature(&features, ARM_FEATURE_VFP4);
81
}
82
--
55
--
83
2.19.1
56
2.34.1
84
57
85
58
diff view generated by jsdifflib
1
Update the onenand device to use qemu_log_mask() for reporting
1
helper.c includes some small TCG helper functions used for mostly
2
guest errors and unimplemented features, rather than plain
2
arithmetic instructions. These are TCG only and there's no need for
3
fprintf() and hw_error().
3
them to be in the large and unwieldy helper.c. Move them out to
4
their own source file in the tcg/ subdirectory, together with the
5
op_addsub.h multiply-included template header that they use.
4
6
5
(We leave the hw_error() in onenand_reset(), as that is
7
Since we are moving op_addsub.h, we take the opportunity to
6
triggered by a failure to read the underlying block device
8
give it a name which matches our convention for files which
7
for the bootRAM, not by guest action.)
9
are not true header files but which are #included from other
10
C files: op_addsub.c.inc.
11
12
(Ironically, this means that helper.c no longer contains
13
any TCG helper function definitions at all.)
8
14
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20250110131211.2546314-1-peter.maydell@linaro.org
13
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
18
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20181115143535.5885-3-peter.maydell@linaro.org
15
---
19
---
16
hw/block/onenand.c | 22 +++++++++++++---------
20
target/arm/helper.c | 285 -----------------
17
1 file changed, 13 insertions(+), 9 deletions(-)
21
target/arm/tcg/arith_helper.c | 296 ++++++++++++++++++
22
.../arm/{op_addsub.h => tcg/op_addsub.c.inc} | 0
23
target/arm/tcg/meson.build | 1 +
24
4 files changed, 297 insertions(+), 285 deletions(-)
25
create mode 100644 target/arm/tcg/arith_helper.c
26
rename target/arm/{op_addsub.h => tcg/op_addsub.c.inc} (100%)
18
27
19
diff --git a/hw/block/onenand.c b/hw/block/onenand.c
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/block/onenand.c
30
--- a/target/arm/helper.c
22
+++ b/hw/block/onenand.c
31
+++ b/target/arm/helper.c
23
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
24
#include "exec/memory.h"
33
#include "qemu/main-loop.h"
25
#include "hw/sysbus.h"
34
#include "qemu/timer.h"
26
#include "qemu/error-report.h"
35
#include "qemu/bitops.h"
27
+#include "qemu/log.h"
36
-#include "qemu/crc32c.h"
28
37
#include "qemu/qemu-print.h"
29
/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
38
#include "exec/exec-all.h"
30
#define PAGE_SHIFT    11
39
#include "exec/translation-block.h"
31
@@ -XXX,XX +XXX,XX @@ static void onenand_command(OneNANDState *s)
40
-#include <zlib.h> /* for crc32 */
32
default:
41
#include "hw/irq.h"
33
s->status |= ONEN_ERR_CMD;
42
#include "system/cpu-timers.h"
34
s->intstatus |= ONEN_INT;
43
#include "system/kvm.h"
35
- fprintf(stderr, "%s: unknown OneNAND command %x\n",
44
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
36
- __func__, s->command);
45
};
37
+ qemu_log_mask(LOG_GUEST_ERROR, "unknown OneNAND command %x\n",
38
+ s->command);
39
}
40
41
onenand_intr_update(s);
42
@@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
43
case 0xff02:    /* ECC Result of spare area data */
44
case 0xff03:    /* ECC Result of main area data */
45
case 0xff04:    /* ECC Result of spare area data */
46
- hw_error("%s: implement ECC\n", __func__);
47
+ qemu_log_mask(LOG_UNIMP,
48
+ "onenand: ECC result registers unimplemented\n");
49
return 0x0000;
50
}
51
52
- fprintf(stderr, "%s: unknown OneNAND register %x\n",
53
- __func__, offset);
54
+ qemu_log_mask(LOG_GUEST_ERROR, "read of unknown OneNAND register 0x%x\n",
55
+ offset);
56
return 0;
57
}
46
}
58
47
59
@@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr,
48
-/*
60
break;
49
- * Note that signed overflow is undefined in C. The following routines are
61
50
- * careful to use unsigned types where modulo arithmetic is required.
62
default:
51
- * Failure to do so _will_ break on newer gcc.
63
- fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
52
- */
64
- __func__, value);
53
-
65
+ qemu_log_mask(LOG_GUEST_ERROR,
54
-/* Signed saturating arithmetic. */
66
+ "unknown OneNAND boot command %" PRIx64 "\n",
55
-
67
+ value);
56
-/* Perform 16-bit signed saturating addition. */
68
}
57
-static inline uint16_t add16_sat(uint16_t a, uint16_t b)
69
break;
58
-{
70
59
- uint16_t res;
71
@@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr,
60
-
72
break;
61
- res = a + b;
73
62
- if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
74
default:
63
- if (a & 0x8000) {
75
- fprintf(stderr, "%s: unknown OneNAND register %x\n",
64
- res = 0x8000;
76
- __func__, offset);
65
- } else {
77
+ qemu_log_mask(LOG_GUEST_ERROR,
66
- res = 0x7fff;
78
+ "write to unknown OneNAND register 0x%x\n",
67
- }
79
+ offset);
68
- }
80
}
69
- return res;
81
}
70
-}
82
71
-
72
-/* Perform 8-bit signed saturating addition. */
73
-static inline uint8_t add8_sat(uint8_t a, uint8_t b)
74
-{
75
- uint8_t res;
76
-
77
- res = a + b;
78
- if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
79
- if (a & 0x80) {
80
- res = 0x80;
81
- } else {
82
- res = 0x7f;
83
- }
84
- }
85
- return res;
86
-}
87
-
88
-/* Perform 16-bit signed saturating subtraction. */
89
-static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
90
-{
91
- uint16_t res;
92
-
93
- res = a - b;
94
- if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
95
- if (a & 0x8000) {
96
- res = 0x8000;
97
- } else {
98
- res = 0x7fff;
99
- }
100
- }
101
- return res;
102
-}
103
-
104
-/* Perform 8-bit signed saturating subtraction. */
105
-static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
106
-{
107
- uint8_t res;
108
-
109
- res = a - b;
110
- if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
111
- if (a & 0x80) {
112
- res = 0x80;
113
- } else {
114
- res = 0x7f;
115
- }
116
- }
117
- return res;
118
-}
119
-
120
-#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
121
-#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
122
-#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
123
-#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
124
-#define PFX q
125
-
126
-#include "op_addsub.h"
127
-
128
-/* Unsigned saturating arithmetic. */
129
-static inline uint16_t add16_usat(uint16_t a, uint16_t b)
130
-{
131
- uint16_t res;
132
- res = a + b;
133
- if (res < a) {
134
- res = 0xffff;
135
- }
136
- return res;
137
-}
138
-
139
-static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
140
-{
141
- if (a > b) {
142
- return a - b;
143
- } else {
144
- return 0;
145
- }
146
-}
147
-
148
-static inline uint8_t add8_usat(uint8_t a, uint8_t b)
149
-{
150
- uint8_t res;
151
- res = a + b;
152
- if (res < a) {
153
- res = 0xff;
154
- }
155
- return res;
156
-}
157
-
158
-static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
159
-{
160
- if (a > b) {
161
- return a - b;
162
- } else {
163
- return 0;
164
- }
165
-}
166
-
167
-#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
168
-#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
169
-#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
170
-#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
171
-#define PFX uq
172
-
173
-#include "op_addsub.h"
174
-
175
-/* Signed modulo arithmetic. */
176
-#define SARITH16(a, b, n, op) do { \
177
- int32_t sum; \
178
- sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
179
- RESULT(sum, n, 16); \
180
- if (sum >= 0) \
181
- ge |= 3 << (n * 2); \
182
- } while (0)
183
-
184
-#define SARITH8(a, b, n, op) do { \
185
- int32_t sum; \
186
- sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
187
- RESULT(sum, n, 8); \
188
- if (sum >= 0) \
189
- ge |= 1 << n; \
190
- } while (0)
191
-
192
-
193
-#define ADD16(a, b, n) SARITH16(a, b, n, +)
194
-#define SUB16(a, b, n) SARITH16(a, b, n, -)
195
-#define ADD8(a, b, n) SARITH8(a, b, n, +)
196
-#define SUB8(a, b, n) SARITH8(a, b, n, -)
197
-#define PFX s
198
-#define ARITH_GE
199
-
200
-#include "op_addsub.h"
201
-
202
-/* Unsigned modulo arithmetic. */
203
-#define ADD16(a, b, n) do { \
204
- uint32_t sum; \
205
- sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
206
- RESULT(sum, n, 16); \
207
- if ((sum >> 16) == 1) \
208
- ge |= 3 << (n * 2); \
209
- } while (0)
210
-
211
-#define ADD8(a, b, n) do { \
212
- uint32_t sum; \
213
- sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
214
- RESULT(sum, n, 8); \
215
- if ((sum >> 8) == 1) \
216
- ge |= 1 << n; \
217
- } while (0)
218
-
219
-#define SUB16(a, b, n) do { \
220
- uint32_t sum; \
221
- sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
222
- RESULT(sum, n, 16); \
223
- if ((sum >> 16) == 0) \
224
- ge |= 3 << (n * 2); \
225
- } while (0)
226
-
227
-#define SUB8(a, b, n) do { \
228
- uint32_t sum; \
229
- sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
230
- RESULT(sum, n, 8); \
231
- if ((sum >> 8) == 0) \
232
- ge |= 1 << n; \
233
- } while (0)
234
-
235
-#define PFX u
236
-#define ARITH_GE
237
-
238
-#include "op_addsub.h"
239
-
240
-/* Halved signed arithmetic. */
241
-#define ADD16(a, b, n) \
242
- RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
243
-#define SUB16(a, b, n) \
244
- RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
245
-#define ADD8(a, b, n) \
246
- RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
247
-#define SUB8(a, b, n) \
248
- RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
249
-#define PFX sh
250
-
251
-#include "op_addsub.h"
252
-
253
-/* Halved unsigned arithmetic. */
254
-#define ADD16(a, b, n) \
255
- RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
256
-#define SUB16(a, b, n) \
257
- RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
258
-#define ADD8(a, b, n) \
259
- RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
260
-#define SUB8(a, b, n) \
261
- RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
262
-#define PFX uh
263
-
264
-#include "op_addsub.h"
265
-
266
-static inline uint8_t do_usad(uint8_t a, uint8_t b)
267
-{
268
- if (a > b) {
269
- return a - b;
270
- } else {
271
- return b - a;
272
- }
273
-}
274
-
275
-/* Unsigned sum of absolute byte differences. */
276
-uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
277
-{
278
- uint32_t sum;
279
- sum = do_usad(a, b);
280
- sum += do_usad(a >> 8, b >> 8);
281
- sum += do_usad(a >> 16, b >> 16);
282
- sum += do_usad(a >> 24, b >> 24);
283
- return sum;
284
-}
285
-
286
-/* For ARMv6 SEL instruction. */
287
-uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
288
-{
289
- uint32_t mask;
290
-
291
- mask = 0;
292
- if (flags & 1) {
293
- mask |= 0xff;
294
- }
295
- if (flags & 2) {
296
- mask |= 0xff00;
297
- }
298
- if (flags & 4) {
299
- mask |= 0xff0000;
300
- }
301
- if (flags & 8) {
302
- mask |= 0xff000000;
303
- }
304
- return (a & mask) | (b & ~mask);
305
-}
306
-
307
-/*
308
- * CRC helpers.
309
- * The upper bytes of val (above the number specified by 'bytes') must have
310
- * been zeroed out by the caller.
311
- */
312
-uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
313
-{
314
- uint8_t buf[4];
315
-
316
- stl_le_p(buf, val);
317
-
318
- /* zlib crc32 converts the accumulator and output to one's complement. */
319
- return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
320
-}
321
-
322
-uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
323
-{
324
- uint8_t buf[4];
325
-
326
- stl_le_p(buf, val);
327
-
328
- /* Linux crc32c converts the output to one's complement. */
329
- return crc32c(acc, buf, bytes) ^ 0xffffffff;
330
-}
331
332
/*
333
* Return the exception level to which FP-disabled exceptions should
334
diff --git a/target/arm/tcg/arith_helper.c b/target/arm/tcg/arith_helper.c
335
new file mode 100644
336
index XXXXXXX..XXXXXXX
337
--- /dev/null
338
+++ b/target/arm/tcg/arith_helper.c
339
@@ -XXX,XX +XXX,XX @@
340
+/*
341
+ * ARM generic helpers for various arithmetical operations.
342
+ *
343
+ * This code is licensed under the GNU GPL v2 or later.
344
+ *
345
+ * SPDX-License-Identifier: GPL-2.0-or-later
346
+ */
347
+#include "qemu/osdep.h"
348
+#include "cpu.h"
349
+#include "exec/helper-proto.h"
350
+#include "qemu/crc32c.h"
351
+#include <zlib.h> /* for crc32 */
352
+
353
+/*
354
+ * Note that signed overflow is undefined in C. The following routines are
355
+ * careful to use unsigned types where modulo arithmetic is required.
356
+ * Failure to do so _will_ break on newer gcc.
357
+ */
358
+
359
+/* Signed saturating arithmetic. */
360
+
361
+/* Perform 16-bit signed saturating addition. */
362
+static inline uint16_t add16_sat(uint16_t a, uint16_t b)
363
+{
364
+ uint16_t res;
365
+
366
+ res = a + b;
367
+ if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
368
+ if (a & 0x8000) {
369
+ res = 0x8000;
370
+ } else {
371
+ res = 0x7fff;
372
+ }
373
+ }
374
+ return res;
375
+}
376
+
377
+/* Perform 8-bit signed saturating addition. */
378
+static inline uint8_t add8_sat(uint8_t a, uint8_t b)
379
+{
380
+ uint8_t res;
381
+
382
+ res = a + b;
383
+ if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
384
+ if (a & 0x80) {
385
+ res = 0x80;
386
+ } else {
387
+ res = 0x7f;
388
+ }
389
+ }
390
+ return res;
391
+}
392
+
393
+/* Perform 16-bit signed saturating subtraction. */
394
+static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
395
+{
396
+ uint16_t res;
397
+
398
+ res = a - b;
399
+ if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
400
+ if (a & 0x8000) {
401
+ res = 0x8000;
402
+ } else {
403
+ res = 0x7fff;
404
+ }
405
+ }
406
+ return res;
407
+}
408
+
409
+/* Perform 8-bit signed saturating subtraction. */
410
+static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
411
+{
412
+ uint8_t res;
413
+
414
+ res = a - b;
415
+ if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
416
+ if (a & 0x80) {
417
+ res = 0x80;
418
+ } else {
419
+ res = 0x7f;
420
+ }
421
+ }
422
+ return res;
423
+}
424
+
425
+#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
426
+#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
427
+#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
428
+#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
429
+#define PFX q
430
+
431
+#include "op_addsub.c.inc"
432
+
433
+/* Unsigned saturating arithmetic. */
434
+static inline uint16_t add16_usat(uint16_t a, uint16_t b)
435
+{
436
+ uint16_t res;
437
+ res = a + b;
438
+ if (res < a) {
439
+ res = 0xffff;
440
+ }
441
+ return res;
442
+}
443
+
444
+static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
445
+{
446
+ if (a > b) {
447
+ return a - b;
448
+ } else {
449
+ return 0;
450
+ }
451
+}
452
+
453
+static inline uint8_t add8_usat(uint8_t a, uint8_t b)
454
+{
455
+ uint8_t res;
456
+ res = a + b;
457
+ if (res < a) {
458
+ res = 0xff;
459
+ }
460
+ return res;
461
+}
462
+
463
+static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
464
+{
465
+ if (a > b) {
466
+ return a - b;
467
+ } else {
468
+ return 0;
469
+ }
470
+}
471
+
472
+#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
473
+#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
474
+#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
475
+#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
476
+#define PFX uq
477
+
478
+#include "op_addsub.c.inc"
479
+
480
+/* Signed modulo arithmetic. */
481
+#define SARITH16(a, b, n, op) do { \
482
+ int32_t sum; \
483
+ sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
484
+ RESULT(sum, n, 16); \
485
+ if (sum >= 0) \
486
+ ge |= 3 << (n * 2); \
487
+ } while (0)
488
+
489
+#define SARITH8(a, b, n, op) do { \
490
+ int32_t sum; \
491
+ sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
492
+ RESULT(sum, n, 8); \
493
+ if (sum >= 0) \
494
+ ge |= 1 << n; \
495
+ } while (0)
496
+
497
+
498
+#define ADD16(a, b, n) SARITH16(a, b, n, +)
499
+#define SUB16(a, b, n) SARITH16(a, b, n, -)
500
+#define ADD8(a, b, n) SARITH8(a, b, n, +)
501
+#define SUB8(a, b, n) SARITH8(a, b, n, -)
502
+#define PFX s
503
+#define ARITH_GE
504
+
505
+#include "op_addsub.c.inc"
506
+
507
+/* Unsigned modulo arithmetic. */
508
+#define ADD16(a, b, n) do { \
509
+ uint32_t sum; \
510
+ sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
511
+ RESULT(sum, n, 16); \
512
+ if ((sum >> 16) == 1) \
513
+ ge |= 3 << (n * 2); \
514
+ } while (0)
515
+
516
+#define ADD8(a, b, n) do { \
517
+ uint32_t sum; \
518
+ sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
519
+ RESULT(sum, n, 8); \
520
+ if ((sum >> 8) == 1) \
521
+ ge |= 1 << n; \
522
+ } while (0)
523
+
524
+#define SUB16(a, b, n) do { \
525
+ uint32_t sum; \
526
+ sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
527
+ RESULT(sum, n, 16); \
528
+ if ((sum >> 16) == 0) \
529
+ ge |= 3 << (n * 2); \
530
+ } while (0)
531
+
532
+#define SUB8(a, b, n) do { \
533
+ uint32_t sum; \
534
+ sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
535
+ RESULT(sum, n, 8); \
536
+ if ((sum >> 8) == 0) \
537
+ ge |= 1 << n; \
538
+ } while (0)
539
+
540
+#define PFX u
541
+#define ARITH_GE
542
+
543
+#include "op_addsub.c.inc"
544
+
545
+/* Halved signed arithmetic. */
546
+#define ADD16(a, b, n) \
547
+ RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
548
+#define SUB16(a, b, n) \
549
+ RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
550
+#define ADD8(a, b, n) \
551
+ RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
552
+#define SUB8(a, b, n) \
553
+ RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
554
+#define PFX sh
555
+
556
+#include "op_addsub.c.inc"
557
+
558
+/* Halved unsigned arithmetic. */
559
+#define ADD16(a, b, n) \
560
+ RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
561
+#define SUB16(a, b, n) \
562
+ RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
563
+#define ADD8(a, b, n) \
564
+ RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
565
+#define SUB8(a, b, n) \
566
+ RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
567
+#define PFX uh
568
+
569
+#include "op_addsub.c.inc"
570
+
571
+static inline uint8_t do_usad(uint8_t a, uint8_t b)
572
+{
573
+ if (a > b) {
574
+ return a - b;
575
+ } else {
576
+ return b - a;
577
+ }
578
+}
579
+
580
+/* Unsigned sum of absolute byte differences. */
581
+uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
582
+{
583
+ uint32_t sum;
584
+ sum = do_usad(a, b);
585
+ sum += do_usad(a >> 8, b >> 8);
586
+ sum += do_usad(a >> 16, b >> 16);
587
+ sum += do_usad(a >> 24, b >> 24);
588
+ return sum;
589
+}
590
+
591
+/* For ARMv6 SEL instruction. */
592
+uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
593
+{
594
+ uint32_t mask;
595
+
596
+ mask = 0;
597
+ if (flags & 1) {
598
+ mask |= 0xff;
599
+ }
600
+ if (flags & 2) {
601
+ mask |= 0xff00;
602
+ }
603
+ if (flags & 4) {
604
+ mask |= 0xff0000;
605
+ }
606
+ if (flags & 8) {
607
+ mask |= 0xff000000;
608
+ }
609
+ return (a & mask) | (b & ~mask);
610
+}
611
+
612
+/*
613
+ * CRC helpers.
614
+ * The upper bytes of val (above the number specified by 'bytes') must have
615
+ * been zeroed out by the caller.
616
+ */
617
+uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
618
+{
619
+ uint8_t buf[4];
620
+
621
+ stl_le_p(buf, val);
622
+
623
+ /* zlib crc32 converts the accumulator and output to one's complement. */
624
+ return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
625
+}
626
+
627
+uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
628
+{
629
+ uint8_t buf[4];
630
+
631
+ stl_le_p(buf, val);
632
+
633
+ /* Linux crc32c converts the output to one's complement. */
634
+ return crc32c(acc, buf, bytes) ^ 0xffffffff;
635
+}
636
diff --git a/target/arm/op_addsub.h b/target/arm/tcg/op_addsub.c.inc
637
similarity index 100%
638
rename from target/arm/op_addsub.h
639
rename to target/arm/tcg/op_addsub.c.inc
640
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
641
index XXXXXXX..XXXXXXX 100644
642
--- a/target/arm/tcg/meson.build
643
+++ b/target/arm/tcg/meson.build
644
@@ -XXX,XX +XXX,XX @@ arm_ss.add(files(
645
'tlb_helper.c',
646
'vec_helper.c',
647
'tlb-insns.c',
648
+ 'arith_helper.c',
649
))
650
651
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
83
--
652
--
84
2.19.1
653
2.34.1
85
654
86
655
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Before changing default pauth algorithm, we need to make sure current
4
Message-id: 20181113180154.17903-3-richard.henderson@linaro.org
4
default one (QARMA5) can still be selected.
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
6
$ qemu-system-aarch64 -cpu max,pauth-qarma5=on ...
7
8
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241219183211.3493974-2-pierrick.bouvier@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
target/arm/kvm64.c | 90 ++++++++++++++++++++++++++++++++++++++++++++--
13
docs/system/arm/cpu-features.rst | 5 ++++-
9
1 file changed, 88 insertions(+), 2 deletions(-)
14
target/arm/cpu.h | 1 +
15
target/arm/arm-qmp-cmds.c | 2 +-
16
target/arm/cpu64.c | 20 ++++++++++++++------
17
tests/qtest/arm-cpu-features.c | 15 +++++++++++----
18
5 files changed, 31 insertions(+), 12 deletions(-)
10
19
11
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
20
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
12
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/kvm64.c
22
--- a/docs/system/arm/cpu-features.rst
14
+++ b/target/arm/kvm64.c
23
+++ b/docs/system/arm/cpu-features.rst
15
@@ -XXX,XX +XXX,XX @@ static inline void unset_feature(uint64_t *features, int feature)
24
@@ -XXX,XX +XXX,XX @@ Below is the list of TCG VCPU features and their descriptions.
16
*features &= ~(1ULL << feature);
25
``pauth-qarma3``
26
When ``pauth`` is enabled, select the architected QARMA3 algorithm.
27
28
-Without either ``pauth-impdef`` or ``pauth-qarma3`` enabled,
29
+``pauth-qarma5``
30
+ When ``pauth`` is enabled, select the architected QARMA5 algorithm.
31
+
32
+Without ``pauth-impdef``, ``pauth-qarma3`` or ``pauth-qarma5`` enabled,
33
the architected QARMA5 algorithm is used. The architected QARMA5
34
and QARMA3 algorithms have good cryptographic properties, but can
35
be quite slow to emulate. The impdef algorithm used by QEMU is
36
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/cpu.h
39
+++ b/target/arm/cpu.h
40
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
41
bool prop_pauth;
42
bool prop_pauth_impdef;
43
bool prop_pauth_qarma3;
44
+ bool prop_pauth_qarma5;
45
bool prop_lpa2;
46
47
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
48
diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/arm-qmp-cmds.c
51
+++ b/target/arm/arm-qmp-cmds.c
52
@@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = {
53
"sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
54
"sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
55
"kvm-no-adjvtime", "kvm-steal-time",
56
- "pauth", "pauth-impdef", "pauth-qarma3",
57
+ "pauth", "pauth-impdef", "pauth-qarma3", "pauth-qarma5",
58
NULL
59
};
60
61
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/cpu64.c
64
+++ b/target/arm/cpu64.c
65
@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
66
}
67
68
if (cpu->prop_pauth) {
69
- if (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) {
70
+ if ((cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) ||
71
+ (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma5) ||
72
+ (cpu->prop_pauth_qarma3 && cpu->prop_pauth_qarma5)) {
73
error_setg(errp,
74
- "cannot enable both pauth-impdef and pauth-qarma3");
75
+ "cannot enable pauth-impdef, pauth-qarma3 and "
76
+ "pauth-qarma5 at the same time");
77
return;
78
}
79
80
@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
81
} else if (cpu->prop_pauth_qarma3) {
82
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features);
83
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1);
84
- } else {
85
+ } else { /* default is pauth-qarma5 */
86
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features);
87
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1);
88
}
89
- } else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3) {
90
- error_setg(errp, "cannot enable pauth-impdef or "
91
- "pauth-qarma3 without pauth");
92
+ } else if (cpu->prop_pauth_impdef ||
93
+ cpu->prop_pauth_qarma3 ||
94
+ cpu->prop_pauth_qarma5) {
95
+ error_setg(errp, "cannot enable pauth-impdef, pauth-qarma3 or "
96
+ "pauth-qarma5 without pauth");
97
error_append_hint(errp, "Add pauth=on to the CPU property list.\n");
98
}
99
}
100
@@ -XXX,XX +XXX,XX @@ static const Property arm_cpu_pauth_impdef_property =
101
DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false);
102
static const Property arm_cpu_pauth_qarma3_property =
103
DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false);
104
+static Property arm_cpu_pauth_qarma5_property =
105
+ DEFINE_PROP_BOOL("pauth-qarma5", ARMCPU, prop_pauth_qarma5, false);
106
107
void aarch64_add_pauth_properties(Object *obj)
108
{
109
@@ -XXX,XX +XXX,XX @@ void aarch64_add_pauth_properties(Object *obj)
110
} else {
111
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property);
112
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma3_property);
113
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma5_property);
114
}
17
}
115
}
18
116
19
+static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
117
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
20
+{
118
index XXXXXXX..XXXXXXX 100644
21
+ uint64_t ret;
119
--- a/tests/qtest/arm-cpu-features.c
22
+ struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret };
120
+++ b/tests/qtest/arm-cpu-features.c
23
+ int err;
121
@@ -XXX,XX +XXX,XX @@ static void pauth_tests_default(QTestState *qts, const char *cpu_type)
24
+
122
assert_has_feature_enabled(qts, cpu_type, "pauth");
25
+ assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
123
assert_has_feature_disabled(qts, cpu_type, "pauth-impdef");
26
+ err = ioctl(fd, KVM_GET_ONE_REG, &idreg);
124
assert_has_feature_disabled(qts, cpu_type, "pauth-qarma3");
27
+ if (err < 0) {
125
+ assert_has_feature_disabled(qts, cpu_type, "pauth-qarma5");
28
+ return -1;
126
assert_set_feature(qts, cpu_type, "pauth", false);
29
+ }
127
assert_set_feature(qts, cpu_type, "pauth", true);
30
+ *pret = ret;
128
assert_set_feature(qts, cpu_type, "pauth-impdef", true);
31
+ return 0;
129
assert_set_feature(qts, cpu_type, "pauth-impdef", false);
32
+}
130
assert_set_feature(qts, cpu_type, "pauth-qarma3", true);
33
+
131
assert_set_feature(qts, cpu_type, "pauth-qarma3", false);
34
+static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id)
132
+ assert_set_feature(qts, cpu_type, "pauth-qarma5", true);
35
+{
133
+ assert_set_feature(qts, cpu_type, "pauth-qarma5", false);
36
+ struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
134
assert_error(qts, cpu_type,
37
+
135
- "cannot enable pauth-impdef or pauth-qarma3 without pauth",
38
+ assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
136
+ "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5 without pauth",
39
+ return ioctl(fd, KVM_GET_ONE_REG, &idreg);
137
"{ 'pauth': false, 'pauth-impdef': true }");
40
+}
138
assert_error(qts, cpu_type,
41
+
139
- "cannot enable pauth-impdef or pauth-qarma3 without pauth",
42
bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
140
+ "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5 without pauth",
43
{
141
"{ 'pauth': false, 'pauth-qarma3': true }");
44
/* Identify the feature bits corresponding to the host CPU, and
142
assert_error(qts, cpu_type,
45
* fill out the ARMHostCPUClass fields accordingly. To do this
143
- "cannot enable both pauth-impdef and pauth-qarma3",
46
* we have to create a scratch VM, create a single CPU inside it,
144
- "{ 'pauth': true, 'pauth-impdef': true, 'pauth-qarma3': true }");
47
* and then query that CPU for the relevant ID registers.
145
+ "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5 without pauth",
48
- * For AArch64 we currently don't care about ID registers at
146
+ "{ 'pauth': false, 'pauth-qarma5': true }");
49
- * all; we just want to know the CPU type.
147
+ assert_error(qts, cpu_type,
50
*/
148
+ "cannot enable pauth-impdef, pauth-qarma3 and pauth-qarma5 at the same time",
51
int fdarray[3];
149
+ "{ 'pauth': true, 'pauth-impdef': true, 'pauth-qarma3': true,"
52
uint64_t features = 0;
150
+ " 'pauth-qarma5': true }");
53
+ int err;
151
}
54
+
152
55
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
153
static void test_query_cpu_model_expansion(const void *data)
56
* we know these will only support creating one kind of guest CPU,
57
* which is its preferred CPU type. Fortunately these old kernels
58
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
59
ahcf->target = init.target;
60
ahcf->dtb_compatible = "arm,arm-v8";
61
62
+ err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
63
+ ARM64_SYS_REG(3, 0, 0, 4, 0));
64
+ if (unlikely(err < 0)) {
65
+ /*
66
+ * Before v4.15, the kernel only exposed a limited number of system
67
+ * registers, not including any of the interesting AArch64 ID regs.
68
+ * For the most part we could leave these fields as zero with minimal
69
+ * effect, since this does not affect the values seen by the guest.
70
+ *
71
+ * However, it could cause problems down the line for QEMU,
72
+ * so provide a minimal v8.0 default.
73
+ *
74
+ * ??? Could read MIDR and use knowledge from cpu64.c.
75
+ * ??? Could map a page of memory into our temp guest and
76
+ * run the tiniest of hand-crafted kernels to extract
77
+ * the values seen by the guest.
78
+ * ??? Either of these sounds like too much effort just
79
+ * to work around running a modern host kernel.
80
+ */
81
+ ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
82
+ err = 0;
83
+ } else {
84
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
85
+ ARM64_SYS_REG(3, 0, 0, 4, 1));
86
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
87
+ ARM64_SYS_REG(3, 0, 0, 6, 0));
88
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
89
+ ARM64_SYS_REG(3, 0, 0, 6, 1));
90
+
91
+ /*
92
+ * Note that if AArch32 support is not present in the host,
93
+ * the AArch32 sysregs are present to be read, but will
94
+ * return UNKNOWN values. This is neither better nor worse
95
+ * than skipping the reads and leaving 0, as we must avoid
96
+ * considering the values in every case.
97
+ */
98
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
99
+ ARM64_SYS_REG(3, 0, 0, 2, 0));
100
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
101
+ ARM64_SYS_REG(3, 0, 0, 2, 1));
102
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
103
+ ARM64_SYS_REG(3, 0, 0, 2, 2));
104
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
105
+ ARM64_SYS_REG(3, 0, 0, 2, 3));
106
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
107
+ ARM64_SYS_REG(3, 0, 0, 2, 4));
108
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
109
+ ARM64_SYS_REG(3, 0, 0, 2, 5));
110
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
111
+ ARM64_SYS_REG(3, 0, 0, 2, 7));
112
+
113
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
114
+ ARM64_SYS_REG(3, 0, 0, 3, 0));
115
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
116
+ ARM64_SYS_REG(3, 0, 0, 3, 1));
117
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
118
+ ARM64_SYS_REG(3, 0, 0, 3, 2));
119
+ }
120
+
121
kvm_arm_destroy_scratch_host_vcpu(fdarray);
122
123
+ if (err < 0) {
124
+ return false;
125
+ }
126
+
127
/* We can assume any KVM supporting CPU is at least a v8
128
* with VFPv4+Neon; this in turn implies most of the other
129
* feature bits.
130
--
154
--
131
2.19.1
155
2.34.1
132
133
diff view generated by jsdifflib
1
In practice for most of the more-or-less orphan Arm board models,
1
The pauth-3 test explicitly tests that a computation of the
2
I will review patches and put them in via the target-arm tree.
2
pointer-authentication produces the expected result. This means that
3
So list myself as an "Odd Fixes" status maintainer for them.
3
it must be run with the QARMA5 algorithm.
4
4
5
This commit downgrades these boards to "Odd Fixes":
5
Explicitly set the pauth algorithm when running this test, so that it
6
* Allwinner-A10
6
doesn't break when we change the default algorithm the 'max' CPU
7
* Exynos
7
uses.
8
* Calxeda Highbank
9
* Canon DIGIC
10
* Musicpal
11
* nSeries
12
* Palm
13
* PXA2xx
14
15
These boards were already "Odd Fixes":
16
* Gumstix
17
* i.MX31 (kzm)
18
19
Philippe Mathieu-Daudé has requested to be moved to R:
20
status for Gumstix now that I am listed as the M: contact.
21
22
Some boards are maintained, but their patches still go
23
via the target-arm tree, so add myself as a secondary
24
maintainer contact for those:
25
* Xilinx Zynq
26
* Xilinx ZynqMP
27
* STM32F205
28
* Netduino 2
29
* SmartFusion2
30
* Mecraft M2S-FG484
31
* ASPEED BMCs
32
* NRF51
33
8
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
36
Reviewed-by: Thomas Huth <thuth@redhat.com>
37
Message-id: 20181108134139.31666-1-peter.maydell@linaro.org
38
---
10
---
39
MAINTAINERS | 36 +++++++++++++++++++++++++++---------
11
tests/tcg/aarch64/Makefile.softmmu-target | 3 +++
40
1 file changed, 27 insertions(+), 9 deletions(-)
12
1 file changed, 3 insertions(+)
41
13
42
diff --git a/MAINTAINERS b/MAINTAINERS
14
diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target
43
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
44
--- a/MAINTAINERS
16
--- a/tests/tcg/aarch64/Makefile.softmmu-target
45
+++ b/MAINTAINERS
17
+++ b/tests/tcg/aarch64/Makefile.softmmu-target
46
@@ -XXX,XX +XXX,XX @@ ARM Machines
18
@@ -XXX,XX +XXX,XX @@ EXTRA_RUNS+=run-memory-replay
47
------------
19
48
Allwinner-a10
20
ifneq ($(CROSS_CC_HAS_ARMV8_3),)
49
M: Beniamino Galvani <b.galvani@gmail.com>
21
pauth-3: CFLAGS += $(CROSS_CC_HAS_ARMV8_3)
50
+M: Peter Maydell <peter.maydell@linaro.org>
22
+# This test explicitly checks the output of the pauth operation so we
51
L: qemu-arm@nongnu.org
23
+# must force the use of the QARMA5 algorithm for it.
52
-S: Maintained
24
+run-pauth-3: QEMU_BASE_MACHINE=-M virt -cpu max,pauth-qarma5=on -display none
53
+S: Odd Fixes
25
else
54
F: hw/*/allwinner*
26
pauth-3:
55
F: include/hw/*/allwinner*
27
    $(call skip-test, "BUILD of $@", "missing compiler support")
56
F: hw/arm/cubieboard.c
57
@@ -XXX,XX +XXX,XX @@ F: tests/test-arm-mptimer.c
58
59
Exynos
60
M: Igor Mitsyanko <i.mitsyanko@gmail.com>
61
+M: Peter Maydell <peter.maydell@linaro.org>
62
L: qemu-arm@nongnu.org
63
-S: Maintained
64
+S: Odd Fixes
65
F: hw/*/exynos*
66
F: include/hw/arm/exynos4210.h
67
68
Calxeda Highbank
69
M: Rob Herring <robh@kernel.org>
70
+M: Peter Maydell <peter.maydell@linaro.org>
71
L: qemu-arm@nongnu.org
72
-S: Maintained
73
+S: Odd Fixes
74
F: hw/arm/highbank.c
75
F: hw/net/xgmac.c
76
77
Canon DIGIC
78
M: Antony Pavlov <antonynpavlov@gmail.com>
79
+M: Peter Maydell <peter.maydell@linaro.org>
80
L: qemu-arm@nongnu.org
81
-S: Maintained
82
+S: Odd Fixes
83
F: include/hw/arm/digic.h
84
F: hw/*/digic*
85
86
Gumstix
87
-M: Philippe Mathieu-Daudé <f4bug@amsat.org>
88
+M: Peter Maydell <peter.maydell@linaro.org>
89
+R: Philippe Mathieu-Daudé <f4bug@amsat.org>
90
L: qemu-devel@nongnu.org
91
L: qemu-arm@nongnu.org
92
S: Odd Fixes
93
@@ -XXX,XX +XXX,XX @@ F: hw/arm/gumstix.c
94
95
i.MX31 (kzm)
96
M: Peter Chubb <peter.chubb@nicta.com.au>
97
+M: Peter Maydell <peter.maydell@linaro.org>
98
L: qemu-arm@nongnu.org
99
S: Odd Fixes
100
F: hw/arm/kzm.c
101
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/iotkit-sysinfo.h
102
103
Musicpal
104
M: Jan Kiszka <jan.kiszka@web.de>
105
+M: Peter Maydell <peter.maydell@linaro.org>
106
L: qemu-arm@nongnu.org
107
-S: Maintained
108
+S: Odd Fixes
109
F: hw/arm/musicpal.c
110
111
nSeries
112
M: Andrzej Zaborowski <balrogg@gmail.com>
113
+M: Peter Maydell <peter.maydell@linaro.org>
114
L: qemu-arm@nongnu.org
115
-S: Maintained
116
+S: Odd Fixes
117
F: hw/arm/nseries.c
118
119
Palm
120
M: Andrzej Zaborowski <balrogg@gmail.com>
121
+M: Peter Maydell <peter.maydell@linaro.org>
122
L: qemu-arm@nongnu.org
123
-S: Maintained
124
+S: Odd Fixes
125
F: hw/arm/palm.c
126
127
Raspberry Pi
128
@@ -XXX,XX +XXX,XX @@ F: include/hw/intc/realview_gic.h
129
130
PXA2XX
131
M: Andrzej Zaborowski <balrogg@gmail.com>
132
+M: Peter Maydell <peter.maydell@linaro.org>
133
L: qemu-arm@nongnu.org
134
-S: Maintained
135
+S: Odd Fixes
136
F: hw/arm/mainstone.c
137
F: hw/arm/spitz.c
138
F: hw/arm/tosa.c
139
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/virt.h
140
Xilinx Zynq
141
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
142
M: Alistair Francis <alistair@alistair23.me>
143
+M: Peter Maydell <peter.maydell@linaro.org>
144
L: qemu-arm@nongnu.org
145
S: Maintained
146
F: hw/*/xilinx_*
147
@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
148
Xilinx ZynqMP
149
M: Alistair Francis <alistair@alistair23.me>
150
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
151
+M: Peter Maydell <peter.maydell@linaro.org>
152
L: qemu-arm@nongnu.org
153
S: Maintained
154
F: hw/*/xlnx*.c
155
@@ -XXX,XX +XXX,XX @@ F: hw/arm/virt-acpi-build.c
156
157
STM32F205
158
M: Alistair Francis <alistair@alistair23.me>
159
+M: Peter Maydell <peter.maydell@linaro.org>
160
S: Maintained
161
F: hw/arm/stm32f205_soc.c
162
F: hw/misc/stm32f2xx_syscfg.c
163
@@ -XXX,XX +XXX,XX @@ F: include/hw/*/stm32*.h
164
165
Netduino 2
166
M: Alistair Francis <alistair@alistair23.me>
167
+M: Peter Maydell <peter.maydell@linaro.org>
168
S: Maintained
169
F: hw/arm/netduino2.c
170
171
SmartFusion2
172
M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
173
+M: Peter Maydell <peter.maydell@linaro.org>
174
S: Maintained
175
F: hw/arm/msf2-soc.c
176
F: hw/misc/msf2-sysreg.c
177
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/mss-spi.h
178
179
Emcraft M2S-FG484
180
M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
181
+M: Peter Maydell <peter.maydell@linaro.org>
182
S: Maintained
183
F: hw/arm/msf2-som.c
184
185
ASPEED BMCs
186
M: Cédric Le Goater <clg@kaod.org>
187
+M: Peter Maydell <peter.maydell@linaro.org>
188
R: Andrew Jeffery <andrew@aj.id.au>
189
R: Joel Stanley <joel@jms.id.au>
190
L: qemu-arm@nongnu.org
191
@@ -XXX,XX +XXX,XX @@ F: include/hw/net/ftgmac100.h
192
193
NRF51
194
M: Joel Stanley <joel@jms.id.au>
195
+M: Peter Maydell <peter.maydell@linaro.org>
196
L: qemu-arm@nongnu.org
197
S: Maintained
198
F: hw/arm/nrf51_soc.c
199
--
28
--
200
2.19.1
29
2.34.1
201
202
diff view generated by jsdifflib
New patch
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
Pointer authentication on aarch64 is pretty expensive (up to 50% of
4
execution time) when running a virtual machine with tcg and -cpu max
5
(which enables pauth=on).
6
7
The advice is always: use pauth-impdef=on.
8
Our documentation even mentions it "by default" in
9
docs/system/introduction.rst.
10
11
Thus, we change the default to use impdef by default. This does not
12
affect kvm or hvf acceleration, since pauth algorithm used is the one
13
from host cpu.
14
15
This change is retro compatible, in terms of cli, with previous
16
versions, as the semantic of using -cpu max,pauth-impdef=on, and -cpu
17
max,pauth-qarma3=on is preserved.
18
The new option introduced in previous patch and matching old default is
19
-cpu max,pauth-qarma5=on.
20
It is retro compatible with migration as well, by defining a backcompat
21
property, that will use qarma5 by default for virt machine <= 9.2.
22
Tested by saving and restoring a vm from qemu 9.2.0 into qemu-master
23
(10.0) for cpus neoverse-n2 and max.
24
25
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
26
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Message-id: 20241219183211.3493974-3-pierrick.bouvier@linaro.org
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
---
30
docs/system/arm/cpu-features.rst | 2 +-
31
docs/system/introduction.rst | 2 +-
32
target/arm/cpu.h | 3 +++
33
hw/core/machine.c | 4 +++-
34
target/arm/cpu.c | 2 ++
35
target/arm/cpu64.c | 22 ++++++++++++++++------
36
6 files changed, 26 insertions(+), 9 deletions(-)
37
38
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
39
index XXXXXXX..XXXXXXX 100644
40
--- a/docs/system/arm/cpu-features.rst
41
+++ b/docs/system/arm/cpu-features.rst
42
@@ -XXX,XX +XXX,XX @@ Below is the list of TCG VCPU features and their descriptions.
43
When ``pauth`` is enabled, select the architected QARMA5 algorithm.
44
45
Without ``pauth-impdef``, ``pauth-qarma3`` or ``pauth-qarma5`` enabled,
46
-the architected QARMA5 algorithm is used. The architected QARMA5
47
+the QEMU impdef algorithm is used. The architected QARMA5
48
and QARMA3 algorithms have good cryptographic properties, but can
49
be quite slow to emulate. The impdef algorithm used by QEMU is
50
non-cryptographic but significantly faster.
51
diff --git a/docs/system/introduction.rst b/docs/system/introduction.rst
52
index XXXXXXX..XXXXXXX 100644
53
--- a/docs/system/introduction.rst
54
+++ b/docs/system/introduction.rst
55
@@ -XXX,XX +XXX,XX @@ would default to it anyway.
56
57
.. code::
58
59
- -cpu max,pauth-impdef=on \
60
+ -cpu max \
61
-smp 4 \
62
-accel tcg \
63
64
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/cpu.h
67
+++ b/target/arm/cpu.h
68
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
69
/* QOM property to indicate we should use the back-compat CNTFRQ default */
70
bool backcompat_cntfrq;
71
72
+ /* QOM property to indicate we should use the back-compat QARMA5 default */
73
+ bool backcompat_pauth_default_use_qarma5;
74
+
75
/* Specify the number of cores in this CPU cluster. Used for the L2CTLR
76
* register.
77
*/
78
diff --git a/hw/core/machine.c b/hw/core/machine.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/core/machine.c
81
+++ b/hw/core/machine.c
82
@@ -XXX,XX +XXX,XX @@
83
#include "hw/virtio/virtio-iommu.h"
84
#include "audio/audio.h"
85
86
-GlobalProperty hw_compat_9_2[] = {};
87
+GlobalProperty hw_compat_9_2[] = {
88
+ {"arm-cpu", "backcompat-pauth-default-use-qarma5", "true"},
89
+};
90
const size_t hw_compat_9_2_len = G_N_ELEMENTS(hw_compat_9_2);
91
92
GlobalProperty hw_compat_9_1[] = {
93
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
94
index XXXXXXX..XXXXXXX 100644
95
--- a/target/arm/cpu.c
96
+++ b/target/arm/cpu.c
97
@@ -XXX,XX +XXX,XX @@ static const Property arm_cpu_properties[] = {
98
DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
99
/* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
100
DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
101
+ DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU,
102
+ backcompat_pauth_default_use_qarma5, false),
103
};
104
105
static const gchar *arm_gdb_arch_name(CPUState *cs)
106
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/cpu64.c
109
+++ b/target/arm/cpu64.c
110
@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
111
return;
112
}
113
114
- if (cpu->prop_pauth_impdef) {
115
- isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features);
116
- isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1);
117
+ bool use_default = !cpu->prop_pauth_qarma5 &&
118
+ !cpu->prop_pauth_qarma3 &&
119
+ !cpu->prop_pauth_impdef;
120
+
121
+ if (cpu->prop_pauth_qarma5 ||
122
+ (use_default &&
123
+ cpu->backcompat_pauth_default_use_qarma5)) {
124
+ isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features);
125
+ isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1);
126
} else if (cpu->prop_pauth_qarma3) {
127
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features);
128
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1);
129
- } else { /* default is pauth-qarma5 */
130
- isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features);
131
- isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1);
132
+ } else if (cpu->prop_pauth_impdef ||
133
+ (use_default &&
134
+ !cpu->backcompat_pauth_default_use_qarma5)) {
135
+ isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features);
136
+ isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1);
137
+ } else {
138
+ g_assert_not_reached();
139
}
140
} else if (cpu->prop_pauth_impdef ||
141
cpu->prop_pauth_qarma3 ||
142
--
143
2.34.1
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
2
3
The ID registers are replacing (some of) the feature bits.
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
We need (some of) these values to determine the set of data
4
Message-id: 20241219183211.3493974-4-pierrick.bouvier@linaro.org
5
to be handled during migration.
5
[PMM: Removed a paragraph about using non-versioned models.]
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20181113180154.17903-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
7
---
12
target/arm/kvm_arm.h | 1 +
8
docs/system/arm/virt.rst | 4 ++++
13
target/arm/kvm.c | 1 +
9
1 file changed, 4 insertions(+)
14
2 files changed, 2 insertions(+)
15
10
16
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
11
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm_arm.h
13
--- a/docs/system/arm/virt.rst
19
+++ b/target/arm/kvm_arm.h
14
+++ b/docs/system/arm/virt.rst
20
@@ -XXX,XX +XXX,XX @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);
15
@@ -XXX,XX +XXX,XX @@ of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
21
* by asking the host kernel)
16
is not guaranteed to work between different QEMU releases for
22
*/
17
the non-versioned ``virt`` machine type.
23
typedef struct ARMHostCPUFeatures {
18
24
+ ARMISARegisters isar;
19
+VM migration is not guaranteed when using ``-cpu max``, as features
25
uint64_t features;
20
+supported may change between QEMU versions. To ensure your VM can be
26
uint32_t target;
21
+migrated, it is recommended to use another cpu model instead.
27
const char *dtb_compatible;
22
+
28
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
23
Supported devices
29
index XXXXXXX..XXXXXXX 100644
24
"""""""""""""""""
30
--- a/target/arm/kvm.c
31
+++ b/target/arm/kvm.c
32
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
33
34
cpu->kvm_target = arm_host_cpu_features.target;
35
cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
36
+ cpu->isar = arm_host_cpu_features.isar;
37
env->features = arm_host_cpu_features.features;
38
}
39
25
40
--
26
--
41
2.19.1
27
2.34.1
42
43
diff view generated by jsdifflib