| 1 | Some Arm bugfixes for rc2... | 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. |
|---|---|---|---|
| 2 | 2 | ||
| 3 | thanks | ||
| 4 | -- PMM | 3 | -- PMM |
| 5 | 4 | ||
| 6 | The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812: | 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: |
| 7 | 6 | ||
| 8 | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000) | 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) |
| 9 | 8 | ||
| 10 | are available in the Git repository at: | 9 | are available in the Git repository at: |
| 11 | 10 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 |
| 13 | 12 | ||
| 14 | for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e: | 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: |
| 15 | 14 | ||
| 16 | MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000) | 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) |
| 17 | 16 | ||
| 18 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 18 | target-arm queue: |
| 20 | * various MAINTAINERS file updates | 19 | * Fix KVM SVE ID register probe code |
| 21 | * hw/block/onenand: use qemu_log_mask() for reporting | ||
| 22 | * hw/block/onenand: Fix off-by-one error allowing out-of-bounds read | ||
| 23 | on the n800 and n810 machine models | ||
| 24 | * target/arm: fix smc incorrectly trapping to EL3 when secure is off | ||
| 25 | * hw/arm/stm32f205: Fix the UART and Timer region size | ||
| 26 | * target/arm: read ID registers for KVM guests so they can be | ||
| 27 | used to gate "is feature X present" checks | ||
| 28 | 20 | ||
| 29 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
| 30 | Luc Michel (1): | 22 | Richard Henderson (3): |
| 31 | target/arm: fix smc incorrectly trapping to EL3 when secure is off | 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features |
| 24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
| 25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
| 32 | 26 | ||
| 33 | Peter Maydell (3): | 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- |
| 34 | hw/block/onenand: Fix off-by-one error allowing out-of-bounds read | 28 | 1 file changed, 22 insertions(+), 23 deletions(-) |
| 35 | hw/block/onenand: use qemu_log_mask() for reporting | ||
| 36 | MAINTAINERS: list myself as maintainer for various Arm boards | ||
| 37 | |||
| 38 | Richard Henderson (4): | ||
| 39 | target/arm: Install ARMISARegisters from kvm host | ||
| 40 | target/arm: Fill in ARMISARegisters for kvm64 | ||
| 41 | target/arm: Introduce read_sys_reg32 for kvm32 | ||
| 42 | target/arm: Fill in ARMISARegisters for kvm32 | ||
| 43 | |||
| 44 | Seth Kintigh (1): | ||
| 45 | hw/arm/stm32f205: Fix the UART and Timer region size | ||
| 46 | |||
| 47 | Thomas Huth (1): | ||
| 48 | MAINTAINERS: Add entries for missing ARM boards | ||
| 49 | |||
| 50 | target/arm/kvm_arm.h | 1 + | ||
| 51 | hw/block/onenand.c | 24 +++++----- | ||
| 52 | hw/char/stm32f2xx_usart.c | 2 +- | ||
| 53 | hw/timer/stm32f2xx_timer.c | 2 +- | ||
| 54 | target/arm/kvm.c | 1 + | ||
| 55 | target/arm/kvm32.c | 77 ++++++++++++++++++++------------ | ||
| 56 | target/arm/kvm64.c | 90 +++++++++++++++++++++++++++++++++++++- | ||
| 57 | target/arm/op_helper.c | 54 +++++++++++++++++++---- | ||
| 58 | MAINTAINERS | 106 +++++++++++++++++++++++++++++++++++++++------ | ||
| 59 | 9 files changed, 293 insertions(+), 64 deletions(-) | ||
| 60 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The ID registers are replacing (some of) the feature bits. | ||
| 4 | We need (some of) these values to determine the set of data | ||
| 5 | to be handled during migration. | ||
| 6 | |||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20181113180154.17903-2-richard.henderson@linaro.org | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/kvm_arm.h | 1 + | ||
| 13 | target/arm/kvm.c | 1 + | ||
| 14 | 2 files changed, 2 insertions(+) | ||
| 15 | |||
| 16 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/kvm_arm.h | ||
| 19 | +++ b/target/arm/kvm_arm.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); | ||
| 21 | * by asking the host kernel) | ||
| 22 | */ | ||
| 23 | typedef struct ARMHostCPUFeatures { | ||
| 24 | + ARMISARegisters isar; | ||
| 25 | uint64_t features; | ||
| 26 | uint32_t target; | ||
| 27 | const char *dtb_compatible; | ||
| 28 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/target/arm/kvm.c | ||
| 31 | +++ b/target/arm/kvm.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) | ||
| 33 | |||
| 34 | cpu->kvm_target = arm_host_cpu_features.target; | ||
| 35 | cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; | ||
| 36 | + cpu->isar = arm_host_cpu_features.isar; | ||
| 37 | env->features = arm_host_cpu_features.features; | ||
| 38 | } | ||
| 39 | |||
| 40 | -- | ||
| 41 | 2.19.1 | ||
| 42 | |||
| 43 | diff view generated by jsdifflib |
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Assert that the value to be written is the correct size. | 3 | Indication for support for SVE will not depend on whether we |
| 4 | No change in functionality here, just mirroring the same | 4 | perform the query on the main kvm_state or the temp vcpu. |
| 5 | function from kvm64. | ||
| 6 | 5 | ||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20181113180154.17903-4-richard.henderson@linaro.org | 7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org |
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 10 | --- |
| 12 | target/arm/kvm32.c | 41 ++++++++++++++++------------------------- | 11 | target/arm/kvm64.c | 2 +- |
| 13 | 1 file changed, 16 insertions(+), 25 deletions(-) | 12 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 14 | 13 | ||
| 15 | diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c | 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/arm/kvm32.c | 16 | --- a/target/arm/kvm64.c |
| 18 | +++ b/target/arm/kvm32.c | 17 | +++ b/target/arm/kvm64.c |
| 19 | @@ -XXX,XX +XXX,XX @@ static inline void set_feature(uint64_t *features, int feature) | ||
| 20 | *features |= 1ULL << feature; | ||
| 21 | } | ||
| 22 | |||
| 23 | +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) | ||
| 24 | +{ | ||
| 25 | + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; | ||
| 26 | + | ||
| 27 | + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32); | ||
| 28 | + return ioctl(fd, KVM_GET_ONE_REG, &idreg); | ||
| 29 | +} | ||
| 30 | + | ||
| 31 | bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 32 | { | ||
| 33 | /* Identify the feature bits corresponding to the host CPU, and | ||
| 34 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
| 35 | * we have to create a scratch VM, create a single CPU inside it, | 19 | } |
| 36 | * and then query that CPU for the relevant ID registers. | ||
| 37 | */ | ||
| 38 | - int i, ret, fdarray[3]; | ||
| 39 | + int err = 0, fdarray[3]; | ||
| 40 | uint32_t midr, id_pfr0, mvfr1; | ||
| 41 | uint64_t features = 0; | ||
| 42 | + | ||
| 43 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 44 | * we know these will only support creating one kind of guest CPU, | ||
| 45 | * which is its preferred CPU type. | ||
| 46 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 47 | QEMU_KVM_ARM_TARGET_NONE | ||
| 48 | }; | ||
| 49 | struct kvm_vcpu_init init; | ||
| 50 | - struct kvm_one_reg idregs[] = { | ||
| 51 | - { | ||
| 52 | - .id = KVM_REG_ARM | KVM_REG_SIZE_U32 | ||
| 53 | - | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0), | ||
| 54 | - .addr = (uintptr_t)&midr, | ||
| 55 | - }, | ||
| 56 | - { | ||
| 57 | - .id = KVM_REG_ARM | KVM_REG_SIZE_U32 | ||
| 58 | - | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0), | ||
| 59 | - .addr = (uintptr_t)&id_pfr0, | ||
| 60 | - }, | ||
| 61 | - { | ||
| 62 | - .id = KVM_REG_ARM | KVM_REG_SIZE_U32 | ||
| 63 | - | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1, | ||
| 64 | - .addr = (uintptr_t)&mvfr1, | ||
| 65 | - }, | ||
| 66 | - }; | ||
| 67 | |||
| 68 | if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { | ||
| 69 | return false; | ||
| 70 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 71 | */ | ||
| 72 | ahcf->dtb_compatible = "arm,arm-v7"; | ||
| 73 | |||
| 74 | - for (i = 0; i < ARRAY_SIZE(idregs); i++) { | ||
| 75 | - ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]); | ||
| 76 | - if (ret) { | ||
| 77 | - break; | ||
| 78 | - } | ||
| 79 | - } | ||
| 80 | + err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); | ||
| 81 | + err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0)); | ||
| 82 | + err |= read_sys_reg32(fdarray[2], &mvfr1, | ||
| 83 | + KVM_REG_ARM | KVM_REG_SIZE_U32 | | ||
| 84 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); | ||
| 85 | |||
| 86 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
| 87 | |||
| 88 | - if (ret) { | ||
| 89 | + if (err < 0) { | ||
| 90 | return false; | ||
| 91 | } | 20 | } |
| 92 | 21 | ||
| 22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
| 23 | + sve_supported = kvm_arm_sve_supported(); | ||
| 24 | |||
| 25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
| 26 | if (sve_supported) { | ||
| 93 | -- | 27 | -- |
| 94 | 2.19.1 | 28 | 2.25.1 |
| 95 | |||
| 96 | diff view generated by jsdifflib |
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 | ||
| 4 | was always returning zero. This also obviates the adjustment | ||
| 5 | of ID_AA64PFR0, which had sanitized the SVE field. | ||
| 6 | |||
| 7 | The effects of the bug are not visible, because the only thing that | ||
| 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. | ||
| 9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
| 10 | |||
| 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 4 | Message-id: 20181113180154.17903-5-richard.henderson@linaro.org | 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org |
| 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | --- | 16 | --- |
| 8 | target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++----- | 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- |
| 9 | 1 file changed, 35 insertions(+), 5 deletions(-) | 18 | 1 file changed, 13 insertions(+), 14 deletions(-) |
| 10 | 19 | ||
| 11 | diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c | 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/target/arm/kvm32.c | 22 | --- a/target/arm/kvm64.c |
| 14 | +++ b/target/arm/kvm32.c | 23 | +++ b/target/arm/kvm64.c |
| 15 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
| 16 | * and then query that CPU for the relevant ID registers. | 25 | bool sve_supported; |
| 17 | */ | 26 | bool pmu_supported = false; |
| 18 | int err = 0, fdarray[3]; | ||
| 19 | - uint32_t midr, id_pfr0, mvfr1; | ||
| 20 | + uint32_t midr, id_pfr0; | ||
| 21 | uint64_t features = 0; | 27 | uint64_t features = 0; |
| 28 | - uint64_t t; | ||
| 29 | int err; | ||
| 22 | 30 | ||
| 23 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however |
| 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
| 25 | 33 | struct kvm_vcpu_init init = { .target = -1, }; | |
| 26 | err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); | 34 | |
| 27 | err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0)); | 35 | /* |
| 28 | - err |= read_sys_reg32(fdarray[2], &mvfr1, | 36 | - * Ask for Pointer Authentication if supported. We can't play the |
| 29 | + | 37 | - * SVE trick of synthesising the ID reg as KVM won't tell us |
| 30 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, | 38 | - * whether we have the architected or IMPDEF version of PAuth, so |
| 31 | + ARM_CP15_REG32(0, 0, 2, 0)); | 39 | - * we have to use the actual ID regs. |
| 32 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, | 40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, |
| 33 | + ARM_CP15_REG32(0, 0, 2, 1)); | 41 | + * which is otherwise RAZ. |
| 34 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, | 42 | + */ |
| 35 | + ARM_CP15_REG32(0, 0, 2, 2)); | 43 | + sve_supported = kvm_arm_sve_supported(); |
| 36 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, | 44 | + if (sve_supported) { |
| 37 | + ARM_CP15_REG32(0, 0, 2, 3)); | 45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; |
| 38 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, | ||
| 39 | + ARM_CP15_REG32(0, 0, 2, 4)); | ||
| 40 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, | ||
| 41 | + ARM_CP15_REG32(0, 0, 2, 5)); | ||
| 42 | + if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, | ||
| 43 | + ARM_CP15_REG32(0, 0, 2, 7))) { | ||
| 44 | + /* | ||
| 45 | + * Older kernels don't support reading ID_ISAR6. This register was | ||
| 46 | + * only introduced in ARMv8, so we can assume that it is zero on a | ||
| 47 | + * CPU that a kernel this old is running on. | ||
| 48 | + */ | ||
| 49 | + ahcf->isar.id_isar6 = 0; | ||
| 50 | + } | 46 | + } |
| 51 | + | 47 | + |
| 52 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, | ||
| 53 | + KVM_REG_ARM | KVM_REG_SIZE_U32 | | ||
| 54 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); | ||
| 55 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, | ||
| 56 | KVM_REG_ARM | KVM_REG_SIZE_U32 | | ||
| 57 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); | ||
| 58 | + /* | 48 | + /* |
| 59 | + * FIXME: There is not yet a way to read MVFR2. | 49 | + * Ask for Pointer Authentication if supported, so that we get |
| 60 | + * Fortunately there is not yet anything in there that affects migration. | 50 | + * the unsanitized field values for AA64ISAR1_EL1. |
| 61 | + */ | 51 | */ |
| 62 | 52 | if (kvm_arm_pauth_supported()) { | |
| 63 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | 53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | |
| 64 | |||
| 65 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | 54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
| 66 | if (extract32(id_pfr0, 12, 4) == 1) { | 55 | } |
| 67 | set_feature(&features, ARM_FEATURE_THUMB2EE); | ||
| 68 | } | 56 | } |
| 69 | - if (extract32(mvfr1, 20, 4) == 1) { | 57 | |
| 70 | + if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) { | 58 | - sve_supported = kvm_arm_sve_supported(); |
| 71 | set_feature(&features, ARM_FEATURE_VFP_FP16); | 59 | - |
| 72 | } | 60 | - /* Add feature bits that can't appear until after VCPU init. */ |
| 73 | - if (extract32(mvfr1, 12, 4) == 1) { | 61 | if (sve_supported) { |
| 74 | + if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) { | 62 | - t = ahcf->isar.id_aa64pfr0; |
| 75 | set_feature(&features, ARM_FEATURE_NEON); | 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); |
| 76 | } | 64 | - ahcf->isar.id_aa64pfr0 = t; |
| 77 | - if (extract32(mvfr1, 28, 4) == 1) { | 65 | - |
| 78 | + if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) { | 66 | /* |
| 79 | /* FMAC support implies VFPv4 */ | 67 | * There is a range of kernels between kernel commit 73433762fcae |
| 80 | set_feature(&features, ARM_FEATURE_VFP4); | 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose |
| 81 | } | 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled |
| 70 | - * SVE support, so we only read it here, rather than together with all | ||
| 71 | - * the other ID registers earlier. | ||
| 72 | + * SVE support, which resulted in an error rather than RAZ. | ||
| 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
| 74 | */ | ||
| 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
| 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
| 82 | -- | 77 | -- |
| 83 | 2.19.1 | 78 | 2.25.1 |
| 84 | |||
| 85 | diff view generated by jsdifflib |
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The test for the IF block indicates no ID registers are exposed, much | ||
| 4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
| 5 | |||
| 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 4 | Message-id: 20181113180154.17903-3-richard.henderson@linaro.org | 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org |
| 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | --- | 10 | --- |
| 8 | target/arm/kvm64.c | 90 ++++++++++++++++++++++++++++++++++++++++++++-- | 11 | target/arm/kvm64.c | 22 +++++++++++----------- |
| 9 | 1 file changed, 88 insertions(+), 2 deletions(-) | 12 | 1 file changed, 11 insertions(+), 11 deletions(-) |
| 10 | 13 | ||
| 11 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
| 12 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 13 | --- a/target/arm/kvm64.c | 16 | --- a/target/arm/kvm64.c |
| 14 | +++ b/target/arm/kvm64.c | 17 | +++ b/target/arm/kvm64.c |
| 15 | @@ -XXX,XX +XXX,XX @@ static inline void unset_feature(uint64_t *features, int feature) | ||
| 16 | *features &= ~(1ULL << feature); | ||
| 17 | } | ||
| 18 | |||
| 19 | +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) | ||
| 20 | +{ | ||
| 21 | + uint64_t ret; | ||
| 22 | + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; | ||
| 23 | + int err; | ||
| 24 | + | ||
| 25 | + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); | ||
| 26 | + err = ioctl(fd, KVM_GET_ONE_REG, &idreg); | ||
| 27 | + if (err < 0) { | ||
| 28 | + return -1; | ||
| 29 | + } | ||
| 30 | + *pret = ret; | ||
| 31 | + return 0; | ||
| 32 | +} | ||
| 33 | + | ||
| 34 | +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) | ||
| 35 | +{ | ||
| 36 | + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; | ||
| 37 | + | ||
| 38 | + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); | ||
| 39 | + return ioctl(fd, KVM_GET_ONE_REG, &idreg); | ||
| 40 | +} | ||
| 41 | + | ||
| 42 | bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
| 43 | { | ||
| 44 | /* Identify the feature bits corresponding to the host CPU, and | ||
| 45 | * fill out the ARMHostCPUClass fields accordingly. To do this | ||
| 46 | * we have to create a scratch VM, create a single CPU inside it, | ||
| 47 | * and then query that CPU for the relevant ID registers. | ||
| 48 | - * For AArch64 we currently don't care about ID registers at | ||
| 49 | - * all; we just want to know the CPU type. | ||
| 50 | */ | ||
| 51 | int fdarray[3]; | ||
| 52 | uint64_t features = 0; | ||
| 53 | + int err; | ||
| 54 | + | ||
| 55 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
| 56 | * we know these will only support creating one kind of guest CPU, | ||
| 57 | * which is its preferred CPU type. Fortunately these old kernels | ||
| 58 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
| 59 | ahcf->target = init.target; | 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, |
| 60 | ahcf->dtb_compatible = "arm,arm-v8"; | 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); |
| 61 | 21 | } | |
| 62 | + err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, | 22 | - } |
| 63 | + ARM64_SYS_REG(3, 0, 0, 4, 0)); | 23 | |
| 64 | + if (unlikely(err < 0)) { | 24 | - if (sve_supported) { |
| 65 | + /* | 25 | - /* |
| 66 | + * Before v4.15, the kernel only exposed a limited number of system | 26 | - * There is a range of kernels between kernel commit 73433762fcae |
| 67 | + * registers, not including any of the interesting AArch64 ID regs. | 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose |
| 68 | + * For the most part we could leave these fields as zero with minimal | 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled |
| 69 | + * effect, since this does not affect the values seen by the guest. | 29 | - * SVE support, which resulted in an error rather than RAZ. |
| 70 | + * | 30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. |
| 71 | + * However, it could cause problems down the line for QEMU, | 31 | - */ |
| 72 | + * so provide a minimal v8.0 default. | 32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, |
| 73 | + * | 33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); |
| 74 | + * ??? Could read MIDR and use knowledge from cpu64.c. | 34 | + if (sve_supported) { |
| 75 | + * ??? Could map a page of memory into our temp guest and | 35 | + /* |
| 76 | + * run the tiniest of hand-crafted kernels to extract | 36 | + * There is a range of kernels between kernel commit 73433762fcae |
| 77 | + * the values seen by the guest. | 37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't |
| 78 | + * ??? Either of these sounds like too much effort just | 38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has |
| 79 | + * to work around running a modern host kernel. | 39 | + * enabled SVE support, which resulted in an error rather than RAZ. |
| 80 | + */ | 40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. |
| 81 | + ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */ | 41 | + */ |
| 82 | + err = 0; | 42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, |
| 83 | + } else { | 43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); |
| 84 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, | 44 | + } |
| 85 | + ARM64_SYS_REG(3, 0, 0, 4, 1)); | 45 | } |
| 86 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, | 46 | |
| 87 | + ARM64_SYS_REG(3, 0, 0, 6, 0)); | ||
| 88 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, | ||
| 89 | + ARM64_SYS_REG(3, 0, 0, 6, 1)); | ||
| 90 | + | ||
| 91 | + /* | ||
| 92 | + * Note that if AArch32 support is not present in the host, | ||
| 93 | + * the AArch32 sysregs are present to be read, but will | ||
| 94 | + * return UNKNOWN values. This is neither better nor worse | ||
| 95 | + * than skipping the reads and leaving 0, as we must avoid | ||
| 96 | + * considering the values in every case. | ||
| 97 | + */ | ||
| 98 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, | ||
| 99 | + ARM64_SYS_REG(3, 0, 0, 2, 0)); | ||
| 100 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, | ||
| 101 | + ARM64_SYS_REG(3, 0, 0, 2, 1)); | ||
| 102 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, | ||
| 103 | + ARM64_SYS_REG(3, 0, 0, 2, 2)); | ||
| 104 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, | ||
| 105 | + ARM64_SYS_REG(3, 0, 0, 2, 3)); | ||
| 106 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, | ||
| 107 | + ARM64_SYS_REG(3, 0, 0, 2, 4)); | ||
| 108 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, | ||
| 109 | + ARM64_SYS_REG(3, 0, 0, 2, 5)); | ||
| 110 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, | ||
| 111 | + ARM64_SYS_REG(3, 0, 0, 2, 7)); | ||
| 112 | + | ||
| 113 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, | ||
| 114 | + ARM64_SYS_REG(3, 0, 0, 3, 0)); | ||
| 115 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, | ||
| 116 | + ARM64_SYS_REG(3, 0, 0, 3, 1)); | ||
| 117 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, | ||
| 118 | + ARM64_SYS_REG(3, 0, 0, 3, 2)); | ||
| 119 | + } | ||
| 120 | + | ||
| 121 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | 47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); |
| 122 | |||
| 123 | + if (err < 0) { | ||
| 124 | + return false; | ||
| 125 | + } | ||
| 126 | + | ||
| 127 | /* We can assume any KVM supporting CPU is at least a v8 | ||
| 128 | * with VFPv4+Neon; this in turn implies most of the other | ||
| 129 | * feature bits. | ||
| 130 | -- | 48 | -- |
| 131 | 2.19.1 | 49 | 2.25.1 |
| 132 | |||
| 133 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Thomas Huth <thuth@redhat.com> | ||
| 2 | 1 | ||
| 3 | Add entries for the boards "mcimx6ul-evk", "mcimx7d-sabre", "raspi2", | ||
| 4 | "raspi3", "sabrelite", "vexpress-a15", "vexpress-a9" and "virt". | ||
| 5 | While we're at it, also adjust the "i.MX31" section a little bit, | ||
| 6 | so that the wildcards there do not match anymore for unrelated files | ||
| 7 | (e.g. the new hw/misc/imx6ul_ccm.c file). | ||
| 8 | |||
| 9 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
| 10 | Message-id: 1542184999-11145-1-git-send-email-thuth@redhat.com | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | --- | ||
| 13 | MAINTAINERS | 70 +++++++++++++++++++++++++++++++++++++++++++++++++---- | ||
| 14 | 1 file changed, 65 insertions(+), 5 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/MAINTAINERS | ||
| 19 | +++ b/MAINTAINERS | ||
| 20 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
| 21 | S: Odd Fixes | ||
| 22 | F: hw/arm/gumstix.c | ||
| 23 | |||
| 24 | -i.MX31 | ||
| 25 | +i.MX31 (kzm) | ||
| 26 | M: Peter Chubb <peter.chubb@nicta.com.au> | ||
| 27 | L: qemu-arm@nongnu.org | ||
| 28 | -S: Odd fixes | ||
| 29 | -F: hw/*/imx* | ||
| 30 | -F: include/hw/*/imx* | ||
| 31 | +S: Odd Fixes | ||
| 32 | F: hw/arm/kzm.c | ||
| 33 | -F: include/hw/arm/fsl-imx31.h | ||
| 34 | +F: hw/*/imx_* | ||
| 35 | +F: hw/*/*imx31* | ||
| 36 | +F: include/hw/*/imx_* | ||
| 37 | +F: include/hw/*/*imx31* | ||
| 38 | |||
| 39 | Integrator CP | ||
| 40 | M: Peter Maydell <peter.maydell@linaro.org> | ||
| 41 | @@ -XXX,XX +XXX,XX @@ S: Maintained | ||
| 42 | F: hw/arm/integratorcp.c | ||
| 43 | F: hw/misc/arm_integrator_debug.c | ||
| 44 | |||
| 45 | +MCIMX6UL EVK / i.MX6ul | ||
| 46 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 47 | +R: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
| 48 | +L: qemu-arm@nongnu.org | ||
| 49 | +S: Odd Fixes | ||
| 50 | +F: hw/arm/mcimx6ul-evk.c | ||
| 51 | +F: hw/arm/fsl-imx6ul.c | ||
| 52 | +F: hw/misc/imx6ul_ccm.c | ||
| 53 | +F: include/hw/arm/fsl-imx6ul.h | ||
| 54 | +F: include/hw/misc/imx6ul_ccm.h | ||
| 55 | + | ||
| 56 | +MCIMX7D SABRE / i.MX7 | ||
| 57 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 58 | +R: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
| 59 | +L: qemu-arm@nongnu.org | ||
| 60 | +S: Odd Fixes | ||
| 61 | +F: hw/arm/mcimx7d-sabre.c | ||
| 62 | +F: hw/arm/fsl-imx7.c | ||
| 63 | +F: include/hw/arm/fsl-imx7.h | ||
| 64 | +F: hw/pci-host/designware.c | ||
| 65 | +F: include/hw/pci-host/designware.h | ||
| 66 | + | ||
| 67 | MPS2 | ||
| 68 | M: Peter Maydell <peter.maydell@linaro.org> | ||
| 69 | L: qemu-arm@nongnu.org | ||
| 70 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
| 71 | S: Maintained | ||
| 72 | F: hw/arm/palm.c | ||
| 73 | |||
| 74 | +Raspberry Pi | ||
| 75 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 76 | +R: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
| 77 | +R: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 78 | +L: qemu-arm@nongnu.org | ||
| 79 | +S: Odd Fixes | ||
| 80 | +F: hw/arm/raspi_platform.h | ||
| 81 | +F: hw/*/bcm283* | ||
| 82 | +F: include/hw/arm/raspi* | ||
| 83 | +F: include/hw/*/bcm283* | ||
| 84 | + | ||
| 85 | Real View | ||
| 86 | M: Peter Maydell <peter.maydell@linaro.org> | ||
| 87 | L: qemu-arm@nongnu.org | ||
| 88 | @@ -XXX,XX +XXX,XX @@ F: hw/*/pxa2xx* | ||
| 89 | F: hw/misc/mst_fpga.c | ||
| 90 | F: include/hw/arm/pxa.h | ||
| 91 | |||
| 92 | +SABRELITE / i.MX6 | ||
| 93 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 94 | +R: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
| 95 | +L: qemu-arm@nongnu.org | ||
| 96 | +S: Odd Fixes | ||
| 97 | +F: hw/arm/sabrelite.c | ||
| 98 | +F: hw/arm/fsl-imx6.c | ||
| 99 | +F: hw/misc/imx6_src.c | ||
| 100 | +F: hw/ssi/imx_spi.c | ||
| 101 | +F: include/hw/arm/fsl-imx6.h | ||
| 102 | +F: include/hw/misc/imx6_src.h | ||
| 103 | +F: include/hw/ssi/imx_spi.h | ||
| 104 | + | ||
| 105 | Sharp SL-5500 (Collie) PDA | ||
| 106 | M: Peter Maydell <peter.maydell@linaro.org> | ||
| 107 | L: qemu-arm@nongnu.org | ||
| 108 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
| 109 | S: Maintained | ||
| 110 | F: hw/*/stellaris* | ||
| 111 | |||
| 112 | +Versatile Express | ||
| 113 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 114 | +L: qemu-arm@nongnu.org | ||
| 115 | +S: Maintained | ||
| 116 | +F: hw/arm/vexpress.c | ||
| 117 | + | ||
| 118 | Versatile PB | ||
| 119 | M: Peter Maydell <peter.maydell@linaro.org> | ||
| 120 | L: qemu-arm@nongnu.org | ||
| 121 | @@ -XXX,XX +XXX,XX @@ S: Maintained | ||
| 122 | F: hw/*/versatile* | ||
| 123 | F: hw/misc/arm_sysctl.c | ||
| 124 | |||
| 125 | +Virt | ||
| 126 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 127 | +L: qemu-arm@nongnu.org | ||
| 128 | +S: Maintained | ||
| 129 | +F: hw/arm/virt* | ||
| 130 | +F: include/hw/arm/virt.h | ||
| 131 | + | ||
| 132 | Xilinx Zynq | ||
| 133 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | ||
| 134 | M: Alistair Francis <alistair@alistair23.me> | ||
| 135 | -- | ||
| 136 | 2.19.1 | ||
| 137 | |||
| 138 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Seth Kintigh <skintigh@gmail.com> | ||
| 2 | 1 | ||
| 3 | The UART and timer devices for the stm32f205 were being created | ||
| 4 | with memory regions that were too large. Use the size specified | ||
| 5 | in the chip datasheet. | ||
| 6 | |||
| 7 | The old sizes were so large that the devices would overlap with | ||
| 8 | each other in the SoC memory map, so this fixes a bug that | ||
| 9 | caused odd behavior and/or crashes when trying to set up multiple | ||
| 10 | UARTs. | ||
| 11 | |||
| 12 | Signed-off-by: Seth Kintigh <skintigh@gmail.com> | ||
| 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | [PMM: rephrased commit message to follow our usual standard] | ||
| 15 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 16 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 18 | --- | ||
| 19 | hw/char/stm32f2xx_usart.c | 2 +- | ||
| 20 | hw/timer/stm32f2xx_timer.c | 2 +- | ||
| 21 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
| 22 | |||
| 23 | diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c | ||
| 24 | index XXXXXXX..XXXXXXX 100644 | ||
| 25 | --- a/hw/char/stm32f2xx_usart.c | ||
| 26 | +++ b/hw/char/stm32f2xx_usart.c | ||
| 27 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_init(Object *obj) | ||
| 28 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | ||
| 29 | |||
| 30 | memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s, | ||
| 31 | - TYPE_STM32F2XX_USART, 0x2000); | ||
| 32 | + TYPE_STM32F2XX_USART, 0x400); | ||
| 33 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | ||
| 34 | } | ||
| 35 | |||
| 36 | diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c | ||
| 37 | index XXXXXXX..XXXXXXX 100644 | ||
| 38 | --- a/hw/timer/stm32f2xx_timer.c | ||
| 39 | +++ b/hw/timer/stm32f2xx_timer.c | ||
| 40 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_timer_init(Object *obj) | ||
| 41 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | ||
| 42 | |||
| 43 | memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s, | ||
| 44 | - "stm32f2xx_timer", 0x4000); | ||
| 45 | + "stm32f2xx_timer", 0x400); | ||
| 46 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); | ||
| 47 | |||
| 48 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s); | ||
| 49 | -- | ||
| 50 | 2.19.1 | ||
| 51 | |||
| 52 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Luc Michel <luc.michel@greensocs.com> | ||
| 2 | 1 | ||
| 3 | This commit fixes a case where the CPU would try to go to EL3 when | ||
| 4 | executing an smc instruction, even though ARM_FEATURE_EL3 is false. This | ||
| 5 | case is raised when the PSCI conduit is set to smc, but the smc | ||
| 6 | instruction does not lead to a valid PSCI call. | ||
| 7 | |||
| 8 | QEMU crashes with an assertion failure latter on because of incoherent | ||
| 9 | mmu_idx. | ||
| 10 | |||
| 11 | This commit refactors the pre_smc helper by enumerating all the possible | ||
| 12 | way of handling an scm instruction, and covering the previously missing | ||
| 13 | case leading to the crash. | ||
| 14 | |||
| 15 | The following minimal test would crash before this commit: | ||
| 16 | |||
| 17 | .global _start | ||
| 18 | .text | ||
| 19 | _start: | ||
| 20 | ldr x0, =0xdeadbeef ; invalid PSCI call | ||
| 21 | smc #0 | ||
| 22 | |||
| 23 | run with the following command line: | ||
| 24 | |||
| 25 | aarch64-linux-gnu-gcc -nostdinc -nostdlib -Wl,-Ttext=40000000 \ | ||
| 26 | -o test test.s | ||
| 27 | |||
| 28 | qemu-system-aarch64 -M virt,virtualization=on,secure=off \ | ||
| 29 | -cpu cortex-a57 -kernel test | ||
| 30 | |||
| 31 | Signed-off-by: Luc Michel <luc.michel@greensocs.com> | ||
| 32 | Message-id: 20181117160213.18995-1-luc.michel@greensocs.com | ||
| 33 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 35 | --- | ||
| 36 | target/arm/op_helper.c | 54 +++++++++++++++++++++++++++++++++++------- | ||
| 37 | 1 file changed, 46 insertions(+), 8 deletions(-) | ||
| 38 | |||
| 39 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/target/arm/op_helper.c | ||
| 42 | +++ b/target/arm/op_helper.c | ||
| 43 | @@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) | ||
| 44 | ARMCPU *cpu = arm_env_get_cpu(env); | ||
| 45 | int cur_el = arm_current_el(env); | ||
| 46 | bool secure = arm_is_secure(env); | ||
| 47 | - bool smd = env->cp15.scr_el3 & SCR_SMD; | ||
| 48 | + bool smd_flag = env->cp15.scr_el3 & SCR_SMD; | ||
| 49 | + | ||
| 50 | + /* | ||
| 51 | + * SMC behaviour is summarized in the following table. | ||
| 52 | + * This helper handles the "Trap to EL2" and "Undef insn" cases. | ||
| 53 | + * The "Trap to EL3" and "PSCI call" cases are handled in the exception | ||
| 54 | + * helper. | ||
| 55 | + * | ||
| 56 | + * -> ARM_FEATURE_EL3 and !SMD | ||
| 57 | + * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 | ||
| 58 | + * | ||
| 59 | + * Conduit SMC, valid call Trap to EL2 PSCI Call | ||
| 60 | + * Conduit SMC, inval call Trap to EL2 Trap to EL3 | ||
| 61 | + * Conduit not SMC Trap to EL2 Trap to EL3 | ||
| 62 | + * | ||
| 63 | + * | ||
| 64 | + * -> ARM_FEATURE_EL3 and SMD | ||
| 65 | + * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 | ||
| 66 | + * | ||
| 67 | + * Conduit SMC, valid call Trap to EL2 PSCI Call | ||
| 68 | + * Conduit SMC, inval call Trap to EL2 Undef insn | ||
| 69 | + * Conduit not SMC Trap to EL2 Undef insn | ||
| 70 | + * | ||
| 71 | + * | ||
| 72 | + * -> !ARM_FEATURE_EL3 | ||
| 73 | + * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 | ||
| 74 | + * | ||
| 75 | + * Conduit SMC, valid call Trap to EL2 PSCI Call | ||
| 76 | + * Conduit SMC, inval call Trap to EL2 Undef insn | ||
| 77 | + * Conduit not SMC Undef insn Undef insn | ||
| 78 | + */ | ||
| 79 | + | ||
| 80 | /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state. | ||
| 81 | * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization | ||
| 82 | * extensions, SMD only applies to NS state. | ||
| 83 | @@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) | ||
| 84 | * doesn't exist, but we forbid the guest to set it to 1 in scr_write(), | ||
| 85 | * so we need not special case this here. | ||
| 86 | */ | ||
| 87 | - bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure; | ||
| 88 | + bool smd = arm_feature(env, ARM_FEATURE_AARCH64) ? smd_flag | ||
| 89 | + : smd_flag && !secure; | ||
| 90 | |||
| 91 | if (!arm_feature(env, ARM_FEATURE_EL3) && | ||
| 92 | cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { | ||
| 93 | @@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) | ||
| 94 | * to forbid its EL1 from making PSCI calls into QEMU's | ||
| 95 | * "firmware" via HCR.TSC, so for these purposes treat | ||
| 96 | * PSCI-via-SMC as implying an EL3. | ||
| 97 | + * This handles the very last line of the previous table. | ||
| 98 | */ | ||
| 99 | - undef = true; | ||
| 100 | - } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) { | ||
| 101 | + raise_exception(env, EXCP_UDEF, syn_uncategorized(), | ||
| 102 | + exception_target_el(env)); | ||
| 103 | + } | ||
| 104 | + | ||
| 105 | + if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) { | ||
| 106 | /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. | ||
| 107 | * We also want an EL2 guest to be able to forbid its EL1 from | ||
| 108 | * making PSCI calls into QEMU's "firmware" via HCR.TSC. | ||
| 109 | + * This handles all the "Trap to EL2" cases of the previous table. | ||
| 110 | */ | ||
| 111 | raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); | ||
| 112 | } | ||
| 113 | |||
| 114 | - /* If PSCI is enabled and this looks like a valid PSCI call then | ||
| 115 | - * suppress the UNDEF -- we'll catch the SMC exception and | ||
| 116 | - * implement the PSCI call behaviour there. | ||
| 117 | + /* Catch the two remaining "Undef insn" cases of the previous table: | ||
| 118 | + * - PSCI conduit is SMC but we don't have a valid PCSI call, | ||
| 119 | + * - We don't have EL3 or SMD is set. | ||
| 120 | */ | ||
| 121 | - if (undef && !arm_is_psci_call(cpu, EXCP_SMC)) { | ||
| 122 | + if (!arm_is_psci_call(cpu, EXCP_SMC) && | ||
| 123 | + (smd || !arm_feature(env, ARM_FEATURE_EL3))) { | ||
| 124 | raise_exception(env, EXCP_UDEF, syn_uncategorized(), | ||
| 125 | exception_target_el(env)); | ||
| 126 | } | ||
| 127 | -- | ||
| 128 | 2.19.1 | ||
| 129 | |||
| 130 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | An off-by-one error in a switch case in onenand_read() allowed | ||
| 2 | a misbehaving guest to read off the end of a block of memory. | ||
| 3 | 1 | ||
| 4 | NB: the onenand device is used only by the "n800" and "n810" | ||
| 5 | machines, which are usable only with TCG, not KVM, so this is | ||
| 6 | not a security issue. | ||
| 7 | |||
| 8 | Reported-by: Thomas Huth <thuth@redhat.com> | ||
| 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | Message-id: 20181115143535.5885-2-peter.maydell@linaro.org | ||
| 13 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | --- | ||
| 16 | hw/block/onenand.c | 2 +- | ||
| 17 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 18 | |||
| 19 | diff --git a/hw/block/onenand.c b/hw/block/onenand.c | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/hw/block/onenand.c | ||
| 22 | +++ b/hw/block/onenand.c | ||
| 23 | @@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr, | ||
| 24 | int offset = addr >> s->shift; | ||
| 25 | |||
| 26 | switch (offset) { | ||
| 27 | - case 0x0000 ... 0xc000: | ||
| 28 | + case 0x0000 ... 0xbffe: | ||
| 29 | return lduw_le_p(s->boot[0] + addr); | ||
| 30 | |||
| 31 | case 0xf000: /* Manufacturer ID */ | ||
| 32 | -- | ||
| 33 | 2.19.1 | ||
| 34 | |||
| 35 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Update the onenand device to use qemu_log_mask() for reporting | ||
| 2 | guest errors and unimplemented features, rather than plain | ||
| 3 | fprintf() and hw_error(). | ||
| 4 | 1 | ||
| 5 | (We leave the hw_error() in onenand_reset(), as that is | ||
| 6 | triggered by a failure to read the underlying block device | ||
| 7 | for the bootRAM, not by guest action.) | ||
| 8 | |||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
| 13 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 14 | Message-id: 20181115143535.5885-3-peter.maydell@linaro.org | ||
| 15 | --- | ||
| 16 | hw/block/onenand.c | 22 +++++++++++++--------- | ||
| 17 | 1 file changed, 13 insertions(+), 9 deletions(-) | ||
| 18 | |||
| 19 | diff --git a/hw/block/onenand.c b/hw/block/onenand.c | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/hw/block/onenand.c | ||
| 22 | +++ b/hw/block/onenand.c | ||
| 23 | @@ -XXX,XX +XXX,XX @@ | ||
| 24 | #include "exec/memory.h" | ||
| 25 | #include "hw/sysbus.h" | ||
| 26 | #include "qemu/error-report.h" | ||
| 27 | +#include "qemu/log.h" | ||
| 28 | |||
| 29 | /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */ | ||
| 30 | #define PAGE_SHIFT 11 | ||
| 31 | @@ -XXX,XX +XXX,XX @@ static void onenand_command(OneNANDState *s) | ||
| 32 | default: | ||
| 33 | s->status |= ONEN_ERR_CMD; | ||
| 34 | s->intstatus |= ONEN_INT; | ||
| 35 | - fprintf(stderr, "%s: unknown OneNAND command %x\n", | ||
| 36 | - __func__, s->command); | ||
| 37 | + qemu_log_mask(LOG_GUEST_ERROR, "unknown OneNAND command %x\n", | ||
| 38 | + s->command); | ||
| 39 | } | ||
| 40 | |||
| 41 | onenand_intr_update(s); | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr, | ||
| 43 | case 0xff02: /* ECC Result of spare area data */ | ||
| 44 | case 0xff03: /* ECC Result of main area data */ | ||
| 45 | case 0xff04: /* ECC Result of spare area data */ | ||
| 46 | - hw_error("%s: implement ECC\n", __func__); | ||
| 47 | + qemu_log_mask(LOG_UNIMP, | ||
| 48 | + "onenand: ECC result registers unimplemented\n"); | ||
| 49 | return 0x0000; | ||
| 50 | } | ||
| 51 | |||
| 52 | - fprintf(stderr, "%s: unknown OneNAND register %x\n", | ||
| 53 | - __func__, offset); | ||
| 54 | + qemu_log_mask(LOG_GUEST_ERROR, "read of unknown OneNAND register 0x%x\n", | ||
| 55 | + offset); | ||
| 56 | return 0; | ||
| 57 | } | ||
| 58 | |||
| 59 | @@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr, | ||
| 60 | break; | ||
| 61 | |||
| 62 | default: | ||
| 63 | - fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n", | ||
| 64 | - __func__, value); | ||
| 65 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 66 | + "unknown OneNAND boot command %" PRIx64 "\n", | ||
| 67 | + value); | ||
| 68 | } | ||
| 69 | break; | ||
| 70 | |||
| 71 | @@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr, | ||
| 72 | break; | ||
| 73 | |||
| 74 | default: | ||
| 75 | - fprintf(stderr, "%s: unknown OneNAND register %x\n", | ||
| 76 | - __func__, offset); | ||
| 77 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
| 78 | + "write to unknown OneNAND register 0x%x\n", | ||
| 79 | + offset); | ||
| 80 | } | ||
| 81 | } | ||
| 82 | |||
| 83 | -- | ||
| 84 | 2.19.1 | ||
| 85 | |||
| 86 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In practice for most of the more-or-less orphan Arm board models, | ||
| 2 | I will review patches and put them in via the target-arm tree. | ||
| 3 | So list myself as an "Odd Fixes" status maintainer for them. | ||
| 4 | 1 | ||
| 5 | This commit downgrades these boards to "Odd Fixes": | ||
| 6 | * Allwinner-A10 | ||
| 7 | * Exynos | ||
| 8 | * Calxeda Highbank | ||
| 9 | * Canon DIGIC | ||
| 10 | * Musicpal | ||
| 11 | * nSeries | ||
| 12 | * Palm | ||
| 13 | * PXA2xx | ||
| 14 | |||
| 15 | These boards were already "Odd Fixes": | ||
| 16 | * Gumstix | ||
| 17 | * i.MX31 (kzm) | ||
| 18 | |||
| 19 | Philippe Mathieu-Daudé has requested to be moved to R: | ||
| 20 | status for Gumstix now that I am listed as the M: contact. | ||
| 21 | |||
| 22 | Some boards are maintained, but their patches still go | ||
| 23 | via the target-arm tree, so add myself as a secondary | ||
| 24 | maintainer contact for those: | ||
| 25 | * Xilinx Zynq | ||
| 26 | * Xilinx ZynqMP | ||
| 27 | * STM32F205 | ||
| 28 | * Netduino 2 | ||
| 29 | * SmartFusion2 | ||
| 30 | * Mecraft M2S-FG484 | ||
| 31 | * ASPEED BMCs | ||
| 32 | * NRF51 | ||
| 33 | |||
| 34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 35 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 36 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
| 37 | Message-id: 20181108134139.31666-1-peter.maydell@linaro.org | ||
| 38 | --- | ||
| 39 | MAINTAINERS | 36 +++++++++++++++++++++++++++--------- | ||
| 40 | 1 file changed, 27 insertions(+), 9 deletions(-) | ||
| 41 | |||
| 42 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 43 | index XXXXXXX..XXXXXXX 100644 | ||
| 44 | --- a/MAINTAINERS | ||
| 45 | +++ b/MAINTAINERS | ||
| 46 | @@ -XXX,XX +XXX,XX @@ ARM Machines | ||
| 47 | ------------ | ||
| 48 | Allwinner-a10 | ||
| 49 | M: Beniamino Galvani <b.galvani@gmail.com> | ||
| 50 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 51 | L: qemu-arm@nongnu.org | ||
| 52 | -S: Maintained | ||
| 53 | +S: Odd Fixes | ||
| 54 | F: hw/*/allwinner* | ||
| 55 | F: include/hw/*/allwinner* | ||
| 56 | F: hw/arm/cubieboard.c | ||
| 57 | @@ -XXX,XX +XXX,XX @@ F: tests/test-arm-mptimer.c | ||
| 58 | |||
| 59 | Exynos | ||
| 60 | M: Igor Mitsyanko <i.mitsyanko@gmail.com> | ||
| 61 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 62 | L: qemu-arm@nongnu.org | ||
| 63 | -S: Maintained | ||
| 64 | +S: Odd Fixes | ||
| 65 | F: hw/*/exynos* | ||
| 66 | F: include/hw/arm/exynos4210.h | ||
| 67 | |||
| 68 | Calxeda Highbank | ||
| 69 | M: Rob Herring <robh@kernel.org> | ||
| 70 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 71 | L: qemu-arm@nongnu.org | ||
| 72 | -S: Maintained | ||
| 73 | +S: Odd Fixes | ||
| 74 | F: hw/arm/highbank.c | ||
| 75 | F: hw/net/xgmac.c | ||
| 76 | |||
| 77 | Canon DIGIC | ||
| 78 | M: Antony Pavlov <antonynpavlov@gmail.com> | ||
| 79 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 80 | L: qemu-arm@nongnu.org | ||
| 81 | -S: Maintained | ||
| 82 | +S: Odd Fixes | ||
| 83 | F: include/hw/arm/digic.h | ||
| 84 | F: hw/*/digic* | ||
| 85 | |||
| 86 | Gumstix | ||
| 87 | -M: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 88 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 89 | +R: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 90 | L: qemu-devel@nongnu.org | ||
| 91 | L: qemu-arm@nongnu.org | ||
| 92 | S: Odd Fixes | ||
| 93 | @@ -XXX,XX +XXX,XX @@ F: hw/arm/gumstix.c | ||
| 94 | |||
| 95 | i.MX31 (kzm) | ||
| 96 | M: Peter Chubb <peter.chubb@nicta.com.au> | ||
| 97 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 98 | L: qemu-arm@nongnu.org | ||
| 99 | S: Odd Fixes | ||
| 100 | F: hw/arm/kzm.c | ||
| 101 | @@ -XXX,XX +XXX,XX @@ F: include/hw/misc/iotkit-sysinfo.h | ||
| 102 | |||
| 103 | Musicpal | ||
| 104 | M: Jan Kiszka <jan.kiszka@web.de> | ||
| 105 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 106 | L: qemu-arm@nongnu.org | ||
| 107 | -S: Maintained | ||
| 108 | +S: Odd Fixes | ||
| 109 | F: hw/arm/musicpal.c | ||
| 110 | |||
| 111 | nSeries | ||
| 112 | M: Andrzej Zaborowski <balrogg@gmail.com> | ||
| 113 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 114 | L: qemu-arm@nongnu.org | ||
| 115 | -S: Maintained | ||
| 116 | +S: Odd Fixes | ||
| 117 | F: hw/arm/nseries.c | ||
| 118 | |||
| 119 | Palm | ||
| 120 | M: Andrzej Zaborowski <balrogg@gmail.com> | ||
| 121 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 122 | L: qemu-arm@nongnu.org | ||
| 123 | -S: Maintained | ||
| 124 | +S: Odd Fixes | ||
| 125 | F: hw/arm/palm.c | ||
| 126 | |||
| 127 | Raspberry Pi | ||
| 128 | @@ -XXX,XX +XXX,XX @@ F: include/hw/intc/realview_gic.h | ||
| 129 | |||
| 130 | PXA2XX | ||
| 131 | M: Andrzej Zaborowski <balrogg@gmail.com> | ||
| 132 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 133 | L: qemu-arm@nongnu.org | ||
| 134 | -S: Maintained | ||
| 135 | +S: Odd Fixes | ||
| 136 | F: hw/arm/mainstone.c | ||
| 137 | F: hw/arm/spitz.c | ||
| 138 | F: hw/arm/tosa.c | ||
| 139 | @@ -XXX,XX +XXX,XX @@ F: include/hw/arm/virt.h | ||
| 140 | Xilinx Zynq | ||
| 141 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | ||
| 142 | M: Alistair Francis <alistair@alistair23.me> | ||
| 143 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 144 | L: qemu-arm@nongnu.org | ||
| 145 | S: Maintained | ||
| 146 | F: hw/*/xilinx_* | ||
| 147 | @@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_* | ||
| 148 | Xilinx ZynqMP | ||
| 149 | M: Alistair Francis <alistair@alistair23.me> | ||
| 150 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | ||
| 151 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 152 | L: qemu-arm@nongnu.org | ||
| 153 | S: Maintained | ||
| 154 | F: hw/*/xlnx*.c | ||
| 155 | @@ -XXX,XX +XXX,XX @@ F: hw/arm/virt-acpi-build.c | ||
| 156 | |||
| 157 | STM32F205 | ||
| 158 | M: Alistair Francis <alistair@alistair23.me> | ||
| 159 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 160 | S: Maintained | ||
| 161 | F: hw/arm/stm32f205_soc.c | ||
| 162 | F: hw/misc/stm32f2xx_syscfg.c | ||
| 163 | @@ -XXX,XX +XXX,XX @@ F: include/hw/*/stm32*.h | ||
| 164 | |||
| 165 | Netduino 2 | ||
| 166 | M: Alistair Francis <alistair@alistair23.me> | ||
| 167 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 168 | S: Maintained | ||
| 169 | F: hw/arm/netduino2.c | ||
| 170 | |||
| 171 | SmartFusion2 | ||
| 172 | M: Subbaraya Sundeep <sundeep.lkml@gmail.com> | ||
| 173 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 174 | S: Maintained | ||
| 175 | F: hw/arm/msf2-soc.c | ||
| 176 | F: hw/misc/msf2-sysreg.c | ||
| 177 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/mss-spi.h | ||
| 178 | |||
| 179 | Emcraft M2S-FG484 | ||
| 180 | M: Subbaraya Sundeep <sundeep.lkml@gmail.com> | ||
| 181 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 182 | S: Maintained | ||
| 183 | F: hw/arm/msf2-som.c | ||
| 184 | |||
| 185 | ASPEED BMCs | ||
| 186 | M: Cédric Le Goater <clg@kaod.org> | ||
| 187 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 188 | R: Andrew Jeffery <andrew@aj.id.au> | ||
| 189 | R: Joel Stanley <joel@jms.id.au> | ||
| 190 | L: qemu-arm@nongnu.org | ||
| 191 | @@ -XXX,XX +XXX,XX @@ F: include/hw/net/ftgmac100.h | ||
| 192 | |||
| 193 | NRF51 | ||
| 194 | M: Joel Stanley <joel@jms.id.au> | ||
| 195 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
| 196 | L: qemu-arm@nongnu.org | ||
| 197 | S: Maintained | ||
| 198 | F: hw/arm/nrf51_soc.c | ||
| 199 | -- | ||
| 200 | 2.19.1 | ||
| 201 | |||
| 202 | diff view generated by jsdifflib |