1 | Some Arm bugfixes for rc2... | 1 | Arm queue; bugfixes only. |
---|---|---|---|
2 | 2 | ||
3 | thanks | 3 | thanks |
4 | -- PMM | 4 | -- PMM |
5 | 5 | ||
6 | The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812: | 6 | The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739: |
7 | 7 | ||
8 | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000) | 8 | Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000) |
9 | 9 | ||
10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117 |
13 | 13 | ||
14 | for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e: | 14 | for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42: |
15 | 15 | ||
16 | MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000) | 16 | tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * various MAINTAINERS file updates | 20 | * hw/arm/virt: ARM_VIRT must select ARM_GIC |
21 | * hw/block/onenand: use qemu_log_mask() for reporting | 21 | * exynos: Fix bad printf format specifiers |
22 | * hw/block/onenand: Fix off-by-one error allowing out-of-bounds read | 22 | * hw/input/ps2.c: Remove remnants of printf debug |
23 | on the n800 and n810 machine models | 23 | * target/openrisc: Remove dead code attempting to check "is timer disabled" |
24 | * target/arm: fix smc incorrectly trapping to EL3 when secure is off | 24 | * register: Remove unnecessary NULL check |
25 | * hw/arm/stm32f205: Fix the UART and Timer region size | 25 | * util/cutils: Fix Coverity array overrun in freq_to_str() |
26 | * target/arm: read ID registers for KVM guests so they can be | 26 | * configure: Make "does libgio work" test pull in some actual functions |
27 | used to gate "is feature X present" checks | 27 | * tmp105: reset the T_low and T_High registers |
28 | * tmp105: Correct handling of temperature limit checks | ||
28 | 29 | ||
29 | ---------------------------------------------------------------- | 30 | ---------------------------------------------------------------- |
30 | Luc Michel (1): | 31 | Alex Chen (1): |
31 | target/arm: fix smc incorrectly trapping to EL3 when secure is off | 32 | exynos: Fix bad printf format specifiers |
32 | 33 | ||
33 | Peter Maydell (3): | 34 | Alistair Francis (1): |
34 | hw/block/onenand: Fix off-by-one error allowing out-of-bounds read | 35 | register: Remove unnecessary NULL check |
35 | hw/block/onenand: use qemu_log_mask() for reporting | ||
36 | MAINTAINERS: list myself as maintainer for various Arm boards | ||
37 | 36 | ||
38 | Richard Henderson (4): | 37 | Andrew Jones (1): |
39 | target/arm: Install ARMISARegisters from kvm host | 38 | hw/arm/virt: ARM_VIRT must select ARM_GIC |
40 | target/arm: Fill in ARMISARegisters for kvm64 | ||
41 | target/arm: Introduce read_sys_reg32 for kvm32 | ||
42 | target/arm: Fill in ARMISARegisters for kvm32 | ||
43 | 39 | ||
44 | Seth Kintigh (1): | 40 | Peter Maydell (5): |
45 | hw/arm/stm32f205: Fix the UART and Timer region size | 41 | hw/input/ps2.c: Remove remnants of printf debug |
42 | target/openrisc: Remove dead code attempting to check "is timer disabled" | ||
43 | configure: Make "does libgio work" test pull in some actual functions | ||
44 | hw/misc/tmp105: reset the T_low and T_High registers | ||
45 | tmp105: Correct handling of temperature limit checks | ||
46 | 46 | ||
47 | Thomas Huth (1): | 47 | Philippe Mathieu-Daudé (1): |
48 | MAINTAINERS: Add entries for missing ARM boards | 48 | util/cutils: Fix Coverity array overrun in freq_to_str() |
49 | 49 | ||
50 | target/arm/kvm_arm.h | 1 + | 50 | configure | 11 +++++-- |
51 | hw/block/onenand.c | 24 +++++----- | 51 | hw/misc/tmp105.h | 7 +++++ |
52 | hw/char/stm32f2xx_usart.c | 2 +- | 52 | hw/core/register.c | 4 --- |
53 | hw/timer/stm32f2xx_timer.c | 2 +- | 53 | hw/input/ps2.c | 9 ------ |
54 | target/arm/kvm.c | 1 + | 54 | hw/misc/tmp105.c | 73 ++++++++++++++++++++++++++++++++++++++------ |
55 | target/arm/kvm32.c | 77 ++++++++++++++++++++------------ | 55 | hw/timer/exynos4210_mct.c | 4 +-- |
56 | target/arm/kvm64.c | 90 +++++++++++++++++++++++++++++++++++++- | 56 | hw/timer/exynos4210_pwm.c | 8 ++--- |
57 | target/arm/op_helper.c | 54 +++++++++++++++++++---- | 57 | target/openrisc/sys_helper.c | 3 -- |
58 | MAINTAINERS | 106 +++++++++++++++++++++++++++++++++++++++------ | 58 | util/cutils.c | 3 +- |
59 | 9 files changed, 293 insertions(+), 64 deletions(-) | 59 | hw/arm/Kconfig | 1 + |
60 | 10 files changed, 89 insertions(+), 34 deletions(-) | ||
60 | 61 | diff view generated by jsdifflib |
1 | An off-by-one error in a switch case in onenand_read() allowed | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | a misbehaving guest to read off the end of a block of memory. | ||
3 | 2 | ||
4 | NB: the onenand device is used only by the "n800" and "n810" | 3 | The removal of the selection of A15MPCORE from ARM_VIRT also |
5 | machines, which are usable only with TCG, not KVM, so this is | 4 | removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC. |
6 | not a security issue. | ||
7 | 5 | ||
8 | Reported-by: Thomas Huth <thuth@redhat.com> | 6 | Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals") |
7 | Reported-by: Miroslav Rezanina <mrezanin@redhat.com> | ||
8 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
9 | Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Message-id: 20201111143440.112763-1-drjones@redhat.com |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Message-id: 20181115143535.5885-2-peter.maydell@linaro.org | ||
13 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 13 | --- |
16 | hw/block/onenand.c | 2 +- | 14 | hw/arm/Kconfig | 1 + |
17 | 1 file changed, 1 insertion(+), 1 deletion(-) | 15 | 1 file changed, 1 insertion(+) |
18 | 16 | ||
19 | diff --git a/hw/block/onenand.c b/hw/block/onenand.c | 17 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
20 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/block/onenand.c | 19 | --- a/hw/arm/Kconfig |
22 | +++ b/hw/block/onenand.c | 20 | +++ b/hw/arm/Kconfig |
23 | @@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr, | 21 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT |
24 | int offset = addr >> s->shift; | 22 | imply VFIO_PLATFORM |
25 | 23 | imply VFIO_XGMAC | |
26 | switch (offset) { | 24 | imply TPM_TIS_SYSBUS |
27 | - case 0x0000 ... 0xc000: | 25 | + select ARM_GIC |
28 | + case 0x0000 ... 0xbffe: | 26 | select ACPI |
29 | return lduw_le_p(s->boot[0] + addr); | 27 | select ARM_SMMUV3 |
30 | 28 | select GPIO_KEY | |
31 | case 0xf000: /* Manufacturer ID */ | ||
32 | -- | 29 | -- |
33 | 2.19.1 | 30 | 2.20.1 |
34 | 31 | ||
35 | 32 | diff view generated by jsdifflib |
1 | From: Luc Michel <luc.michel@greensocs.com> | 1 | From: Alex Chen <alex.chen@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | This commit fixes a case where the CPU would try to go to EL3 when | 3 | We should use printf format specifier "%u" instead of "%d" for |
4 | executing an smc instruction, even though ARM_FEATURE_EL3 is false. This | 4 | argument of type "unsigned int". |
5 | case is raised when the PSCI conduit is set to smc, but the smc | ||
6 | instruction does not lead to a valid PSCI call. | ||
7 | 5 | ||
8 | QEMU crashes with an assertion failure latter on because of incoherent | 6 | Reported-by: Euler Robot <euler.robot@huawei.com> |
9 | mmu_idx. | 7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> |
10 | 8 | Message-id: 20201111073651.72804-1-alex.chen@huawei.com | |
11 | This commit refactors the pre_smc helper by enumerating all the possible | ||
12 | way of handling an scm instruction, and covering the previously missing | ||
13 | case leading to the crash. | ||
14 | |||
15 | The following minimal test would crash before this commit: | ||
16 | |||
17 | .global _start | ||
18 | .text | ||
19 | _start: | ||
20 | ldr x0, =0xdeadbeef ; invalid PSCI call | ||
21 | smc #0 | ||
22 | |||
23 | run with the following command line: | ||
24 | |||
25 | aarch64-linux-gnu-gcc -nostdinc -nostdlib -Wl,-Ttext=40000000 \ | ||
26 | -o test test.s | ||
27 | |||
28 | qemu-system-aarch64 -M virt,virtualization=on,secure=off \ | ||
29 | -cpu cortex-a57 -kernel test | ||
30 | |||
31 | Signed-off-by: Luc Michel <luc.michel@greensocs.com> | ||
32 | Message-id: 20181117160213.18995-1-luc.michel@greensocs.com | ||
33 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
35 | --- | 11 | --- |
36 | target/arm/op_helper.c | 54 +++++++++++++++++++++++++++++++++++------- | 12 | hw/timer/exynos4210_mct.c | 4 ++-- |
37 | 1 file changed, 46 insertions(+), 8 deletions(-) | 13 | hw/timer/exynos4210_pwm.c | 8 ++++---- |
14 | 2 files changed, 6 insertions(+), 6 deletions(-) | ||
38 | 15 | ||
39 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | 16 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c |
40 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/target/arm/op_helper.c | 18 | --- a/hw/timer/exynos4210_mct.c |
42 | +++ b/target/arm/op_helper.c | 19 | +++ b/hw/timer/exynos4210_mct.c |
43 | @@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) | 20 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id) |
44 | ARMCPU *cpu = arm_env_get_cpu(env); | 21 | /* If CSTAT is pending and IRQ is enabled */ |
45 | int cur_el = arm_current_el(env); | 22 | if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) && |
46 | bool secure = arm_is_secure(env); | 23 | (s->reg.int_enb & G_INT_ENABLE(id))) { |
47 | - bool smd = env->cp15.scr_el3 & SCR_SMD; | 24 | - DPRINTF("gcmp timer[%d] IRQ\n", id); |
48 | + bool smd_flag = env->cp15.scr_el3 & SCR_SMD; | 25 | + DPRINTF("gcmp timer[%u] IRQ\n", id); |
49 | + | 26 | qemu_irq_raise(s->irq[id]); |
50 | + /* | ||
51 | + * SMC behaviour is summarized in the following table. | ||
52 | + * This helper handles the "Trap to EL2" and "Undef insn" cases. | ||
53 | + * The "Trap to EL3" and "PSCI call" cases are handled in the exception | ||
54 | + * helper. | ||
55 | + * | ||
56 | + * -> ARM_FEATURE_EL3 and !SMD | ||
57 | + * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 | ||
58 | + * | ||
59 | + * Conduit SMC, valid call Trap to EL2 PSCI Call | ||
60 | + * Conduit SMC, inval call Trap to EL2 Trap to EL3 | ||
61 | + * Conduit not SMC Trap to EL2 Trap to EL3 | ||
62 | + * | ||
63 | + * | ||
64 | + * -> ARM_FEATURE_EL3 and SMD | ||
65 | + * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 | ||
66 | + * | ||
67 | + * Conduit SMC, valid call Trap to EL2 PSCI Call | ||
68 | + * Conduit SMC, inval call Trap to EL2 Undef insn | ||
69 | + * Conduit not SMC Trap to EL2 Undef insn | ||
70 | + * | ||
71 | + * | ||
72 | + * -> !ARM_FEATURE_EL3 | ||
73 | + * HCR_TSC && NS EL1 !HCR_TSC || !NS EL1 | ||
74 | + * | ||
75 | + * Conduit SMC, valid call Trap to EL2 PSCI Call | ||
76 | + * Conduit SMC, inval call Trap to EL2 Undef insn | ||
77 | + * Conduit not SMC Undef insn Undef insn | ||
78 | + */ | ||
79 | + | ||
80 | /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state. | ||
81 | * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization | ||
82 | * extensions, SMD only applies to NS state. | ||
83 | @@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) | ||
84 | * doesn't exist, but we forbid the guest to set it to 1 in scr_write(), | ||
85 | * so we need not special case this here. | ||
86 | */ | ||
87 | - bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure; | ||
88 | + bool smd = arm_feature(env, ARM_FEATURE_AARCH64) ? smd_flag | ||
89 | + : smd_flag && !secure; | ||
90 | |||
91 | if (!arm_feature(env, ARM_FEATURE_EL3) && | ||
92 | cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { | ||
93 | @@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) | ||
94 | * to forbid its EL1 from making PSCI calls into QEMU's | ||
95 | * "firmware" via HCR.TSC, so for these purposes treat | ||
96 | * PSCI-via-SMC as implying an EL3. | ||
97 | + * This handles the very last line of the previous table. | ||
98 | */ | ||
99 | - undef = true; | ||
100 | - } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) { | ||
101 | + raise_exception(env, EXCP_UDEF, syn_uncategorized(), | ||
102 | + exception_target_el(env)); | ||
103 | + } | ||
104 | + | ||
105 | + if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) { | ||
106 | /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. | ||
107 | * We also want an EL2 guest to be able to forbid its EL1 from | ||
108 | * making PSCI calls into QEMU's "firmware" via HCR.TSC. | ||
109 | + * This handles all the "Trap to EL2" cases of the previous table. | ||
110 | */ | ||
111 | raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); | ||
112 | } | 27 | } |
113 | 28 | } | |
114 | - /* If PSCI is enabled and this looks like a valid PSCI call then | 29 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) |
115 | - * suppress the UNDEF -- we'll catch the SMC exception and | 30 | MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); |
116 | - * implement the PSCI call behaviour there. | 31 | |
117 | + /* Catch the two remaining "Undef insn" cases of the previous table: | 32 | if (freq != s->freq) { |
118 | + * - PSCI conduit is SMC but we don't have a valid PCSI call, | 33 | - DPRINTF("freq=%dHz\n", s->freq); |
119 | + * - We don't have EL3 or SMD is set. | 34 | + DPRINTF("freq=%uHz\n", s->freq); |
120 | */ | 35 | |
121 | - if (undef && !arm_is_psci_call(cpu, EXCP_SMC)) { | 36 | /* global timer */ |
122 | + if (!arm_is_psci_call(cpu, EXCP_SMC) && | 37 | tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); |
123 | + (smd || !arm_feature(env, ARM_FEATURE_EL3))) { | 38 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c |
124 | raise_exception(env, EXCP_UDEF, syn_uncategorized(), | 39 | index XXXXXXX..XXXXXXX 100644 |
125 | exception_target_el(env)); | 40 | --- a/hw/timer/exynos4210_pwm.c |
41 | +++ b/hw/timer/exynos4210_pwm.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) | ||
43 | |||
44 | if (freq != s->timer[id].freq) { | ||
45 | ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq); | ||
46 | - DPRINTF("freq=%dHz\n", s->timer[id].freq); | ||
47 | + DPRINTF("freq=%uHz\n", s->timer[id].freq); | ||
126 | } | 48 | } |
49 | } | ||
50 | |||
51 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque) | ||
52 | uint32_t id = s->id; | ||
53 | bool cmp; | ||
54 | |||
55 | - DPRINTF("timer %d tick\n", id); | ||
56 | + DPRINTF("timer %u tick\n", id); | ||
57 | |||
58 | /* set irq status */ | ||
59 | p->reg_tint_cstat |= TINT_CSTAT_STATUS(id); | ||
60 | |||
61 | /* raise IRQ */ | ||
62 | if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) { | ||
63 | - DPRINTF("timer %d IRQ\n", id); | ||
64 | + DPRINTF("timer %u IRQ\n", id); | ||
65 | qemu_irq_raise(p->timer[id].irq); | ||
66 | } | ||
67 | |||
68 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque) | ||
69 | } | ||
70 | |||
71 | if (cmp) { | ||
72 | - DPRINTF("auto reload timer %d count to %x\n", id, | ||
73 | + DPRINTF("auto reload timer %u count to %x\n", id, | ||
74 | p->timer[id].reg_tcntb); | ||
75 | ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb); | ||
76 | ptimer_run(p->timer[id].ptimer, 1); | ||
127 | -- | 77 | -- |
128 | 2.19.1 | 78 | 2.20.1 |
129 | 79 | ||
130 | 80 | diff view generated by jsdifflib |
1 | In practice for most of the more-or-less orphan Arm board models, | 1 | In commit 5edab03d4040 we added tracepoints to the ps2 keyboard |
---|---|---|---|
2 | I will review patches and put them in via the target-arm tree. | 2 | and mouse emulation. However we didn't remove all the debug-by-printf |
3 | So list myself as an "Odd Fixes" status maintainer for them. | 3 | support. In fact there is only one printf() remaining, and it is |
4 | 4 | redundant with the trace_ps2_write_mouse() event next to it. | |
5 | This commit downgrades these boards to "Odd Fixes": | 5 | Remove the printf() and the now-unused DEBUG* macros. |
6 | * Allwinner-A10 | ||
7 | * Exynos | ||
8 | * Calxeda Highbank | ||
9 | * Canon DIGIC | ||
10 | * Musicpal | ||
11 | * nSeries | ||
12 | * Palm | ||
13 | * PXA2xx | ||
14 | |||
15 | These boards were already "Odd Fixes": | ||
16 | * Gumstix | ||
17 | * i.MX31 (kzm) | ||
18 | |||
19 | Philippe Mathieu-Daudé has requested to be moved to R: | ||
20 | status for Gumstix now that I am listed as the M: contact. | ||
21 | |||
22 | Some boards are maintained, but their patches still go | ||
23 | via the target-arm tree, so add myself as a secondary | ||
24 | maintainer contact for those: | ||
25 | * Xilinx Zynq | ||
26 | * Xilinx ZynqMP | ||
27 | * STM32F205 | ||
28 | * Netduino 2 | ||
29 | * SmartFusion2 | ||
30 | * Mecraft M2S-FG484 | ||
31 | * ASPEED BMCs | ||
32 | * NRF51 | ||
33 | 6 | ||
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
35 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
36 | Reviewed-by: Thomas Huth <thuth@redhat.com> | 9 | Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> |
37 | Message-id: 20181108134139.31666-1-peter.maydell@linaro.org | 10 | Message-id: 20201101133258.4240-1-peter.maydell@linaro.org |
38 | --- | 11 | --- |
39 | MAINTAINERS | 36 +++++++++++++++++++++++++++--------- | 12 | hw/input/ps2.c | 9 --------- |
40 | 1 file changed, 27 insertions(+), 9 deletions(-) | 13 | 1 file changed, 9 deletions(-) |
41 | 14 | ||
42 | diff --git a/MAINTAINERS b/MAINTAINERS | 15 | diff --git a/hw/input/ps2.c b/hw/input/ps2.c |
43 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
44 | --- a/MAINTAINERS | 17 | --- a/hw/input/ps2.c |
45 | +++ b/MAINTAINERS | 18 | +++ b/hw/input/ps2.c |
46 | @@ -XXX,XX +XXX,XX @@ ARM Machines | 19 | @@ -XXX,XX +XXX,XX @@ |
47 | ------------ | 20 | |
48 | Allwinner-a10 | 21 | #include "trace.h" |
49 | M: Beniamino Galvani <b.galvani@gmail.com> | 22 | |
50 | +M: Peter Maydell <peter.maydell@linaro.org> | 23 | -/* debug PC keyboard */ |
51 | L: qemu-arm@nongnu.org | 24 | -//#define DEBUG_KBD |
52 | -S: Maintained | 25 | - |
53 | +S: Odd Fixes | 26 | -/* debug PC keyboard : only mouse */ |
54 | F: hw/*/allwinner* | 27 | -//#define DEBUG_MOUSE |
55 | F: include/hw/*/allwinner* | 28 | - |
56 | F: hw/arm/cubieboard.c | 29 | /* Keyboard Commands */ |
57 | @@ -XXX,XX +XXX,XX @@ F: tests/test-arm-mptimer.c | 30 | #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ |
58 | 31 | #define KBD_CMD_ECHO 0xEE | |
59 | Exynos | 32 | @@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val) |
60 | M: Igor Mitsyanko <i.mitsyanko@gmail.com> | 33 | PS2MouseState *s = (PS2MouseState *)opaque; |
61 | +M: Peter Maydell <peter.maydell@linaro.org> | 34 | |
62 | L: qemu-arm@nongnu.org | 35 | trace_ps2_write_mouse(opaque, val); |
63 | -S: Maintained | 36 | -#ifdef DEBUG_MOUSE |
64 | +S: Odd Fixes | 37 | - printf("kbd: write mouse 0x%02x\n", val); |
65 | F: hw/*/exynos* | 38 | -#endif |
66 | F: include/hw/arm/exynos4210.h | 39 | switch(s->common.write_cmd) { |
67 | 40 | default: | |
68 | Calxeda Highbank | 41 | case -1: |
69 | M: Rob Herring <robh@kernel.org> | ||
70 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
71 | L: qemu-arm@nongnu.org | ||
72 | -S: Maintained | ||
73 | +S: Odd Fixes | ||
74 | F: hw/arm/highbank.c | ||
75 | F: hw/net/xgmac.c | ||
76 | |||
77 | Canon DIGIC | ||
78 | M: Antony Pavlov <antonynpavlov@gmail.com> | ||
79 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
80 | L: qemu-arm@nongnu.org | ||
81 | -S: Maintained | ||
82 | +S: Odd Fixes | ||
83 | F: include/hw/arm/digic.h | ||
84 | F: hw/*/digic* | ||
85 | |||
86 | Gumstix | ||
87 | -M: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
88 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
89 | +R: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
90 | L: qemu-devel@nongnu.org | ||
91 | L: qemu-arm@nongnu.org | ||
92 | S: Odd Fixes | ||
93 | @@ -XXX,XX +XXX,XX @@ F: hw/arm/gumstix.c | ||
94 | |||
95 | i.MX31 (kzm) | ||
96 | M: Peter Chubb <peter.chubb@nicta.com.au> | ||
97 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
98 | L: qemu-arm@nongnu.org | ||
99 | S: Odd Fixes | ||
100 | F: hw/arm/kzm.c | ||
101 | @@ -XXX,XX +XXX,XX @@ F: include/hw/misc/iotkit-sysinfo.h | ||
102 | |||
103 | Musicpal | ||
104 | M: Jan Kiszka <jan.kiszka@web.de> | ||
105 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
106 | L: qemu-arm@nongnu.org | ||
107 | -S: Maintained | ||
108 | +S: Odd Fixes | ||
109 | F: hw/arm/musicpal.c | ||
110 | |||
111 | nSeries | ||
112 | M: Andrzej Zaborowski <balrogg@gmail.com> | ||
113 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
114 | L: qemu-arm@nongnu.org | ||
115 | -S: Maintained | ||
116 | +S: Odd Fixes | ||
117 | F: hw/arm/nseries.c | ||
118 | |||
119 | Palm | ||
120 | M: Andrzej Zaborowski <balrogg@gmail.com> | ||
121 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
122 | L: qemu-arm@nongnu.org | ||
123 | -S: Maintained | ||
124 | +S: Odd Fixes | ||
125 | F: hw/arm/palm.c | ||
126 | |||
127 | Raspberry Pi | ||
128 | @@ -XXX,XX +XXX,XX @@ F: include/hw/intc/realview_gic.h | ||
129 | |||
130 | PXA2XX | ||
131 | M: Andrzej Zaborowski <balrogg@gmail.com> | ||
132 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
133 | L: qemu-arm@nongnu.org | ||
134 | -S: Maintained | ||
135 | +S: Odd Fixes | ||
136 | F: hw/arm/mainstone.c | ||
137 | F: hw/arm/spitz.c | ||
138 | F: hw/arm/tosa.c | ||
139 | @@ -XXX,XX +XXX,XX @@ F: include/hw/arm/virt.h | ||
140 | Xilinx Zynq | ||
141 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | ||
142 | M: Alistair Francis <alistair@alistair23.me> | ||
143 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
144 | L: qemu-arm@nongnu.org | ||
145 | S: Maintained | ||
146 | F: hw/*/xilinx_* | ||
147 | @@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_* | ||
148 | Xilinx ZynqMP | ||
149 | M: Alistair Francis <alistair@alistair23.me> | ||
150 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | ||
151 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
152 | L: qemu-arm@nongnu.org | ||
153 | S: Maintained | ||
154 | F: hw/*/xlnx*.c | ||
155 | @@ -XXX,XX +XXX,XX @@ F: hw/arm/virt-acpi-build.c | ||
156 | |||
157 | STM32F205 | ||
158 | M: Alistair Francis <alistair@alistair23.me> | ||
159 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
160 | S: Maintained | ||
161 | F: hw/arm/stm32f205_soc.c | ||
162 | F: hw/misc/stm32f2xx_syscfg.c | ||
163 | @@ -XXX,XX +XXX,XX @@ F: include/hw/*/stm32*.h | ||
164 | |||
165 | Netduino 2 | ||
166 | M: Alistair Francis <alistair@alistair23.me> | ||
167 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
168 | S: Maintained | ||
169 | F: hw/arm/netduino2.c | ||
170 | |||
171 | SmartFusion2 | ||
172 | M: Subbaraya Sundeep <sundeep.lkml@gmail.com> | ||
173 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
174 | S: Maintained | ||
175 | F: hw/arm/msf2-soc.c | ||
176 | F: hw/misc/msf2-sysreg.c | ||
177 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/mss-spi.h | ||
178 | |||
179 | Emcraft M2S-FG484 | ||
180 | M: Subbaraya Sundeep <sundeep.lkml@gmail.com> | ||
181 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
182 | S: Maintained | ||
183 | F: hw/arm/msf2-som.c | ||
184 | |||
185 | ASPEED BMCs | ||
186 | M: Cédric Le Goater <clg@kaod.org> | ||
187 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
188 | R: Andrew Jeffery <andrew@aj.id.au> | ||
189 | R: Joel Stanley <joel@jms.id.au> | ||
190 | L: qemu-arm@nongnu.org | ||
191 | @@ -XXX,XX +XXX,XX @@ F: include/hw/net/ftgmac100.h | ||
192 | |||
193 | NRF51 | ||
194 | M: Joel Stanley <joel@jms.id.au> | ||
195 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
196 | L: qemu-arm@nongnu.org | ||
197 | S: Maintained | ||
198 | F: hw/arm/nrf51_soc.c | ||
199 | -- | 42 | -- |
200 | 2.19.1 | 43 | 2.20.1 |
201 | 44 | ||
202 | 45 | diff view generated by jsdifflib |
1 | From: Seth Kintigh <skintigh@gmail.com> | 1 | In the mtspr helper we attempt to check for "is the timer disabled" |
---|---|---|---|
2 | with "if (env->ttmr & TIMER_NONE)". This is wrong because TIMER_NONE | ||
3 | is zero and the condition is always false (Coverity complains about | ||
4 | the dead code.) | ||
2 | 5 | ||
3 | The UART and timer devices for the stm32f205 were being created | 6 | The correct check would be to test whether the TTMR_M field in the |
4 | with memory regions that were too large. Use the size specified | 7 | register is equal to TIMER_NONE instead. However, the |
5 | in the chip datasheet. | 8 | cpu_openrisc_timer_update() function checks whether the timer is |
9 | enabled (it looks at cpu->env.is_counting, which is set to 0 via | ||
10 | cpu_openrisc_count_stop() when the TTMR_M field is set to | ||
11 | TIMER_NONE), so there's no need to check for "timer disabled" in the | ||
12 | target/openrisc code. Instead, simply remove the dead code. | ||
6 | 13 | ||
7 | The old sizes were so large that the devices would overlap with | 14 | Fixes: Coverity CID 1005812 |
8 | each other in the SoC memory map, so this fixes a bug that | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | caused odd behavior and/or crashes when trying to set up multiple | 16 | Acked-by: Stafford Horne <shorne@gmail.com> |
10 | UARTs. | 17 | Message-id: 20201103114654.18540-1-peter.maydell@linaro.org |
18 | --- | ||
19 | target/openrisc/sys_helper.c | 3 --- | ||
20 | 1 file changed, 3 deletions(-) | ||
11 | 21 | ||
12 | Signed-off-by: Seth Kintigh <skintigh@gmail.com> | 22 | diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c |
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | [PMM: rephrased commit message to follow our usual standard] | ||
15 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
16 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | --- | ||
19 | hw/char/stm32f2xx_usart.c | 2 +- | ||
20 | hw/timer/stm32f2xx_timer.c | 2 +- | ||
21 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
22 | |||
23 | diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/hw/char/stm32f2xx_usart.c | 24 | --- a/target/openrisc/sys_helper.c |
26 | +++ b/hw/char/stm32f2xx_usart.c | 25 | +++ b/target/openrisc/sys_helper.c |
27 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_init(Object *obj) | 26 | @@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) |
28 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | 27 | |
29 | 28 | case TO_SPR(10, 1): /* TTCR */ | |
30 | memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s, | 29 | cpu_openrisc_count_set(cpu, rb); |
31 | - TYPE_STM32F2XX_USART, 0x2000); | 30 | - if (env->ttmr & TIMER_NONE) { |
32 | + TYPE_STM32F2XX_USART, 0x400); | 31 | - return; |
33 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | 32 | - } |
34 | } | 33 | cpu_openrisc_timer_update(cpu); |
35 | 34 | break; | |
36 | diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c | 35 | #endif |
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/hw/timer/stm32f2xx_timer.c | ||
39 | +++ b/hw/timer/stm32f2xx_timer.c | ||
40 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_timer_init(Object *obj) | ||
41 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | ||
42 | |||
43 | memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s, | ||
44 | - "stm32f2xx_timer", 0x4000); | ||
45 | + "stm32f2xx_timer", 0x400); | ||
46 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); | ||
47 | |||
48 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s); | ||
49 | -- | 36 | -- |
50 | 2.19.1 | 37 | 2.20.1 |
51 | 38 | ||
52 | 39 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Alistair Francis <alistair.francis@wdc.com> |
---|---|---|---|
2 | 2 | ||
3 | Assert that the value to be written is the correct size. | 3 | This patch fixes CID 1432800 by removing an unnecessary check. |
4 | No change in functionality here, just mirroring the same | ||
5 | function from kvm64. | ||
6 | 4 | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
8 | Message-id: 20181113180154.17903-4-richard.henderson@linaro.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 8 | --- |
12 | target/arm/kvm32.c | 41 ++++++++++++++++------------------------- | 9 | hw/core/register.c | 4 ---- |
13 | 1 file changed, 16 insertions(+), 25 deletions(-) | 10 | 1 file changed, 4 deletions(-) |
14 | 11 | ||
15 | diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c | 12 | diff --git a/hw/core/register.c b/hw/core/register.c |
16 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/kvm32.c | 14 | --- a/hw/core/register.c |
18 | +++ b/target/arm/kvm32.c | 15 | +++ b/hw/core/register.c |
19 | @@ -XXX,XX +XXX,XX @@ static inline void set_feature(uint64_t *features, int feature) | 16 | @@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner, |
20 | *features |= 1ULL << feature; | 17 | int index = rae[i].addr / data_size; |
21 | } | 18 | RegisterInfo *r = &ri[index]; |
22 | 19 | ||
23 | +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) | 20 | - if (data + data_size * index == 0 || !&rae[i]) { |
24 | +{ | 21 | - continue; |
25 | + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; | ||
26 | + | ||
27 | + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32); | ||
28 | + return ioctl(fd, KVM_GET_ONE_REG, &idreg); | ||
29 | +} | ||
30 | + | ||
31 | bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
32 | { | ||
33 | /* Identify the feature bits corresponding to the host CPU, and | ||
34 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
35 | * we have to create a scratch VM, create a single CPU inside it, | ||
36 | * and then query that CPU for the relevant ID registers. | ||
37 | */ | ||
38 | - int i, ret, fdarray[3]; | ||
39 | + int err = 0, fdarray[3]; | ||
40 | uint32_t midr, id_pfr0, mvfr1; | ||
41 | uint64_t features = 0; | ||
42 | + | ||
43 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
44 | * we know these will only support creating one kind of guest CPU, | ||
45 | * which is its preferred CPU type. | ||
46 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
47 | QEMU_KVM_ARM_TARGET_NONE | ||
48 | }; | ||
49 | struct kvm_vcpu_init init; | ||
50 | - struct kvm_one_reg idregs[] = { | ||
51 | - { | ||
52 | - .id = KVM_REG_ARM | KVM_REG_SIZE_U32 | ||
53 | - | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0), | ||
54 | - .addr = (uintptr_t)&midr, | ||
55 | - }, | ||
56 | - { | ||
57 | - .id = KVM_REG_ARM | KVM_REG_SIZE_U32 | ||
58 | - | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0), | ||
59 | - .addr = (uintptr_t)&id_pfr0, | ||
60 | - }, | ||
61 | - { | ||
62 | - .id = KVM_REG_ARM | KVM_REG_SIZE_U32 | ||
63 | - | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1, | ||
64 | - .addr = (uintptr_t)&mvfr1, | ||
65 | - }, | ||
66 | - }; | ||
67 | |||
68 | if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { | ||
69 | return false; | ||
70 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
71 | */ | ||
72 | ahcf->dtb_compatible = "arm,arm-v7"; | ||
73 | |||
74 | - for (i = 0; i < ARRAY_SIZE(idregs); i++) { | ||
75 | - ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]); | ||
76 | - if (ret) { | ||
77 | - break; | ||
78 | - } | 22 | - } |
79 | - } | 23 | - |
80 | + err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); | 24 | /* Init the register, this will zero it. */ |
81 | + err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0)); | 25 | object_initialize((void *)r, sizeof(*r), TYPE_REGISTER); |
82 | + err |= read_sys_reg32(fdarray[2], &mvfr1, | ||
83 | + KVM_REG_ARM | KVM_REG_SIZE_U32 | | ||
84 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); | ||
85 | |||
86 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
87 | |||
88 | - if (ret) { | ||
89 | + if (err < 0) { | ||
90 | return false; | ||
91 | } | ||
92 | 26 | ||
93 | -- | 27 | -- |
94 | 2.19.1 | 28 | 2.20.1 |
95 | 29 | ||
96 | 30 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | Add entries for the boards "mcimx6ul-evk", "mcimx7d-sabre", "raspi2", | 3 | Fix Coverity CID 1435957: Memory - illegal accesses (OVERRUN): |
4 | "raspi3", "sabrelite", "vexpress-a15", "vexpress-a9" and "virt". | ||
5 | While we're at it, also adjust the "i.MX31" section a little bit, | ||
6 | so that the wildcards there do not match anymore for unrelated files | ||
7 | (e.g. the new hw/misc/imx6ul_ccm.c file). | ||
8 | 4 | ||
9 | Signed-off-by: Thomas Huth <thuth@redhat.com> | 5 | >>> Overrunning array "suffixes" of 7 8-byte elements at element |
10 | Message-id: 1542184999-11145-1-git-send-email-thuth@redhat.com | 6 | index 7 (byte offset 63) using index "idx" (which evaluates to 7). |
7 | |||
8 | Note, the biggest input value freq_to_str() can accept is UINT64_MAX, | ||
9 | which is ~18.446 EHz, less than 1000 EHz. | ||
10 | |||
11 | Reported-by: Eduardo Habkost <ehabkost@redhat.com> | ||
12 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> | ||
15 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
16 | Message-id: 20201101215755.2021421-1-f4bug@amsat.org | ||
17 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 20 | --- |
13 | MAINTAINERS | 70 +++++++++++++++++++++++++++++++++++++++++++++++++---- | 21 | util/cutils.c | 3 ++- |
14 | 1 file changed, 65 insertions(+), 5 deletions(-) | 22 | 1 file changed, 2 insertions(+), 1 deletion(-) |
15 | 23 | ||
16 | diff --git a/MAINTAINERS b/MAINTAINERS | 24 | diff --git a/util/cutils.c b/util/cutils.c |
17 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/MAINTAINERS | 26 | --- a/util/cutils.c |
19 | +++ b/MAINTAINERS | 27 | +++ b/util/cutils.c |
20 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | 28 | @@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz) |
21 | S: Odd Fixes | 29 | double freq = freq_hz; |
22 | F: hw/arm/gumstix.c | 30 | size_t idx = 0; |
23 | 31 | ||
24 | -i.MX31 | 32 | - while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) { |
25 | +i.MX31 (kzm) | 33 | + while (freq >= 1000.0) { |
26 | M: Peter Chubb <peter.chubb@nicta.com.au> | 34 | freq /= 1000.0; |
27 | L: qemu-arm@nongnu.org | 35 | idx++; |
28 | -S: Odd fixes | 36 | } |
29 | -F: hw/*/imx* | 37 | + assert(idx < ARRAY_SIZE(suffixes)); |
30 | -F: include/hw/*/imx* | 38 | |
31 | +S: Odd Fixes | 39 | return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]); |
32 | F: hw/arm/kzm.c | 40 | } |
33 | -F: include/hw/arm/fsl-imx31.h | ||
34 | +F: hw/*/imx_* | ||
35 | +F: hw/*/*imx31* | ||
36 | +F: include/hw/*/imx_* | ||
37 | +F: include/hw/*/*imx31* | ||
38 | |||
39 | Integrator CP | ||
40 | M: Peter Maydell <peter.maydell@linaro.org> | ||
41 | @@ -XXX,XX +XXX,XX @@ S: Maintained | ||
42 | F: hw/arm/integratorcp.c | ||
43 | F: hw/misc/arm_integrator_debug.c | ||
44 | |||
45 | +MCIMX6UL EVK / i.MX6ul | ||
46 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
47 | +R: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
48 | +L: qemu-arm@nongnu.org | ||
49 | +S: Odd Fixes | ||
50 | +F: hw/arm/mcimx6ul-evk.c | ||
51 | +F: hw/arm/fsl-imx6ul.c | ||
52 | +F: hw/misc/imx6ul_ccm.c | ||
53 | +F: include/hw/arm/fsl-imx6ul.h | ||
54 | +F: include/hw/misc/imx6ul_ccm.h | ||
55 | + | ||
56 | +MCIMX7D SABRE / i.MX7 | ||
57 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
58 | +R: Andrey Smirnov <andrew.smirnov@gmail.com> | ||
59 | +L: qemu-arm@nongnu.org | ||
60 | +S: Odd Fixes | ||
61 | +F: hw/arm/mcimx7d-sabre.c | ||
62 | +F: hw/arm/fsl-imx7.c | ||
63 | +F: include/hw/arm/fsl-imx7.h | ||
64 | +F: hw/pci-host/designware.c | ||
65 | +F: include/hw/pci-host/designware.h | ||
66 | + | ||
67 | MPS2 | ||
68 | M: Peter Maydell <peter.maydell@linaro.org> | ||
69 | L: qemu-arm@nongnu.org | ||
70 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
71 | S: Maintained | ||
72 | F: hw/arm/palm.c | ||
73 | |||
74 | +Raspberry Pi | ||
75 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
76 | +R: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
77 | +R: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
78 | +L: qemu-arm@nongnu.org | ||
79 | +S: Odd Fixes | ||
80 | +F: hw/arm/raspi_platform.h | ||
81 | +F: hw/*/bcm283* | ||
82 | +F: include/hw/arm/raspi* | ||
83 | +F: include/hw/*/bcm283* | ||
84 | + | ||
85 | Real View | ||
86 | M: Peter Maydell <peter.maydell@linaro.org> | ||
87 | L: qemu-arm@nongnu.org | ||
88 | @@ -XXX,XX +XXX,XX @@ F: hw/*/pxa2xx* | ||
89 | F: hw/misc/mst_fpga.c | ||
90 | F: include/hw/arm/pxa.h | ||
91 | |||
92 | +SABRELITE / i.MX6 | ||
93 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
94 | +R: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
95 | +L: qemu-arm@nongnu.org | ||
96 | +S: Odd Fixes | ||
97 | +F: hw/arm/sabrelite.c | ||
98 | +F: hw/arm/fsl-imx6.c | ||
99 | +F: hw/misc/imx6_src.c | ||
100 | +F: hw/ssi/imx_spi.c | ||
101 | +F: include/hw/arm/fsl-imx6.h | ||
102 | +F: include/hw/misc/imx6_src.h | ||
103 | +F: include/hw/ssi/imx_spi.h | ||
104 | + | ||
105 | Sharp SL-5500 (Collie) PDA | ||
106 | M: Peter Maydell <peter.maydell@linaro.org> | ||
107 | L: qemu-arm@nongnu.org | ||
108 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
109 | S: Maintained | ||
110 | F: hw/*/stellaris* | ||
111 | |||
112 | +Versatile Express | ||
113 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
114 | +L: qemu-arm@nongnu.org | ||
115 | +S: Maintained | ||
116 | +F: hw/arm/vexpress.c | ||
117 | + | ||
118 | Versatile PB | ||
119 | M: Peter Maydell <peter.maydell@linaro.org> | ||
120 | L: qemu-arm@nongnu.org | ||
121 | @@ -XXX,XX +XXX,XX @@ S: Maintained | ||
122 | F: hw/*/versatile* | ||
123 | F: hw/misc/arm_sysctl.c | ||
124 | |||
125 | +Virt | ||
126 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
127 | +L: qemu-arm@nongnu.org | ||
128 | +S: Maintained | ||
129 | +F: hw/arm/virt* | ||
130 | +F: include/hw/arm/virt.h | ||
131 | + | ||
132 | Xilinx Zynq | ||
133 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | ||
134 | M: Alistair Francis <alistair@alistair23.me> | ||
135 | -- | 41 | -- |
136 | 2.19.1 | 42 | 2.20.1 |
137 | 43 | ||
138 | 44 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | In commit 76346b6264a9b01979 we tried to add a configure check that |
---|---|---|---|
2 | the libgio pkg-config data was correct, which builds an executable | ||
3 | linked against it. Unfortunately this doesn't catch the problem | ||
4 | (missing static library dependency info), because a "do nothing" test | ||
5 | source file doesn't have any symbol references that cause the linker | ||
6 | to pull in .o files from libgio.a, and so we don't see the "missing | ||
7 | symbols from libmount" error that a full QEMU link triggers. | ||
2 | 8 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | (The ineffective test went unnoticed because of a typo that |
4 | Message-id: 20181113180154.17903-3-richard.henderson@linaro.org | 10 | effectively disabled libgio unconditionally, but after commit |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | 3569a5dfc11f2 fixed that, a static link of the system emulator on |
12 | Ubuntu stopped working again.) | ||
13 | |||
14 | Improve the gio test by having the test source fragment reference a | ||
15 | g_dbus function (which is what is indirectly causing us to end up | ||
16 | wanting functions from libmount). | ||
17 | |||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
20 | Message-id: 20201116104617.18333-1-peter.maydell@linaro.org | ||
7 | --- | 21 | --- |
8 | target/arm/kvm64.c | 90 ++++++++++++++++++++++++++++++++++++++++++++-- | 22 | configure | 11 +++++++++-- |
9 | 1 file changed, 88 insertions(+), 2 deletions(-) | 23 | 1 file changed, 9 insertions(+), 2 deletions(-) |
10 | 24 | ||
11 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | 25 | diff --git a/configure b/configure |
12 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100755 |
13 | --- a/target/arm/kvm64.c | 27 | --- a/configure |
14 | +++ b/target/arm/kvm64.c | 28 | +++ b/configure |
15 | @@ -XXX,XX +XXX,XX @@ static inline void unset_feature(uint64_t *features, int feature) | 29 | @@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then |
16 | *features &= ~(1ULL << feature); | 30 | # Check that the libraries actually work -- Ubuntu 18.04 ships |
17 | } | 31 | # with pkg-config --static --libs data for gio-2.0 that is missing |
18 | 32 | # -lblkid and will give a link error. | |
19 | +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) | 33 | - write_c_skeleton |
34 | - if compile_prog "" "$gio_libs" ; then | ||
35 | + cat > $TMPC <<EOF | ||
36 | +#include <gio/gio.h> | ||
37 | +int main(void) | ||
20 | +{ | 38 | +{ |
21 | + uint64_t ret; | 39 | + g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0); |
22 | + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret }; | ||
23 | + int err; | ||
24 | + | ||
25 | + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); | ||
26 | + err = ioctl(fd, KVM_GET_ONE_REG, &idreg); | ||
27 | + if (err < 0) { | ||
28 | + return -1; | ||
29 | + } | ||
30 | + *pret = ret; | ||
31 | + return 0; | 40 | + return 0; |
32 | +} | 41 | +} |
33 | + | 42 | +EOF |
34 | +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) | 43 | + if compile_prog "$gio_cflags" "$gio_libs" ; then |
35 | +{ | 44 | gio=yes |
36 | + struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret }; | 45 | else |
37 | + | 46 | gio=no |
38 | + assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64); | ||
39 | + return ioctl(fd, KVM_GET_ONE_REG, &idreg); | ||
40 | +} | ||
41 | + | ||
42 | bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
43 | { | ||
44 | /* Identify the feature bits corresponding to the host CPU, and | ||
45 | * fill out the ARMHostCPUClass fields accordingly. To do this | ||
46 | * we have to create a scratch VM, create a single CPU inside it, | ||
47 | * and then query that CPU for the relevant ID registers. | ||
48 | - * For AArch64 we currently don't care about ID registers at | ||
49 | - * all; we just want to know the CPU type. | ||
50 | */ | ||
51 | int fdarray[3]; | ||
52 | uint64_t features = 0; | ||
53 | + int err; | ||
54 | + | ||
55 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
56 | * we know these will only support creating one kind of guest CPU, | ||
57 | * which is its preferred CPU type. Fortunately these old kernels | ||
58 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
59 | ahcf->target = init.target; | ||
60 | ahcf->dtb_compatible = "arm,arm-v8"; | ||
61 | |||
62 | + err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, | ||
63 | + ARM64_SYS_REG(3, 0, 0, 4, 0)); | ||
64 | + if (unlikely(err < 0)) { | ||
65 | + /* | ||
66 | + * Before v4.15, the kernel only exposed a limited number of system | ||
67 | + * registers, not including any of the interesting AArch64 ID regs. | ||
68 | + * For the most part we could leave these fields as zero with minimal | ||
69 | + * effect, since this does not affect the values seen by the guest. | ||
70 | + * | ||
71 | + * However, it could cause problems down the line for QEMU, | ||
72 | + * so provide a minimal v8.0 default. | ||
73 | + * | ||
74 | + * ??? Could read MIDR and use knowledge from cpu64.c. | ||
75 | + * ??? Could map a page of memory into our temp guest and | ||
76 | + * run the tiniest of hand-crafted kernels to extract | ||
77 | + * the values seen by the guest. | ||
78 | + * ??? Either of these sounds like too much effort just | ||
79 | + * to work around running a modern host kernel. | ||
80 | + */ | ||
81 | + ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */ | ||
82 | + err = 0; | ||
83 | + } else { | ||
84 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, | ||
85 | + ARM64_SYS_REG(3, 0, 0, 4, 1)); | ||
86 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, | ||
87 | + ARM64_SYS_REG(3, 0, 0, 6, 0)); | ||
88 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, | ||
89 | + ARM64_SYS_REG(3, 0, 0, 6, 1)); | ||
90 | + | ||
91 | + /* | ||
92 | + * Note that if AArch32 support is not present in the host, | ||
93 | + * the AArch32 sysregs are present to be read, but will | ||
94 | + * return UNKNOWN values. This is neither better nor worse | ||
95 | + * than skipping the reads and leaving 0, as we must avoid | ||
96 | + * considering the values in every case. | ||
97 | + */ | ||
98 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, | ||
99 | + ARM64_SYS_REG(3, 0, 0, 2, 0)); | ||
100 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, | ||
101 | + ARM64_SYS_REG(3, 0, 0, 2, 1)); | ||
102 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, | ||
103 | + ARM64_SYS_REG(3, 0, 0, 2, 2)); | ||
104 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, | ||
105 | + ARM64_SYS_REG(3, 0, 0, 2, 3)); | ||
106 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, | ||
107 | + ARM64_SYS_REG(3, 0, 0, 2, 4)); | ||
108 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, | ||
109 | + ARM64_SYS_REG(3, 0, 0, 2, 5)); | ||
110 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, | ||
111 | + ARM64_SYS_REG(3, 0, 0, 2, 7)); | ||
112 | + | ||
113 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, | ||
114 | + ARM64_SYS_REG(3, 0, 0, 3, 0)); | ||
115 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, | ||
116 | + ARM64_SYS_REG(3, 0, 0, 3, 1)); | ||
117 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, | ||
118 | + ARM64_SYS_REG(3, 0, 0, 3, 2)); | ||
119 | + } | ||
120 | + | ||
121 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
122 | |||
123 | + if (err < 0) { | ||
124 | + return false; | ||
125 | + } | ||
126 | + | ||
127 | /* We can assume any KVM supporting CPU is at least a v8 | ||
128 | * with VFPv4+Neon; this in turn implies most of the other | ||
129 | * feature bits. | ||
130 | -- | 47 | -- |
131 | 2.19.1 | 48 | 2.20.1 |
132 | 49 | ||
133 | 50 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the |
---|---|---|---|
2 | power-up reset values for the T_low and T_high registers are 80 degrees C | ||
3 | and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5. These | ||
4 | values are then shifted right by four bits to give the register reset | ||
5 | values, since both registers store the 12 bits of temperature data in bits | ||
6 | [15..4] of a 16 bit register. | ||
2 | 7 | ||
3 | The ID registers are replacing (some of) the feature bits. | 8 | We were resetting these registers to zero, which is problematic for Linux |
4 | We need (some of) these values to determine the set of data | 9 | guests which enable the alert interrupt and then immediately take an |
5 | to be handled during migration. | 10 | unexpected overtemperature alert because the current temperature is above |
11 | freezing... | ||
6 | 12 | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20181113180154.17903-2-richard.henderson@linaro.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
15 | Message-id: 20201110150023.25533-2-peter.maydell@linaro.org | ||
11 | --- | 16 | --- |
12 | target/arm/kvm_arm.h | 1 + | 17 | hw/misc/tmp105.c | 3 +++ |
13 | target/arm/kvm.c | 1 + | 18 | 1 file changed, 3 insertions(+) |
14 | 2 files changed, 2 insertions(+) | ||
15 | 19 | ||
16 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | 20 | diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c |
17 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/kvm_arm.h | 22 | --- a/hw/misc/tmp105.c |
19 | +++ b/target/arm/kvm_arm.h | 23 | +++ b/hw/misc/tmp105.c |
20 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); | 24 | @@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c) |
21 | * by asking the host kernel) | 25 | s->faults = tmp105_faultq[(s->config >> 3) & 3]; |
22 | */ | 26 | s->alarm = 0; |
23 | typedef struct ARMHostCPUFeatures { | 27 | |
24 | + ARMISARegisters isar; | 28 | + s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ |
25 | uint64_t features; | 29 | + s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */ |
26 | uint32_t target; | 30 | + |
27 | const char *dtb_compatible; | 31 | tmp105_interrupt_update(s); |
28 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/kvm.c | ||
31 | +++ b/target/arm/kvm.c | ||
32 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) | ||
33 | |||
34 | cpu->kvm_target = arm_host_cpu_features.target; | ||
35 | cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; | ||
36 | + cpu->isar = arm_host_cpu_features.isar; | ||
37 | env->features = arm_host_cpu_features.features; | ||
38 | } | 32 | } |
39 | 33 | ||
40 | -- | 34 | -- |
41 | 2.19.1 | 35 | 2.20.1 |
42 | 36 | ||
43 | 37 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Message-id: 20181113180154.17903-5-richard.henderson@linaro.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++----- | ||
9 | 1 file changed, 35 insertions(+), 5 deletions(-) | ||
10 | |||
11 | diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/kvm32.c | ||
14 | +++ b/target/arm/kvm32.c | ||
15 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
16 | * and then query that CPU for the relevant ID registers. | ||
17 | */ | ||
18 | int err = 0, fdarray[3]; | ||
19 | - uint32_t midr, id_pfr0, mvfr1; | ||
20 | + uint32_t midr, id_pfr0; | ||
21 | uint64_t features = 0; | ||
22 | |||
23 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | ||
24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
25 | |||
26 | err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0)); | ||
27 | err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0)); | ||
28 | - err |= read_sys_reg32(fdarray[2], &mvfr1, | ||
29 | + | ||
30 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, | ||
31 | + ARM_CP15_REG32(0, 0, 2, 0)); | ||
32 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, | ||
33 | + ARM_CP15_REG32(0, 0, 2, 1)); | ||
34 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, | ||
35 | + ARM_CP15_REG32(0, 0, 2, 2)); | ||
36 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, | ||
37 | + ARM_CP15_REG32(0, 0, 2, 3)); | ||
38 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, | ||
39 | + ARM_CP15_REG32(0, 0, 2, 4)); | ||
40 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, | ||
41 | + ARM_CP15_REG32(0, 0, 2, 5)); | ||
42 | + if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, | ||
43 | + ARM_CP15_REG32(0, 0, 2, 7))) { | ||
44 | + /* | ||
45 | + * Older kernels don't support reading ID_ISAR6. This register was | ||
46 | + * only introduced in ARMv8, so we can assume that it is zero on a | ||
47 | + * CPU that a kernel this old is running on. | ||
48 | + */ | ||
49 | + ahcf->isar.id_isar6 = 0; | ||
50 | + } | ||
51 | + | ||
52 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, | ||
53 | + KVM_REG_ARM | KVM_REG_SIZE_U32 | | ||
54 | + KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); | ||
55 | + err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, | ||
56 | KVM_REG_ARM | KVM_REG_SIZE_U32 | | ||
57 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1); | ||
58 | + /* | ||
59 | + * FIXME: There is not yet a way to read MVFR2. | ||
60 | + * Fortunately there is not yet anything in there that affects migration. | ||
61 | + */ | ||
62 | |||
63 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
64 | |||
65 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
66 | if (extract32(id_pfr0, 12, 4) == 1) { | ||
67 | set_feature(&features, ARM_FEATURE_THUMB2EE); | ||
68 | } | ||
69 | - if (extract32(mvfr1, 20, 4) == 1) { | ||
70 | + if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) { | ||
71 | set_feature(&features, ARM_FEATURE_VFP_FP16); | ||
72 | } | ||
73 | - if (extract32(mvfr1, 12, 4) == 1) { | ||
74 | + if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) { | ||
75 | set_feature(&features, ARM_FEATURE_NEON); | ||
76 | } | ||
77 | - if (extract32(mvfr1, 28, 4) == 1) { | ||
78 | + if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) { | ||
79 | /* FMAC support implies VFPv4 */ | ||
80 | set_feature(&features, ARM_FEATURE_VFP4); | ||
81 | } | ||
82 | -- | ||
83 | 2.19.1 | ||
84 | |||
85 | diff view generated by jsdifflib |
1 | Update the onenand device to use qemu_log_mask() for reporting | 1 | The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device |
---|---|---|---|
2 | guest errors and unimplemented features, rather than plain | 2 | signals an alert when the temperature equals or exceeds the T_high value and |
3 | fprintf() and hw_error(). | 3 | then remains high until a device register is read or the device responds to |
4 | the SMBUS Alert Response address, or the device is put into Shutdown Mode. | ||
5 | Thereafter the Alert pin will only be re-signalled when temperature falls | ||
6 | below T_low; alert can then be cleared in the same set of ways, and the | ||
7 | device returns to its initial "alert when temperature goes above T_high" | ||
8 | mode. (If this textual description is confusing, see figure 3 in the | ||
9 | TI datasheet at https://www.ti.com/lit/gpn/tmp105 .) | ||
4 | 10 | ||
5 | (We leave the hw_error() in onenand_reset(), as that is | 11 | We were misimplementing this as a simple "always alert if temperature is |
6 | triggered by a failure to read the underlying block device | 12 | above T_high or below T_low" condition, which gives a spurious alert on |
7 | for the bootRAM, not by guest action.) | 13 | startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset |
14 | limit values. | ||
15 | |||
16 | Implement the correct (hysteresis) behaviour by tracking whether we | ||
17 | are currently looking for the temperature to rise over T_high or | ||
18 | for it to fall below T_low. Our implementation of the comparator | ||
19 | mode (TM==0) wasn't wrong, but rephrase it to match the way that | ||
20 | interrupt mode is now handled for clarity. | ||
8 | 21 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 23 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 24 | Message-id: 20201110150023.25533-3-peter.maydell@linaro.org |
12 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
13 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
14 | Message-id: 20181115143535.5885-3-peter.maydell@linaro.org | ||
15 | --- | 25 | --- |
16 | hw/block/onenand.c | 22 +++++++++++++--------- | 26 | hw/misc/tmp105.h | 7 +++++ |
17 | 1 file changed, 13 insertions(+), 9 deletions(-) | 27 | hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++------- |
28 | 2 files changed, 68 insertions(+), 9 deletions(-) | ||
18 | 29 | ||
19 | diff --git a/hw/block/onenand.c b/hw/block/onenand.c | 30 | diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h |
20 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/block/onenand.c | 32 | --- a/hw/misc/tmp105.h |
22 | +++ b/hw/block/onenand.c | 33 | +++ b/hw/misc/tmp105.h |
23 | @@ -XXX,XX +XXX,XX @@ | 34 | @@ -XXX,XX +XXX,XX @@ struct TMP105State { |
24 | #include "exec/memory.h" | 35 | int16_t limit[2]; |
25 | #include "hw/sysbus.h" | 36 | int faults; |
26 | #include "qemu/error-report.h" | 37 | uint8_t alarm; |
27 | +#include "qemu/log.h" | 38 | + /* |
28 | 39 | + * The TMP105 initially looks for a temperature rising above T_high; | |
29 | /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */ | 40 | + * once this is detected, the condition it looks for next is the |
30 | #define PAGE_SHIFT 11 | 41 | + * temperature falling below T_low. This flag is false when initially |
31 | @@ -XXX,XX +XXX,XX @@ static void onenand_command(OneNANDState *s) | 42 | + * looking for T_high, true when looking for T_low. |
32 | default: | 43 | + */ |
33 | s->status |= ONEN_ERR_CMD; | 44 | + bool detect_falling; |
34 | s->intstatus |= ONEN_INT; | 45 | }; |
35 | - fprintf(stderr, "%s: unknown OneNAND command %x\n", | 46 | |
36 | - __func__, s->command); | 47 | #endif |
37 | + qemu_log_mask(LOG_GUEST_ERROR, "unknown OneNAND command %x\n", | 48 | diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c |
38 | + s->command); | 49 | index XXXXXXX..XXXXXXX 100644 |
50 | --- a/hw/misc/tmp105.c | ||
51 | +++ b/hw/misc/tmp105.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s) | ||
53 | return; | ||
39 | } | 54 | } |
40 | 55 | ||
41 | onenand_intr_update(s); | 56 | - if ((s->config >> 1) & 1) { /* TM */ |
42 | @@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr, | 57 | - if (s->temperature >= s->limit[1]) |
43 | case 0xff02: /* ECC Result of spare area data */ | 58 | - s->alarm = 1; |
44 | case 0xff03: /* ECC Result of main area data */ | 59 | - else if (s->temperature < s->limit[0]) |
45 | case 0xff04: /* ECC Result of spare area data */ | 60 | - s->alarm = 1; |
46 | - hw_error("%s: implement ECC\n", __func__); | 61 | + if (s->config >> 1 & 1) { |
47 | + qemu_log_mask(LOG_UNIMP, | 62 | + /* |
48 | + "onenand: ECC result registers unimplemented\n"); | 63 | + * TM == 1 : Interrupt mode. We signal Alert when the |
49 | return 0x0000; | 64 | + * temperature rises above T_high, and expect the guest to clear |
65 | + * it (eg by reading a device register). | ||
66 | + */ | ||
67 | + if (s->detect_falling) { | ||
68 | + if (s->temperature < s->limit[0]) { | ||
69 | + s->alarm = 1; | ||
70 | + s->detect_falling = false; | ||
71 | + } | ||
72 | + } else { | ||
73 | + if (s->temperature >= s->limit[1]) { | ||
74 | + s->alarm = 1; | ||
75 | + s->detect_falling = true; | ||
76 | + } | ||
77 | + } | ||
78 | } else { | ||
79 | - if (s->temperature >= s->limit[1]) | ||
80 | - s->alarm = 1; | ||
81 | - else if (s->temperature < s->limit[0]) | ||
82 | - s->alarm = 0; | ||
83 | + /* | ||
84 | + * TM == 0 : Comparator mode. We signal Alert when the temperature | ||
85 | + * rises above T_high, and stop signalling it when the temperature | ||
86 | + * falls below T_low. | ||
87 | + */ | ||
88 | + if (s->detect_falling) { | ||
89 | + if (s->temperature < s->limit[0]) { | ||
90 | + s->alarm = 0; | ||
91 | + s->detect_falling = false; | ||
92 | + } | ||
93 | + } else { | ||
94 | + if (s->temperature >= s->limit[1]) { | ||
95 | + s->alarm = 1; | ||
96 | + s->detect_falling = true; | ||
97 | + } | ||
98 | + } | ||
50 | } | 99 | } |
51 | 100 | ||
52 | - fprintf(stderr, "%s: unknown OneNAND register %x\n", | 101 | tmp105_interrupt_update(s); |
53 | - __func__, offset); | 102 | @@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id) |
54 | + qemu_log_mask(LOG_GUEST_ERROR, "read of unknown OneNAND register 0x%x\n", | ||
55 | + offset); | ||
56 | return 0; | 103 | return 0; |
57 | } | 104 | } |
58 | 105 | ||
59 | @@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr, | 106 | +static bool detect_falling_needed(void *opaque) |
60 | break; | 107 | +{ |
61 | 108 | + TMP105State *s = opaque; | |
62 | default: | 109 | + |
63 | - fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n", | 110 | + /* |
64 | - __func__, value); | 111 | + * We only need to migrate the detect_falling bool if it's set; |
65 | + qemu_log_mask(LOG_GUEST_ERROR, | 112 | + * for migration from older machines we assume that it is false |
66 | + "unknown OneNAND boot command %" PRIx64 "\n", | 113 | + * (ie temperature is not out of range). |
67 | + value); | 114 | + */ |
68 | } | 115 | + return s->detect_falling; |
69 | break; | 116 | +} |
70 | 117 | + | |
71 | @@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr, | 118 | +static const VMStateDescription vmstate_tmp105_detect_falling = { |
72 | break; | 119 | + .name = "TMP105/detect-falling", |
73 | 120 | + .version_id = 1, | |
74 | default: | 121 | + .minimum_version_id = 1, |
75 | - fprintf(stderr, "%s: unknown OneNAND register %x\n", | 122 | + .needed = detect_falling_needed, |
76 | - __func__, offset); | 123 | + .fields = (VMStateField[]) { |
77 | + qemu_log_mask(LOG_GUEST_ERROR, | 124 | + VMSTATE_BOOL(detect_falling, TMP105State), |
78 | + "write to unknown OneNAND register 0x%x\n", | 125 | + VMSTATE_END_OF_LIST() |
79 | + offset); | 126 | + } |
127 | +}; | ||
128 | + | ||
129 | static const VMStateDescription vmstate_tmp105 = { | ||
130 | .name = "TMP105", | ||
131 | .version_id = 0, | ||
132 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = { | ||
133 | VMSTATE_UINT8(alarm, TMP105State), | ||
134 | VMSTATE_I2C_SLAVE(i2c, TMP105State), | ||
135 | VMSTATE_END_OF_LIST() | ||
136 | + }, | ||
137 | + .subsections = (const VMStateDescription*[]) { | ||
138 | + &vmstate_tmp105_detect_falling, | ||
139 | + NULL | ||
80 | } | 140 | } |
81 | } | 141 | }; |
82 | 142 | ||
143 | @@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c) | ||
144 | s->config = 0; | ||
145 | s->faults = tmp105_faultq[(s->config >> 3) & 3]; | ||
146 | s->alarm = 0; | ||
147 | + s->detect_falling = false; | ||
148 | |||
149 | s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ | ||
150 | s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */ | ||
83 | -- | 151 | -- |
84 | 2.19.1 | 152 | 2.20.1 |
85 | 153 | ||
86 | 154 | diff view generated by jsdifflib |