| 1 | v2: fix compile failure on arm hosts... | 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: |
|---|---|---|---|
| 2 | we were using uninitialized data for the guarded bit when | ||
| 3 | combining stage 1 and stage 2 attrs. | ||
| 2 | 4 | ||
| 3 | thanks | 5 | thanks |
| 4 | -- PMM | 6 | -- PMM |
| 5 | 7 | ||
| 6 | The following changes since commit 6db87aae61bc6ac0a8cd9bc2e05d7ebfbcfd3657: | 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: |
| 7 | 9 | ||
| 8 | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-12 17:11:22 +0000) | 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) |
| 9 | 11 | ||
| 10 | are available in the Git repository at: | 12 | are available in the Git repository at: |
| 11 | 13 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181113 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 |
| 13 | 15 | ||
| 14 | for you to fetch changes up to 436c0cbbeb38dd97c02fe921a7cb253a18afdd86: | 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: |
| 15 | 17 | ||
| 16 | target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature (2018-11-13 10:47:59 +0000) | 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) |
| 17 | 19 | ||
| 18 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 19 | target/arm queue: | 21 | target-arm: Fix bug where we weren't initializing |
| 20 | * Remove no-longer-needed workaround for small SAU regions for v8M | 22 | guarded bit state when combining S1/S2 attrs |
| 21 | * Remove antique TODO comment | ||
| 22 | * MAINTAINERS: Add an entry for the 'collie' machine | ||
| 23 | * hw/arm/sysbus-fdt: Only call match_fn callback if the type matches | ||
| 24 | * Fix infinite recursion in tlbi_aa64_vmalle1_write() | ||
| 25 | * ARM KVM: fix various bugs in handling of guest debugging | ||
| 26 | * Correctly implement handling of HCR_EL2.{VI, VF} | ||
| 27 | * Hyp mode R14 is shared with User and System | ||
| 28 | * Give Cortex-A15 and -A7 the EL2 feature | ||
| 29 | 23 | ||
| 30 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 31 | Alex Bennée (6): | 25 | Richard Henderson (2): |
| 32 | target/arm64: properly handle DBGVR RESS bits | 26 | target/arm: PTE bit GP only applies to stage1 |
| 33 | target/arm64: hold BQL when calling do_interrupt() | 27 | target/arm: Copy guarded bit in combine_cacheattrs |
| 34 | target/arm64: kvm debug set target_el when passing exception to guest | ||
| 35 | tests/guest-debug: fix scoping of failcount | ||
| 36 | arm: use symbolic MDCR_TDE in arm_debug_target_el | ||
| 37 | arm: fix aa64_generate_debug_exceptions to work with EL2 | ||
| 38 | 28 | ||
| 39 | Eric Auger (1): | 29 | target/arm/ptw.c | 11 ++++++----- |
| 40 | hw/arm/sysbus-fdt: Only call match_fn callback if the type matches | 30 | 1 file changed, 6 insertions(+), 5 deletions(-) |
| 41 | |||
| 42 | Peter Maydell (7): | ||
| 43 | target/arm: Remove workaround for small SAU regions | ||
| 44 | target/arm: Remove antique TODO comment | ||
| 45 | Revert "target/arm: Implement HCR.VI and VF" | ||
| 46 | target/arm: Track the state of our irq lines from the GIC explicitly | ||
| 47 | target/arm: Correctly implement handling of HCR_EL2.{VI, VF} | ||
| 48 | target/arm: Hyp mode R14 is shared with User and System | ||
| 49 | target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature | ||
| 50 | |||
| 51 | Richard Henderson (1): | ||
| 52 | target/arm: Fix typo in tlbi_aa64_vmalle1_write | ||
| 53 | |||
| 54 | Thomas Huth (1): | ||
| 55 | MAINTAINERS: Add an entry for the 'collie' machine | ||
| 56 | |||
| 57 | target/arm/cpu.h | 44 +++++++++++------ | ||
| 58 | target/arm/internals.h | 34 +++++++++++++ | ||
| 59 | hw/arm/sysbus-fdt.c | 12 +++-- | ||
| 60 | target/arm/cpu.c | 67 ++++++++++++++++++++++++- | ||
| 61 | target/arm/helper.c | 101 +++++++++++++------------------------- | ||
| 62 | target/arm/kvm32.c | 4 +- | ||
| 63 | target/arm/kvm64.c | 20 +++++++- | ||
| 64 | target/arm/machine.c | 51 +++++++++++++++++++ | ||
| 65 | target/arm/op_helper.c | 4 +- | ||
| 66 | MAINTAINERS | 7 +++ | ||
| 67 | tests/guest-debug/test-gdbstub.py | 1 + | ||
| 68 | 11 files changed, 249 insertions(+), 96 deletions(-) | ||
| 69 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Only perform the extract of GP during the stage1 walk. | ||
| 4 | |||
| 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 10 +++++----- | ||
| 12 | 1 file changed, 5 insertions(+), 5 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 19 | result->f.attrs.secure = false; | ||
| 20 | } | ||
| 21 | |||
| 22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 25 | - } | ||
| 26 | - | ||
| 27 | if (regime_is_stage2(mmu_idx)) { | ||
| 28 | result->cacheattrs.is_s2_format = true; | ||
| 29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 31 | assert(attrindx <= 7); | ||
| 32 | result->cacheattrs.is_s2_format = false; | ||
| 33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
| 34 | + | ||
| 35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 38 | + } | ||
| 39 | } | ||
| 40 | |||
| 41 | /* | ||
| 42 | -- | ||
| 43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | The guarded bit comes from the stage1 walk. | ||
| 4 | |||
| 5 | Fixes: Coverity CID 1507929 | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 1 + | ||
| 12 | 1 file changed, 1 insertion(+) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, | ||
| 19 | |||
| 20 | assert(!s1.is_s2_format); | ||
| 21 | ret.is_s2_format = false; | ||
| 22 | + ret.guarded = s1.guarded; | ||
| 23 | |||
| 24 | if (s1.attrs == 0xf0) { | ||
| 25 | tagged = true; | ||
| 26 | -- | ||
| 27 | 2.34.1 | diff view generated by jsdifflib |