1
Handful of bugfix patches for arm for rc0; also
1
Squashed in a trivial fix for 32-bit hosts:
2
one milkymist patch, thrown in since I was putting
3
the pullreq together anyway.
4
2
5
thanks
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
9
- acc = int128_add(acc, 1 << 7); \
10
+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
14
6
-- PMM
15
-- PMM
7
16
8
The following changes since commit 03c1ca1c51783603d42eb0f91d35961f0f4b4947:
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
9
18
10
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20181105' into staging (2018-11-06 09:10:46 +0000)
19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
11
20
12
are available in the Git repository at:
21
are available in the Git repository at:
13
22
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181106
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
15
24
16
for you to fetch changes up to 23463e0e4aeb2f0a9c60549a2c163f4adc0b8512:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
17
26
18
target/arm: Fix ATS1Hx instructions (2018-11-06 11:32:14 +0000)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
19
28
20
----------------------------------------------------------------
29
----------------------------------------------------------------
21
target-arm queue:
30
target-arm queue:
22
* Remove can't-happen if() from handle_vec_simd_shli()
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
23
* hw/arm/exynos4210: Zero memory allocated for Exynos4210State
32
* docs: Document which architecture extensions we emulate
24
* Set S and PTW in 64-bit PAR format
33
* Fix bugs in M-profile FPCXT_NS accesses
25
* Fix ATS1Hx instructions
34
* First slice of MVE patches
26
* milkymist: Check for failure trying to load BIOS image
35
* Implement MTE3
36
* docs/system: arm: Add nRF boards description
27
37
28
----------------------------------------------------------------
38
----------------------------------------------------------------
29
Peter Maydell (5):
39
Alexandre Iooss (1):
30
target/arm: Remove can't-happen if() from handle_vec_simd_shli()
40
docs/system: arm: Add nRF boards description
31
milkymist: Check for failure trying to load BIOS image
32
hw/arm/exynos4210: Zero memory allocated for Exynos4210State
33
target/arm: Set S and PTW in 64-bit PAR format
34
target/arm: Fix ATS1Hx instructions
35
41
36
hw/arm/exynos4210.c | 2 +-
42
Peter Collingbourne (1):
37
hw/lm32/milkymist.c | 5 ++++-
43
target/arm: Implement MTE3
38
target/arm/helper.c | 14 ++++++++------
39
target/arm/translate-a64.c | 8 +++-----
40
4 files changed, 16 insertions(+), 13 deletions(-)
41
44
45
Peter Maydell (55):
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
47
hw/acpi: Provide function acpi_ghes_present()
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
49
docs/system/arm: Document which architecture extensions we emulate
50
target/arm/translate-vfp.c: Whitespace fixes
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
54
target/arm: Factor FP context update code out into helper function
55
target/arm: Split vfp_access_check() into A and M versions
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
59
target/arm: Implement MVE VCLZ
60
target/arm: Implement MVE VCLS
61
target/arm: Implement MVE VREV16, VREV32, VREV64
62
target/arm: Implement MVE VMVN (register)
63
target/arm: Implement MVE VABS
64
target/arm: Implement MVE VNEG
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
101
102
docs/system/arm/emulation.rst | 103 ++++
103
docs/system/arm/nrf.rst | 51 ++
104
docs/system/target-arm.rst | 7 +
105
include/hw/acpi/ghes.h | 9 +
106
include/tcg/tcg-op.h | 8 +
107
include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
109
target/arm/helper.h | 2 +
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
135
diff view generated by jsdifflib
Deleted patch
1
In handle_vec_simd_shli() we have a check:
2
if (size > 3 && !is_q) {
3
unallocated_encoding(s);
4
return;
5
}
6
However this can never be true, because we calculate
7
int size = 32 - clz32(immh) - 1;
8
where immh is a 4 bit field which we know cannot be all-zeroes.
9
So the clz32() return must be in {28,29,30,31} and the resulting
10
size is in {0,1,2,3}, and "size > 3" is never true.
11
1
12
This unnecessary code confuses Coverity's analysis:
13
in CID 1396476 it thinks we might later index off the
14
end of an array because the condition implies that we
15
might have a size > 3.
16
17
Remove the code, and instead assert that the size is in [0..3],
18
since the decode that enforces that is somewhat distant from
19
this function.
20
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
23
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
24
Tested-by: Alex Bennée <alex.bennee@linaro.org>
25
Message-id: 20181030162517.21816-1-peter.maydell@linaro.org
26
---
27
target/arm/translate-a64.c | 8 +++-----
28
1 file changed, 3 insertions(+), 5 deletions(-)
29
30
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/translate-a64.c
33
+++ b/target/arm/translate-a64.c
34
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
35
int immhb = immh << 3 | immb;
36
int shift = immhb - (8 << size);
37
38
- if (extract32(immh, 3, 1) && !is_q) {
39
- unallocated_encoding(s);
40
- return;
41
- }
42
+ /* Range of size is limited by decode: immh is a non-zero 4 bit field */
43
+ assert(size >= 0 && size <= 3);
44
45
- if (size > 3 && !is_q) {
46
+ if (extract32(immh, 3, 1) && !is_q) {
47
unallocated_encoding(s);
48
return;
49
}
50
--
51
2.19.1
52
53
diff view generated by jsdifflib
Deleted patch
1
Check the return value from load_image_targphys(), which tells us
2
whether our attempt to load the BIOS image into RAM failed.
3
(Spotted by Coverity, CID 1190305.)
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Acked-by: Michael Walle <michael@walle.cc>
8
Message-id: 20181030170032.1844-1-peter.maydell@linaro.org
9
---
10
hw/lm32/milkymist.c | 5 ++++-
11
1 file changed, 4 insertions(+), 1 deletion(-)
12
13
diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/lm32/milkymist.c
16
+++ b/hw/lm32/milkymist.c
17
@@ -XXX,XX +XXX,XX @@ milkymist_init(MachineState *machine)
18
bios_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
19
20
if (bios_filename) {
21
- load_image_targphys(bios_filename, BIOS_OFFSET, BIOS_SIZE);
22
+ if (load_image_targphys(bios_filename, BIOS_OFFSET, BIOS_SIZE) < 0) {
23
+ error_report("could not load bios '%s'", bios_filename);
24
+ exit(1);
25
+ }
26
}
27
28
reset_info->bootstrap_pc = BIOS_OFFSET;
29
--
30
2.19.1
31
32
diff view generated by jsdifflib
Deleted patch
1
In exynos4210_init() we allocate memory for an Exynos4210State
2
struct. Generally devices can assume that the memory allocated
3
for their state struct is zero-initialized; we broke that
4
assumption here by using g_new(). Use g_new0() instead.
5
(In particular, some code assumes that the various irq arrays
6
in the Exynos4210Irq sub-struct are zero-initialized.)
7
1
8
In the longer term, this code should be QOMified, and then
9
the struct memory will be allocated elsewhere and by functions
10
which always zero-initalize it; but for 3.1 this is a
11
simple fix.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Message-id: 20181105151132.13884-1-peter.maydell@linaro.org
17
---
18
hw/arm/exynos4210.c | 2 +-
19
1 file changed, 1 insertion(+), 1 deletion(-)
20
21
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/exynos4210.c
24
+++ b/hw/arm/exynos4210.c
25
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
26
27
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
28
{
29
- Exynos4210State *s = g_new(Exynos4210State, 1);
30
+ Exynos4210State *s = g_new0(Exynos4210State, 1);
31
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
32
SysBusDevice *busdev;
33
DeviceState *dev;
34
--
35
2.19.1
36
37
diff view generated by jsdifflib
Deleted patch
1
In do_ats_write() we construct a PAR value based on the result
2
of the translation. A comment says "S2WLK and FSTAGE are always
3
zero, because we don't implement virtualization".
4
Since we do in fact now implement virtualization, add the missing
5
code that sets these bits based on the reported ARMMMUFaultInfo.
6
1
7
(These bits are named PTW and S in ARMv8, so we follow that
8
convention in the new comments in this patch.)
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20181016093703.10637-2-peter.maydell@linaro.org
14
---
15
target/arm/helper.c | 10 ++++++----
16
1 file changed, 6 insertions(+), 4 deletions(-)
17
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.c
21
+++ b/target/arm/helper.c
22
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
23
24
par64 |= 1; /* F */
25
par64 |= (fsr & 0x3f) << 1; /* FS */
26
- /* Note that S2WLK and FSTAGE are always zero, because we don't
27
- * implement virtualization and therefore there can't be a stage 2
28
- * fault.
29
- */
30
+ if (fi.stage2) {
31
+ par64 |= (1 << 9); /* S */
32
+ }
33
+ if (fi.s1ptw) {
34
+ par64 |= (1 << 8); /* PTW */
35
+ }
36
}
37
} else {
38
/* fsr is a DFSR/IFSR value for the short descriptor
39
--
40
2.19.1
41
42
diff view generated by jsdifflib
Deleted patch
1
ATS1HR and ATS1HW (which allow AArch32 EL2 to do address translations
2
on the EL2 translation regime) were implemented in commit 14db7fe09a2c8.
3
However, we got them wrong: these should do stage 1 address translations
4
as defined for NS-EL2, which is ARMMMUIdx_S1E2. We were incorrectly
5
making them perform stage 2 translations.
6
1
7
A few years later in commit 1313e2d7e2cd we forgot entirely that
8
we'd implemented ATS1Hx, and added a comment that ATS1Hx were
9
"not supported yet". Remove the comment; there is no extra code
10
needed to handle these operations in do_ats_write(), because
11
arm_s1_regime_using_lpae_format() returns true for ARMMMUIdx_S1E2,
12
which forces 64-bit PAR format.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
Message-id: 20181016093703.10637-3-peter.maydell@linaro.org
17
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
18
---
19
target/arm/helper.c | 4 ++--
20
1 file changed, 2 insertions(+), 2 deletions(-)
21
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
25
+++ b/target/arm/helper.c
26
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
27
*
28
* (Note that HCR.DC makes HCR.VM behave as if it is 1.)
29
*
30
- * ATS1Hx always uses the 64bit format (not supported yet).
31
+ * ATS1Hx always uses the 64bit format.
32
*/
33
format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
34
35
@@ -XXX,XX +XXX,XX @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
36
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
37
uint64_t par64;
38
39
- par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
40
+ par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2);
41
42
A32_BANKED_CURRENT_REG_SET(env, par, par64);
43
}
44
--
45
2.19.1
46
47
diff view generated by jsdifflib