1 | Respin to fix some accidental wrong Author lines, no content | 1 | no changes to v1, except adding the CVE identifier to one of the commit |
---|---|---|---|
2 | changes. | 2 | messages. |
3 | 3 | ||
4 | -- PMM | 4 | -- PMM |
5 | 5 | ||
6 | The following changes since commit 0bbba1665ca2e7f1c80d4797077fe57bad58898e: | 6 | The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e: |
7 | 7 | ||
8 | Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-october-2018-part-4' into staging (2018-10-30 10:45:49 +0000) | 8 | Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 16:28:00 +0000) |
9 | 9 | ||
10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181030 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210203 |
13 | 13 | ||
14 | for you to fetch changes up to 1f5a65a188210509bfb0c025fc91635c8436b98a: | 14 | for you to fetch changes up to fd8f71b95da86f530aae3d02a14b0ccd9e024772: |
15 | 15 | ||
16 | tests/boot-serial-test: Add microbit board testcase (2018-10-30 13:20:18 +0000) | 16 | hw/arm: Display CPU type in machine description (2021-02-03 10:15:51 +0000) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * microbit: Add the UART to our nRF51 SoC model | 20 | * hw/intc/arm_gic: Allow to use QTest without crashing |
21 | * Add a virtual Xilinx Versal board "xlnx-versal-virt" | 21 | * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled |
22 | * hw/arm/virt: Set VIRT_COMPAT_3_0 compat | 22 | * hw/char/exynos4210_uart: Fix missing call to report ready for input |
23 | * hw/arm/smmuv3: Fix addr_mask for range-based invalidation | ||
24 | * hw/ssi/imx_spi: Fix various minor bugs | ||
25 | * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register | ||
26 | * hw/arm: Add missing Kconfig dependencies | ||
27 | * hw/arm: Display CPU type in machine description | ||
23 | 28 | ||
24 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
25 | Edgar E. Iglesias (2): | 30 | Bin Meng (5): |
26 | hw/arm: versal: Add a model of Xilinx Versal SoC | 31 | hw/ssi: imx_spi: Use a macro for number of chip selects supported |
27 | hw/arm: versal: Add a virtual Xilinx Versal board | 32 | hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() |
33 | hw/ssi: imx_spi: Round up the burst length to be multiple of 8 | ||
34 | hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic | ||
35 | hw/ssi: imx_spi: Correct tx and rx fifo endianness | ||
28 | 36 | ||
29 | Eric Auger (1): | 37 | Iris Johnson (2): |
30 | hw/arm/virt: Set VIRT_COMPAT_3_0 compat | 38 | hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled |
39 | hw/char/exynos4210_uart: Fix missing call to report ready for input | ||
31 | 40 | ||
32 | Julia Suvorova (3): | 41 | Philippe Mathieu-Daudé (12): |
33 | hw/char: Implement nRF51 SoC UART | 42 | hw/intc/arm_gic: Allow to use QTest without crashing |
34 | hw/arm/nrf51_soc: Connect UART to nRF51 SoC | 43 | hw/ssi: imx_spi: Remove pointless variable initialization |
35 | tests/boot-serial-test: Add microbit board testcase | 44 | hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value |
45 | hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled | ||
46 | hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled | ||
47 | hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register | ||
48 | hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ | ||
49 | hw/arm/exynos4210: Add missing dependency on OR_IRQ | ||
50 | hw/arm/xlnx-versal: Versal SoC requires ZDMA | ||
51 | hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals | ||
52 | hw/net/can: ZynqMP CAN device requires PTIMER | ||
53 | hw/arm: Display CPU type in machine description | ||
36 | 54 | ||
37 | hw/arm/Makefile.objs | 1 + | 55 | Xuzhou Cheng (1): |
38 | hw/char/Makefile.objs | 1 + | 56 | hw/ssi: imx_spi: Disable chip selects when controller is disabled |
39 | include/hw/arm/nrf51_soc.h | 3 + | ||
40 | include/hw/arm/xlnx-versal.h | 122 +++++++++ | ||
41 | include/hw/char/nrf51_uart.h | 78 ++++++ | ||
42 | hw/arm/microbit.c | 2 + | ||
43 | hw/arm/nrf51_soc.c | 20 ++ | ||
44 | hw/arm/virt.c | 4 + | ||
45 | hw/arm/xlnx-versal-virt.c | 493 ++++++++++++++++++++++++++++++++++++ | ||
46 | hw/arm/xlnx-versal.c | 323 +++++++++++++++++++++++ | ||
47 | hw/char/nrf51_uart.c | 330 ++++++++++++++++++++++++ | ||
48 | tests/boot-serial-test.c | 19 ++ | ||
49 | default-configs/aarch64-softmmu.mak | 1 + | ||
50 | hw/char/trace-events | 4 + | ||
51 | 14 files changed, 1401 insertions(+) | ||
52 | create mode 100644 include/hw/arm/xlnx-versal.h | ||
53 | create mode 100644 include/hw/char/nrf51_uart.h | ||
54 | create mode 100644 hw/arm/xlnx-versal-virt.c | ||
55 | create mode 100644 hw/arm/xlnx-versal.c | ||
56 | create mode 100644 hw/char/nrf51_uart.c | ||
57 | 57 | ||
58 | Zenghui Yu (1): | ||
59 | hw/arm/smmuv3: Fix addr_mask for range-based invalidation | ||
60 | |||
61 | include/hw/ssi/imx_spi.h | 5 +- | ||
62 | hw/arm/digic_boards.c | 2 +- | ||
63 | hw/arm/microbit.c | 2 +- | ||
64 | hw/arm/netduino2.c | 2 +- | ||
65 | hw/arm/netduinoplus2.c | 2 +- | ||
66 | hw/arm/orangepi.c | 2 +- | ||
67 | hw/arm/smmuv3.c | 4 +- | ||
68 | hw/arm/stellaris.c | 4 +- | ||
69 | hw/char/exynos4210_uart.c | 7 ++- | ||
70 | hw/intc/arm_gic.c | 5 +- | ||
71 | hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++++++----------------- | ||
72 | hw/Kconfig | 1 + | ||
73 | hw/arm/Kconfig | 5 ++ | ||
74 | hw/dma/Kconfig | 3 + | ||
75 | hw/dma/meson.build | 2 +- | ||
76 | 15 files changed, 130 insertions(+), 69 deletions(-) | ||
77 | diff view generated by jsdifflib |