Series comparison

-[Qemu-devel] [PULL 0/6] target-arm queue
+[PULL 00/38] target-arm queue
-Last lot of patches for arm before softfreeze tomorrow...
+The following changes since commit 3db29dcac23da85486704ef9e7a8e7217f7829cd:
-thanks
+  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-01-12 13:51:36 +0000)
 -- PMM
 The following changes since commit ef3a6af5e789ff078d1fef880f9dfb6adf18e8f1:
   Merge remote-tracking branch 'remotes/kraxel/tags/vga-20181029-pull-request' into staging (2018-10-29 12:59:15 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181029
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230113
-for you to fetch changes up to 20cf5663734310a282e27b7389bc9f53ffe227e6:
+for you to fetch changes up to 08899b5c68a55a3780d707e2464073c8f2670d31:
-  tests/boot-serial-test: Add microbit board testcase (2018-10-29 15:19:48 +0000)
+  target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled (2023-01-13 13:19:36 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * microbit: Add the UART to our nRF51 SoC model
+ hw/arm/stm32f405: correctly describe the memory layout
- * Add a virtual Xilinx Versal board "xlnx-versal-virt"
+ hw/arm: Add Olimex H405 board
- * hw/arm/virt: Set VIRT_COMPAT_3_0 compat
+ cubieboard: Support booting from an SD card image with u-boot on it
  target/arm: Fix sve_probe_page
  target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
  various code cleanups
 ----------------------------------------------------------------
-Edgar E. Iglesias (2):
+Evgeny Iakovlev (1):
-      hw/arm: versal: Add a model of Xilinx Versal SoC
+      target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
       hw/arm: versal: Add a virtual Xilinx Versal board
-Eric Auger (1):
+Felipe Balbi (2):
-      hw/arm/virt: Set VIRT_COMPAT_3_0 compat
+      hw/arm/stm32f405: correctly describe the memory layout
       hw/arm: Add Olimex H405
-Julia Suvorova (3):
+Philippe Mathieu-Daudé (27):
-      hw/char: Implement nRF51 SoC UART
+      hw/arm/pxa2xx: Simplify pxa255_init()
-      hw/arm/nrf51_soc: Connect UART to nRF51 SoC
+      hw/arm/pxa2xx: Simplify pxa270_init()
-      tests/boot-serial-test: Add microbit board testcase
+      hw/arm/collie: Use the IEC binary prefix definitions
       hw/arm/collie: Simplify flash creation using for() loop
       hw/arm/gumstix: Improve documentation
       hw/arm/gumstix: Use the IEC binary prefix definitions
       hw/arm/mainstone: Use the IEC binary prefix definitions
       hw/arm/musicpal: Use the IEC binary prefix definitions
       hw/arm/omap_sx1: Remove unused 'total_ram' definitions
       hw/arm/omap_sx1: Use the IEC binary prefix definitions
       hw/arm/z2: Use the IEC binary prefix definitions
       hw/arm/vexpress: Remove dead code in vexpress_common_init()
       hw/arm: Remove unreachable code calling pflash_cfi01_register()
       hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState
       hw/gpio/omap_gpio: Add local variable to avoid embedded cast
       hw/arm/omap: Drop useless casts from void * to pointer
       hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name
       hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name
       hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name
       hw/arm/stellaris: Drop useless casts from void * to pointer
       hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name
       hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE()
       hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
       hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC
       hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
       hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic'
       hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock'
- hw/arm/Makefile.objs                |   1 +
+Richard Henderson (1):
- hw/char/Makefile.objs               |   1 +
+      target/arm: Fix sve_probe_page
  include/hw/arm/nrf51_soc.h          |   3 +
  include/hw/arm/xlnx-versal.h        | 122 +++++++++
  include/hw/char/nrf51_uart.h        |  78 ++++++
  hw/arm/microbit.c                   |   2 +
  hw/arm/nrf51_soc.c                  |  20 ++
  hw/arm/virt.c                       |   4 +
  hw/arm/xlnx-versal-virt.c           | 493 ++++++++++++++++++++++++++++++++++++
  hw/arm/xlnx-versal.c                | 323 +++++++++++++++++++++++
  hw/char/nrf51_uart.c                | 330 ++++++++++++++++++++++++
  tests/boot-serial-test.c            |  19 ++
  default-configs/aarch64-softmmu.mak |   1 +
  hw/char/trace-events                |   4 +
 files changed, 1401 insertions(+)
  create mode 100644 include/hw/arm/xlnx-versal.h
  create mode 100644 include/hw/char/nrf51_uart.h
  create mode 100644 hw/arm/xlnx-versal-virt.c
  create mode 100644 hw/arm/xlnx-versal.c
  create mode 100644 hw/char/nrf51_uart.c
+Strahinja Jankovic (7):
+      hw/misc: Allwinner-A10 Clock Controller Module Emulation
+      hw/misc: Allwinner A10 DRAM Controller Emulation
+      {hw/i2c,docs/system/arm}: Allwinner TWI/I2C Emulation
+      hw/misc: AXP209 PMU Emulation
+      hw/arm: Add AXP209 to Cubieboard
+      hw/arm: Allwinner A10 enable SPL load from MMC
+      tests/avocado: Add SD boot test to Cubieboard
+ docs/system/arm/cubieboard.rst          |   1 +
+ docs/system/arm/orangepi.rst            |   1 +
+ docs/system/arm/stm32.rst               |   1 +
+ configs/devices/arm-softmmu/default.mak |   1 +
+ include/hw/adc/npcm7xx_adc.h            |   7 +-
+ include/hw/arm/allwinner-a10.h          |  27 ++
+ include/hw/arm/allwinner-h3.h           |   3 +
+ include/hw/arm/npcm7xx.h                |  18 +-
+ include/hw/arm/omap.h                   |  24 +-
+ include/hw/arm/pxa.h                    |  11 +-
+ include/hw/arm/stm32f405_soc.h          |   5 +-
+ include/hw/i2c/allwinner-i2c.h          |  55 ++++
+ include/hw/i2c/npcm7xx_smbus.h          |   7 +-
+ include/hw/misc/allwinner-a10-ccm.h     |  67 +++++
+ include/hw/misc/allwinner-a10-dramc.h   |  68 +++++
+ include/hw/misc/npcm7xx_clk.h           |   2 +-
+ include/hw/misc/npcm7xx_gcr.h           |   6 +-
+ include/hw/misc/npcm7xx_mft.h           |   7 +-
+ include/hw/misc/npcm7xx_pwm.h           |   3 +-
+ include/hw/misc/npcm7xx_rng.h           |   6 +-
+ include/hw/net/npcm7xx_emc.h            |   5 +-
+ include/hw/sd/npcm7xx_sdhci.h           |   4 +-
+ hw/arm/allwinner-a10.c                  |  40 +++
+ hw/arm/allwinner-h3.c                   |  11 +-
+ hw/arm/bcm2836.c                        |   9 +-
+ hw/arm/collie.c                         |  25 +-
+ hw/arm/cubieboard.c                     |  11 +
+ hw/arm/gumstix.c                        |  45 ++--
+ hw/arm/mainstone.c                      |  37 ++-
+ hw/arm/musicpal.c                       |   9 +-
+ hw/arm/olimex-stm32-h405.c              |  69 +++++
+ hw/arm/omap1.c                          | 115 ++++----
+ hw/arm/omap2.c                          |  40 ++-
+ hw/arm/omap_sx1.c                       |  53 ++--
+ hw/arm/palm.c                           |   2 +-
+ hw/arm/pxa2xx.c                         |   8 +-
+ hw/arm/spitz.c                          |   6 +-
+ hw/arm/stellaris.c                      |  73 +++--
+ hw/arm/stm32f405_soc.c                  |   8 +
+ hw/arm/tosa.c                           |   2 +-
+ hw/arm/versatilepb.c                    |   6 +-
+ hw/arm/vexpress.c                       |  10 +-
+ hw/arm/z2.c                             |  16 +-
+ hw/char/omap_uart.c                     |   7 +-
+ hw/display/omap_dss.c                   |  15 +-
+ hw/display/omap_lcdc.c                  |   9 +-
+ hw/dma/omap_dma.c                       |  15 +-
+ hw/gpio/omap_gpio.c                     |  48 ++--
+ hw/i2c/allwinner-i2c.c                  | 459 ++++++++++++++++++++++++++++++++
+ hw/intc/omap_intc.c                     |  38 +--
+ hw/intc/xilinx_intc.c                   |  28 +-
+ hw/misc/allwinner-a10-ccm.c             | 224 ++++++++++++++++
+ hw/misc/allwinner-a10-dramc.c           | 179 +++++++++++++
+ hw/misc/axp209.c                        | 238 +++++++++++++++++
+ hw/misc/omap_gpmc.c                     |  12 +-
+ hw/misc/omap_l4.c                       |   7 +-
+ hw/misc/omap_sdrc.c                     |   7 +-
+ hw/misc/omap_tap.c                      |   5 +-
+ hw/misc/sbsa_ec.c                       |  12 +-
+ hw/sd/omap_mmc.c                        |   9 +-
+ hw/ssi/omap_spi.c                       |   7 +-
+ hw/timer/omap_gptimer.c                 |  22 +-
+ hw/timer/omap_synctimer.c               |   4 +-
+ hw/timer/xilinx_timer.c                 |  27 +-
+ target/arm/helper.c                     |   3 +
+ target/arm/sve_helper.c                 |  14 +-
+ MAINTAINERS                             |   8 +
+ hw/arm/Kconfig                          |   9 +
+ hw/arm/meson.build                      |   1 +
+ hw/i2c/Kconfig                          |   4 +
+ hw/i2c/meson.build                      |   1 +
+ hw/i2c/trace-events                     |   5 +
+ hw/misc/Kconfig                         |  10 +
+ hw/misc/meson.build                     |   3 +
+ hw/misc/trace-events                    |   5 +
+ tests/avocado/boot_linux_console.py     |  47 ++++
+files changed, 1951 insertions(+), 455 deletions(-)
+ create mode 100644 include/hw/i2c/allwinner-i2c.h
+ create mode 100644 include/hw/misc/allwinner-a10-ccm.h
+ create mode 100644 include/hw/misc/allwinner-a10-dramc.h
+ create mode 100644 hw/arm/olimex-stm32-h405.c
+ create mode 100644 hw/i2c/allwinner-i2c.c
+ create mode 100644 hw/misc/allwinner-a10-ccm.c
+ create mode 100644 hw/misc/allwinner-a10-dramc.c
+ create mode 100644 hw/misc/axp209.c

-[Qemu-devel] [PULL 5/6] hw/arm/nrf51_soc: Connect UART to nRF51 SoC
+[PULL 01/38] hw/arm/stm32f405: correctly describe the memory layout
-From: Julia Suvorova via Qemu-devel <qemu-devel@nongnu.org>
+From: Felipe Balbi <balbi@kernel.org>
-Wire up nRF51 UART in the corresponding SoC.
+STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled
 Memory) at a different base address. Correctly describe the memory
 layout to give existing FW images a chance to run unmodified.
-Signed-off-by: Julia Suvorova <jusual@mail.ru>
+Reviewed-by: Alistair Francis <alistair@alistair23.me>
-Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Felipe Balbi <balbi@kernel.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20221230145733.200496-2-balbi@kernel.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/nrf51_soc.h |  3 +++
+ include/hw/arm/stm32f405_soc.h | 5 ++++-
- hw/arm/microbit.c          |  2 ++
+ hw/arm/stm32f405_soc.c         | 8 ++++++++
- hw/arm/nrf51_soc.c         | 20 ++++++++++++++++++++
+files changed, 12 insertions(+), 1 deletion(-)
 files changed, 25 insertions(+)
-diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
+diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/nrf51_soc.h
+--- a/include/hw/arm/stm32f405_soc.h
-+++ b/include/hw/arm/nrf51_soc.h
++++ b/include/hw/arm/stm32f405_soc.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
+ #define FLASH_BASE_ADDRESS 0x08000000
- #include "hw/sysbus.h"
+ #define FLASH_SIZE (1024 * 1024)
- #include "hw/arm/armv7m.h"
+ #define SRAM_BASE_ADDRESS 0x20000000
-+#include "hw/char/nrf51_uart.h"
+-#define SRAM_SIZE (192 * 1024)
++#define SRAM_SIZE (128 * 1024)
- #define TYPE_NRF51_SOC "nrf51-soc"
++#define CCM_BASE_ADDRESS 0x10000000
- #define NRF51_SOC(obj) \
++#define CCM_SIZE (64 * 1024)
-@@ -XXX,XX +XXX,XX @@ typedef struct NRF51State {
-     /*< public >*/
+ struct STM32F405State {
-     ARMv7MState cpu;
+     /*< private >*/
+@@ -XXX,XX +XXX,XX @@ struct STM32F405State {
-+    NRF51UARTState uart;
+     STM32F2XXADCState adc[STM_NUM_ADCS];
-+
+     STM32F2XXSPIState spi[STM_NUM_SPIS];
-     MemoryRegion iomem;
 +    MemoryRegion ccm;
      MemoryRegion sram;
      MemoryRegion flash;
-diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
+     MemoryRegion flash_alias;
 diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/microbit.c
+--- a/hw/arm/stm32f405_soc.c
-+++ b/hw/arm/microbit.c
++++ b/hw/arm/stm32f405_soc.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
  #include "qapi/error.h"
  #include "hw/boards.h"
  #include "hw/arm/arm.h"
 +#include "sysemu/sysemu.h"
  #include "exec/address-spaces.h"
  #include "hw/arm/nrf51_soc.h"
@@ -XXX,XX +XXX,XX @@ static void microbit_init(MachineState *machine)
      sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51),
                            TYPE_NRF51_SOC);
 +    qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0));
      object_property_set_link(soc, OBJECT(system_memory), "memory",
                               &error_fatal);
      object_property_set_bool(soc, true, "realized", &error_fatal);
 diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/nrf51_soc.c
 +++ b/hw/arm/nrf51_soc.c
@@ -XXX,XX +XXX,XX @@
  #define NRF51822_FLASH_SIZE     (256 * 1024)
  #define NRF51822_SRAM_SIZE      (16 * 1024)
 +#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
 +
  static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
  {
      NRF51State *s = NRF51_SOC(dev_soc);
 +    MemoryRegion *mr;
      Error *err = NULL;
      if (!s->board_memory) {
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
      }
-     memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
+     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
-+    /* UART */
++    memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE,
-+    object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
++                           &err);
-+    if (err) {
++    if (err != NULL) {
 +        error_propagate(errp, err);
 +        return;
 +    }
-+    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
++    memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm);
 +    memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
 +                       qdev_get_gpio_in(DEVICE(&s->cpu),
 +                       BASE_TO_IRQ(UART_BASE)));
 +
-     create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
+     armv7m = DEVICE(&s->armv7m);
-     create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
+     qdev_prop_set_uint32(armv7m, "num-irq", 96);
-     create_unimplemented_device("nrf51_soc.private",
+     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_init(Object *obj)
      qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
                           ARM_CPU_TYPE_NAME("cortex-m0"));
      qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
 +
 +    sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
 +                           TYPE_NRF51_UART);
 +    object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",
 +                              &error_abort);
  }
  static Property nrf51_soc_properties[] = {
 --
-.19.1
+.34.1

-New patch
+[PULL 02/38] hw/arm: Add Olimex H405
+From: Felipe Balbi <balbi@kernel.org>
+Olimex makes a series of low-cost STM32 boards. This commit introduces
+the minimum setup to support SMT32-H405. See [1] for details
+[1] https://www.olimex.com/Products/ARM/ST/STM32-H405/
+Signed-off-by: Felipe Balbi <balbi@kernel.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20221230145733.200496-3-balbi@kernel.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ docs/system/arm/stm32.rst               |  1 +
+ configs/devices/arm-softmmu/default.mak |  1 +
+ hw/arm/olimex-stm32-h405.c              | 69 +++++++++++++++++++++++++
+ MAINTAINERS                             |  6 +++
+ hw/arm/Kconfig                          |  4 ++
+ hw/arm/meson.build                      |  1 +
+files changed, 82 insertions(+)
+ create mode 100644 hw/arm/olimex-stm32-h405.c
+diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/stm32.rst
++++ b/docs/system/arm/stm32.rst
+@@ -XXX,XX +XXX,XX @@ The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
+ compatible with STM32F2 series. The following machines are based on this chip :
+ - ``netduinoplus2``     Netduino Plus 2 board with STM32F405RGT6 microcontroller
++- ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microcontroller
+ There are many other STM32 series that are currently not supported by QEMU.
+diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
+index XXXXXXX..XXXXXXX 100644
+--- a/configs/devices/arm-softmmu/default.mak
++++ b/configs/devices/arm-softmmu/default.mak
+@@ -XXX,XX +XXX,XX @@ CONFIG_COLLIE=y
+ CONFIG_ASPEED_SOC=y
+ CONFIG_NETDUINO2=y
+ CONFIG_NETDUINOPLUS2=y
++CONFIG_OLIMEX_STM32_H405=y
+ CONFIG_MPS2=y
+ CONFIG_RASPI=y
+ CONFIG_DIGIC=y
+diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/arm/olimex-stm32-h405.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * ST STM32VLDISCOVERY machine
++ * Olimex STM32-H405 machine
++ *
++ * Copyright (c) 2022 Felipe Balbi <balbi@kernel.org>
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
++ * of this software and associated documentation files (the "Software"), to deal
++ * in the Software without restriction, including without limitation the rights
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
++ * copies of the Software, and to permit persons to whom the Software is
++ * furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
++ * THE SOFTWARE.
++ */
++
++#include "qemu/osdep.h"
++#include "qapi/error.h"
++#include "hw/boards.h"
++#include "hw/qdev-properties.h"
++#include "hw/qdev-clock.h"
++#include "qemu/error-report.h"
++#include "hw/arm/stm32f405_soc.h"
++#include "hw/arm/boot.h"
++
++/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
++
++/* Main SYSCLK frequency in Hz (168MHz) */
++#define SYSCLK_FRQ 168000000ULL
++
++static void olimex_stm32_h405_init(MachineState *machine)
++{
++    DeviceState *dev;
++    Clock *sysclk;
++
++    /* This clock doesn't need migration because it is fixed-frequency */
++    sysclk = clock_new(OBJECT(machine), "SYSCLK");
++    clock_set_hz(sysclk, SYSCLK_FRQ);
++
++    dev = qdev_new(TYPE_STM32F405_SOC);
++    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
++    qdev_connect_clock_in(dev, "sysclk", sysclk);
++    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
++
++    armv7m_load_kernel(ARM_CPU(first_cpu),
++                       machine->kernel_filename,
++                       0, FLASH_SIZE);
++}
++
++static void olimex_stm32_h405_machine_init(MachineClass *mc)
++{
++    mc->desc = "Olimex STM32-H405 (Cortex-M4)";
++    mc->init = olimex_stm32_h405_init;
++    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
++
++    /* SRAM pre-allocated as part of the SoC instantiation */
++    mc->default_ram_size = 0;
++}
++
++DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
+ S: Maintained
+ F: hw/arm/netduinoplus2.c
++Olimex STM32 H405
++M: Felipe Balbi <balbi@kernel.org>
++L: qemu-arm@nongnu.org
++S: Maintained
++F: hw/arm/olimex-stm32-h405.c
++
+ SmartFusion2
+ M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ M: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/Kconfig
++++ b/hw/arm/Kconfig
+@@ -XXX,XX +XXX,XX @@ config NETDUINOPLUS2
+     bool
+     select STM32F405_SOC
++config OLIMEX_STM32_H405
++    bool
++    select STM32F405_SOC
++
+ config NSERIES
+     bool
+     select OMAP
+diff --git a/hw/arm/meson.build b/hw/arm/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/meson.build
++++ b/hw/arm/meson.build
+@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
+ arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
+ arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
+ arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
++arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
+ arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
+ arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
+ arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
+--
+.34.1

-[Qemu-devel] [PULL 4/6] hw/char: Implement nRF51 SoC UART
+[PULL 03/38] hw/misc: Allwinner-A10 Clock Controller Module Emulation
-From: Julia Suvorova via Qemu-devel <qemu-devel@nongnu.org>
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
-Not implemented: CTS/NCTS, PSEL*.
+During SPL boot several Clock Controller Module (CCM) registers are
 read, most important are PLL and Tuning, as well as divisor registers.
-Signed-off-by: Julia Suvorova <jusual@mail.ru>
+This patch adds these registers and initializes reset values from user's
-Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
+guide.
 Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
 Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
 Message-id: 20221226220303.14420-2-strahinja.p.jankovic@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/char/Makefile.objs        |   1 +
+ include/hw/arm/allwinner-a10.h      |   2 +
- include/hw/char/nrf51_uart.h |  78 +++++++++
+ include/hw/misc/allwinner-a10-ccm.h |  67 +++++++++
- hw/char/nrf51_uart.c         | 330 +++++++++++++++++++++++++++++++++++
+ hw/arm/allwinner-a10.c              |   7 +
- hw/char/trace-events         |   4 +
+ hw/misc/allwinner-a10-ccm.c         | 224 ++++++++++++++++++++++++++++
-files changed, 413 insertions(+)
+ hw/arm/Kconfig                      |   1 +
- create mode 100644 include/hw/char/nrf51_uart.h
+ hw/misc/Kconfig                     |   3 +
- create mode 100644 hw/char/nrf51_uart.c
+ hw/misc/meson.build                 |   1 +
 files changed, 305 insertions(+)
  create mode 100644 include/hw/misc/allwinner-a10-ccm.h
  create mode 100644 hw/misc/allwinner-a10-ccm.c
-diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
+diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/Makefile.objs
+--- a/include/hw/arm/allwinner-a10.h
-+++ b/hw/char/Makefile.objs
++++ b/include/hw/arm/allwinner-a10.h
 @@ -XXX,XX +XXX,XX @@
- common-obj-$(CONFIG_IPACK) += ipoctal232.o
+ #include "hw/usb/hcd-ohci.h"
- common-obj-$(CONFIG_ESCC) += escc.o
+ #include "hw/usb/hcd-ehci.h"
-+common-obj-$(CONFIG_NRF51_SOC) += nrf51_uart.o
+ #include "hw/rtc/allwinner-rtc.h"
- common-obj-$(CONFIG_PARALLEL) += parallel.o
++#include "hw/misc/allwinner-a10-ccm.h"
- common-obj-$(CONFIG_PARALLEL) += parallel-isa.o
- common-obj-$(CONFIG_PL011) += pl011.o
+ #include "target/arm/cpu.h"
-diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h
+ #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
      /*< public >*/
      ARMCPU cpu;
 +    AwA10ClockCtlState ccm;
      AwA10PITState timer;
      AwA10PICState intc;
      AwEmacState emac;
 diff --git a/include/hw/misc/allwinner-a10-ccm.h b/include/hw/misc/allwinner-a10-ccm.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/char/nrf51_uart.h
++++ b/include/hw/misc/allwinner-a10-ccm.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * nRF51 SoC UART emulation
++ * Allwinner A10 Clock Control Module emulation
 + *
-+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
++ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
 + *
-+ * This program is free software; you can redistribute it and/or modify
++ *  This file is derived from Allwinner H3 CCU,
-+ * it under the terms of the GNU General Public License version 2 or
++ *  by Niek Linnenbank.
 + *
 + * This program is free software: you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation, either version 2 of the License, or
 + * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#ifndef NRF51_UART_H
++#ifndef HW_MISC_ALLWINNER_A10_CCM_H
-+#define NRF51_UART_H
++#define HW_MISC_ALLWINNER_A10_CCM_H
 +
 +#include "qom/object.h"
 +#include "hw/sysbus.h"
-+#include "chardev/char-fe.h"
++
-+#include "hw/registerfields.h"
++/**
-+
++ * @name Constants
-+#define UART_FIFO_LENGTH 6
++ * @{
-+#define UART_BASE 0x40002000
++ */
-+#define UART_SIZE 0x1000
++
-+
++/** Size of register I/O address space used by CCM device */
-+#define TYPE_NRF51_UART "nrf51_soc.uart"
++#define AW_A10_CCM_IOSIZE        (0x400)
-+#define NRF51_UART(obj) OBJECT_CHECK(NRF51UARTState, (obj), TYPE_NRF51_UART)
++
-+
++/** Total number of known registers */
-+REG32(UART_STARTRX, 0x000)
++#define AW_A10_CCM_REGS_NUM      (AW_A10_CCM_IOSIZE / sizeof(uint32_t))
-+REG32(UART_STOPRX, 0x004)
++
-+REG32(UART_STARTTX, 0x008)
++/** @} */
-+REG32(UART_STOPTX, 0x00C)
++
-+REG32(UART_SUSPEND, 0x01C)
++/**
-+
++ * @name Object model
-+REG32(UART_CTS, 0x100)
++ * @{
-+REG32(UART_NCTS, 0x104)
++ */
-+REG32(UART_RXDRDY, 0x108)
++
-+REG32(UART_TXDRDY, 0x11C)
++#define TYPE_AW_A10_CCM    "allwinner-a10-ccm"
-+REG32(UART_ERROR, 0x124)
++OBJECT_DECLARE_SIMPLE_TYPE(AwA10ClockCtlState, AW_A10_CCM)
-+REG32(UART_RXTO, 0x144)
++
-+
++/** @} */
-+REG32(UART_INTEN, 0x300)
++
-+    FIELD(UART_INTEN, CTS, 0, 1)
++/**
-+    FIELD(UART_INTEN, NCTS, 1, 1)
++ * Allwinner A10 CCM object instance state.
-+    FIELD(UART_INTEN, RXDRDY, 2, 1)
++ */
-+    FIELD(UART_INTEN, TXDRDY, 7, 1)
++struct AwA10ClockCtlState {
-+    FIELD(UART_INTEN, ERROR, 9, 1)
++    /*< private >*/
 +    FIELD(UART_INTEN, RXTO, 17, 1)
 +REG32(UART_INTENSET, 0x304)
 +REG32(UART_INTENCLR, 0x308)
 +REG32(UART_ERRORSRC, 0x480)
 +REG32(UART_ENABLE, 0x500)
 +REG32(UART_PSELRTS, 0x508)
 +REG32(UART_PSELTXD, 0x50C)
 +REG32(UART_PSELCTS, 0x510)
 +REG32(UART_PSELRXD, 0x514)
 +REG32(UART_RXD, 0x518)
 +REG32(UART_TXD, 0x51C)
 +REG32(UART_BAUDRATE, 0x524)
 +REG32(UART_CONFIG, 0x56C)
 +
 +typedef struct NRF51UARTState {
 +    SysBusDevice parent_obj;
-+
++    /*< public >*/
 +
 +    /** Maps I/O registers in physical memory */
 +    MemoryRegion iomem;
-+    CharBackend chr;
++
-+    qemu_irq irq;
++    /** Array of hardware registers */
-+    guint watch_tag;
++    uint32_t regs[AW_A10_CCM_REGS_NUM];
-+
++};
-+    uint8_t rx_fifo[UART_FIFO_LENGTH];
++
-+    unsigned int rx_fifo_pos;
++#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
-+    unsigned int rx_fifo_len;
+diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
-+
+index XXXXXXX..XXXXXXX 100644
-+    uint32_t reg[0x56C];
+--- a/hw/arm/allwinner-a10.c
-+
++++ b/hw/arm/allwinner-a10.c
-+    bool rx_started;
+@@ -XXX,XX +XXX,XX @@
-+    bool tx_started;
+ #include "hw/usb/hcd-ohci.h"
-+    bool pending_tx_byte;
-+    bool enabled;
+ #define AW_A10_MMC0_BASE        0x01c0f000
-+} NRF51UARTState;
++#define AW_A10_CCM_BASE         0x01c20000
-+
+ #define AW_A10_PIC_REG_BASE     0x01c20400
-+#endif
+ #define AW_A10_PIT_REG_BASE     0x01c20c00
-diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c
+ #define AW_A10_UART0_REG_BASE   0x01c28000
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
      object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
 +    object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
 +
      object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
      object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
      memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
      create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
 +    /* Clock Control Module */
 +    sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
 +
      /* FIXME use qdev NIC properties instead of nd_table[] */
      if (nd_table[0].used) {
          qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
 diff --git a/hw/misc/allwinner-a10-ccm.c b/hw/misc/allwinner-a10-ccm.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/char/nrf51_uart.c
++++ b/hw/misc/allwinner-a10-ccm.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * nRF51 SoC UART emulation
++ * Allwinner A10 Clock Control Module emulation
 + *
-+ * See nRF51 Series Reference Manual, "29 Universal Asynchronous
++ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
-+ * Receiver/Transmitter" for hardware specifications:
++ *
-+ * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
++ *  This file is derived from Allwinner H3 CCU,
-+ *
++ *  by Niek Linnenbank.
-+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
++ *
-+ *
++ * This program is free software: you can redistribute it and/or modify
-+ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
-+ * it under the terms of the GNU General Public License version 2 or
++ * the Free Software Foundation, either version 2 of the License, or
 + * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
++#include "qemu/units.h"
++#include "hw/sysbus.h"
++#include "migration/vmstate.h"
 +#include "qemu/log.h"
-+#include "hw/char/nrf51_uart.h"
++#include "qemu/module.h"
-+#include "trace.h"
++#include "hw/misc/allwinner-a10-ccm.h"
 +
-+static void nrf51_uart_update_irq(NRF51UARTState *s)
++/* CCM register offsets */
-+{
++enum {
-+    bool irq = false;
++    REG_PLL1_CFG             = 0x0000, /* PLL1 Control */
-+
++    REG_PLL1_TUN             = 0x0004, /* PLL1 Tuning */
-+    irq |= (s->reg[R_UART_RXDRDY] &&
++    REG_PLL2_CFG             = 0x0008, /* PLL2 Control */
-+            (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK));
++    REG_PLL2_TUN             = 0x000C, /* PLL2 Tuning */
-+    irq |= (s->reg[R_UART_TXDRDY] &&
++    REG_PLL3_CFG             = 0x0010, /* PLL3 Control */
-+            (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK));
++    REG_PLL4_CFG             = 0x0018, /* PLL4 Control */
-+    irq |= (s->reg[R_UART_ERROR]  &&
++    REG_PLL5_CFG             = 0x0020, /* PLL5 Control */
-+            (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK));
++    REG_PLL5_TUN             = 0x0024, /* PLL5 Tuning */
-+    irq |= (s->reg[R_UART_RXTO]   &&
++    REG_PLL6_CFG             = 0x0028, /* PLL6 Control */
-+            (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK));
++    REG_PLL6_TUN             = 0x002C, /* PLL6 Tuning */
-+
++    REG_PLL7_CFG             = 0x0030, /* PLL7 Control */
-+    qemu_set_irq(s->irq, irq);
++    REG_PLL1_TUN2            = 0x0038, /* PLL1 Tuning2 */
-+}
++    REG_PLL5_TUN2            = 0x003C, /* PLL5 Tuning2 */
-+
++    REG_PLL8_CFG             = 0x0040, /* PLL8 Control */
-+static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size)
++    REG_OSC24M_CFG           = 0x0050, /* OSC24M Control */
-+{
++    REG_CPU_AHB_APB0_CFG     = 0x0054, /* CPU, AHB and APB0 Divide Ratio */
-+    NRF51UARTState *s = NRF51_UART(opaque);
++};
-+    uint64_t r;
++
-+
++#define REG_INDEX(offset)    (offset / sizeof(uint32_t))
-+    if (!s->enabled) {
++
 +/* CCM register reset values */
 +enum {
 +    REG_PLL1_CFG_RST         = 0x21005000,
 +    REG_PLL1_TUN_RST         = 0x0A101000,
 +    REG_PLL2_CFG_RST         = 0x08100010,
 +    REG_PLL2_TUN_RST         = 0x00000000,
 +    REG_PLL3_CFG_RST         = 0x0010D063,
 +    REG_PLL4_CFG_RST         = 0x21009911,
 +    REG_PLL5_CFG_RST         = 0x11049280,
 +    REG_PLL5_TUN_RST         = 0x14888000,
 +    REG_PLL6_CFG_RST         = 0x21009911,
 +    REG_PLL6_TUN_RST         = 0x00000000,
 +    REG_PLL7_CFG_RST         = 0x0010D063,
 +    REG_PLL1_TUN2_RST        = 0x00000000,
 +    REG_PLL5_TUN2_RST        = 0x00000000,
 +    REG_PLL8_CFG_RST         = 0x21009911,
 +    REG_OSC24M_CFG_RST       = 0x00138013,
 +    REG_CPU_AHB_APB0_CFG_RST = 0x00010010,
 +};
 +
 +static uint64_t allwinner_a10_ccm_read(void *opaque, hwaddr offset,
 +                                       unsigned size)
 +{
 +    const AwA10ClockCtlState *s = AW_A10_CCM(opaque);
 +    const uint32_t idx = REG_INDEX(offset);
 +
 +    switch (offset) {
 +    case REG_PLL1_CFG:
 +    case REG_PLL1_TUN:
 +    case REG_PLL2_CFG:
 +    case REG_PLL2_TUN:
 +    case REG_PLL3_CFG:
 +    case REG_PLL4_CFG:
 +    case REG_PLL5_CFG:
 +    case REG_PLL5_TUN:
 +    case REG_PLL6_CFG:
 +    case REG_PLL6_TUN:
 +    case REG_PLL7_CFG:
 +    case REG_PLL1_TUN2:
 +    case REG_PLL5_TUN2:
 +    case REG_PLL8_CFG:
 +    case REG_OSC24M_CFG:
 +    case REG_CPU_AHB_APB0_CFG:
 +        break;
 +    case 0x158 ... AW_A10_CCM_IOSIZE:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
 +                      __func__, (uint32_t)offset);
 +        return 0;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
 +                      __func__, (uint32_t)offset);
 +        return 0;
 +    }
 +
-+    switch (addr) {
++    return s->regs[idx];
-+    case A_UART_RXD:
++}
-+        r = s->rx_fifo[s->rx_fifo_pos];
++
-+        if (s->rx_started && s->rx_fifo_len) {
++static void allwinner_a10_ccm_write(void *opaque, hwaddr offset,
-+            s->rx_fifo_pos = (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH;
++                                   uint64_t val, unsigned size)
-+            s->rx_fifo_len--;
++{
-+            if (s->rx_fifo_len) {
++    AwA10ClockCtlState *s = AW_A10_CCM(opaque);
-+                s->reg[R_UART_RXDRDY] = 1;
++    const uint32_t idx = REG_INDEX(offset);
-+                nrf51_uart_update_irq(s);
++
-+            }
++    switch (offset) {
-+            qemu_chr_fe_accept_input(&s->chr);
++    case REG_PLL1_CFG:
-+        }
++    case REG_PLL1_TUN:
 +    case REG_PLL2_CFG:
 +    case REG_PLL2_TUN:
 +    case REG_PLL3_CFG:
 +    case REG_PLL4_CFG:
 +    case REG_PLL5_CFG:
 +    case REG_PLL5_TUN:
 +    case REG_PLL6_CFG:
 +    case REG_PLL6_TUN:
 +    case REG_PLL7_CFG:
 +    case REG_PLL1_TUN2:
 +    case REG_PLL5_TUN2:
 +    case REG_PLL8_CFG:
 +    case REG_OSC24M_CFG:
 +    case REG_CPU_AHB_APB0_CFG:
 +        break;
-+    case A_UART_INTENSET:
++    case 0x158 ... AW_A10_CCM_IOSIZE:
-+    case A_UART_INTENCLR:
++        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
-+    case A_UART_INTEN:
++                      __func__, (uint32_t)offset);
 +        r = s->reg[R_UART_INTEN];
 +        break;
 +    default:
-+        r = s->reg[addr / 4];
++        qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
 +                      __func__, (uint32_t)offset);
 +        break;
 +    }
 +
-+    trace_nrf51_uart_read(addr, r, size);
++    s->regs[idx] = (uint32_t) val;
-+
++}
-+    return r;
++
-+}
++static const MemoryRegionOps allwinner_a10_ccm_ops = {
-+
++    .read = allwinner_a10_ccm_read,
-+static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque)
++    .write = allwinner_a10_ccm_write,
-+{
++    .endianness = DEVICE_NATIVE_ENDIAN,
-+    NRF51UARTState *s = NRF51_UART(opaque);
++    .valid = {
-+    int r;
++        .min_access_size = 4,
-+    uint8_t c = s->reg[R_UART_TXD];
++        .max_access_size = 4,
-+
++    },
-+    s->watch_tag = 0;
++    .impl.min_access_size = 4,
-+
++};
-+    r = qemu_chr_fe_write(&s->chr, &c, 1);
++
-+    if (r <= 0) {
++static void allwinner_a10_ccm_reset_enter(Object *obj, ResetType type)
-+        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
++{
-+                                             uart_transmit, s);
++    AwA10ClockCtlState *s = AW_A10_CCM(obj);
-+        if (!s->watch_tag) {
++
-+            /* The hardware has no transmit error reporting,
++    /* Set default values for registers */
-+             * so silently drop the byte
++    s->regs[REG_INDEX(REG_PLL1_CFG)] = REG_PLL1_CFG_RST;
-+             */
++    s->regs[REG_INDEX(REG_PLL1_TUN)] = REG_PLL1_TUN_RST;
-+            goto buffer_drained;
++    s->regs[REG_INDEX(REG_PLL2_CFG)] = REG_PLL2_CFG_RST;
-+        }
++    s->regs[REG_INDEX(REG_PLL2_TUN)] = REG_PLL2_TUN_RST;
-+        return FALSE;
++    s->regs[REG_INDEX(REG_PLL3_CFG)] = REG_PLL3_CFG_RST;
-+    }
++    s->regs[REG_INDEX(REG_PLL4_CFG)] = REG_PLL4_CFG_RST;
-+
++    s->regs[REG_INDEX(REG_PLL5_CFG)] = REG_PLL5_CFG_RST;
-+buffer_drained:
++    s->regs[REG_INDEX(REG_PLL5_TUN)] = REG_PLL5_TUN_RST;
-+    s->reg[R_UART_TXDRDY] = 1;
++    s->regs[REG_INDEX(REG_PLL6_CFG)] = REG_PLL6_CFG_RST;
-+    s->pending_tx_byte = false;
++    s->regs[REG_INDEX(REG_PLL6_TUN)] = REG_PLL6_TUN_RST;
-+    return FALSE;
++    s->regs[REG_INDEX(REG_PLL7_CFG)] = REG_PLL7_CFG_RST;
-+}
++    s->regs[REG_INDEX(REG_PLL1_TUN2)] = REG_PLL1_TUN2_RST;
-+
++    s->regs[REG_INDEX(REG_PLL5_TUN2)] = REG_PLL5_TUN2_RST;
-+static void uart_cancel_transmit(NRF51UARTState *s)
++    s->regs[REG_INDEX(REG_PLL8_CFG)] = REG_PLL8_CFG_RST;
-+{
++    s->regs[REG_INDEX(REG_OSC24M_CFG)] = REG_OSC24M_CFG_RST;
-+    if (s->watch_tag) {
++    s->regs[REG_INDEX(REG_CPU_AHB_APB0_CFG)] = REG_CPU_AHB_APB0_CFG_RST;
-+        g_source_remove(s->watch_tag);
++}
-+        s->watch_tag = 0;
++
-+    }
++static void allwinner_a10_ccm_init(Object *obj)
-+}
++{
 +
 +static void uart_write(void *opaque, hwaddr addr,
 +                       uint64_t value, unsigned int size)
 +{
 +    NRF51UARTState *s = NRF51_UART(opaque);
 +
 +    trace_nrf51_uart_write(addr, value, size);
 +
 +    if (!s->enabled && (addr != A_UART_ENABLE)) {
 +        return;
 +    }
 +
 +    switch (addr) {
 +    case A_UART_TXD:
 +        if (!s->pending_tx_byte && s->tx_started) {
 +            s->reg[R_UART_TXD] = value;
 +            s->pending_tx_byte = true;
 +            uart_transmit(NULL, G_IO_OUT, s);
 +        }
 +        break;
 +    case A_UART_INTEN:
 +        s->reg[R_UART_INTEN] = value;
 +        break;
 +    case A_UART_INTENSET:
 +        s->reg[R_UART_INTEN] |= value;
 +        break;
 +    case A_UART_INTENCLR:
 +        s->reg[R_UART_INTEN] &= ~value;
 +        break;
 +    case A_UART_TXDRDY ... A_UART_RXTO:
 +        s->reg[addr / 4] = value;
 +        break;
 +    case A_UART_ERRORSRC:
 +        s->reg[addr / 4] &= ~value;
 +        break;
 +    case A_UART_RXD:
 +        break;
 +    case A_UART_RXDRDY:
 +        if (value == 0) {
 +            s->reg[R_UART_RXDRDY] = 0;
 +        }
 +        break;
 +    case A_UART_STARTTX:
 +        if (value == 1) {
 +            s->tx_started = true;
 +        }
 +        break;
 +    case A_UART_STARTRX:
 +        if (value == 1) {
 +            s->rx_started = true;
 +        }
 +        break;
 +    case A_UART_ENABLE:
 +        if (value) {
 +            if (value == 4) {
 +                s->enabled = true;
 +            }
 +            break;
 +        }
 +        s->enabled = false;
 +        value = 1;
 +        /* fall through */
 +    case A_UART_SUSPEND:
 +    case A_UART_STOPTX:
 +        if (value == 1) {
 +            s->tx_started = false;
 +        }
 +        /* fall through */
 +    case A_UART_STOPRX:
 +        if (addr != A_UART_STOPTX && value == 1) {
 +            s->rx_started = false;
 +            s->reg[R_UART_RXTO] = 1;
 +        }
 +        break;
 +    default:
 +        s->reg[addr / 4] = value;
 +        break;
 +    }
 +    nrf51_uart_update_irq(s);
 +}
 +
 +static const MemoryRegionOps uart_ops = {
 +    .read =  uart_read,
 +    .write = uart_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +};
 +
 +static void nrf51_uart_reset(DeviceState *dev)
 +{
 +    NRF51UARTState *s = NRF51_UART(dev);
 +
 +    s->pending_tx_byte = 0;
 +
 +    uart_cancel_transmit(s);
 +
 +    memset(s->reg, 0, sizeof(s->reg));
 +
 +    s->reg[R_UART_PSELRTS] = 0xFFFFFFFF;
 +    s->reg[R_UART_PSELTXD] = 0xFFFFFFFF;
 +    s->reg[R_UART_PSELCTS] = 0xFFFFFFFF;
 +    s->reg[R_UART_PSELRXD] = 0xFFFFFFFF;
 +    s->reg[R_UART_BAUDRATE] = 0x4000000;
 +
 +    s->rx_fifo_len = 0;
 +    s->rx_fifo_pos = 0;
 +    s->rx_started = false;
 +    s->tx_started = false;
 +    s->enabled = false;
 +}
 +
 +static void uart_receive(void *opaque, const uint8_t *buf, int size)
 +{
 +
 +    NRF51UARTState *s = NRF51_UART(opaque);
 +    int i;
 +
 +    if (size == 0 || s->rx_fifo_len >= UART_FIFO_LENGTH) {
 +        return;
 +    }
 +
 +    for (i = 0; i < size; i++) {
 +        uint32_t pos = (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LENGTH;
 +        s->rx_fifo[pos] = buf[i];
 +        s->rx_fifo_len++;
 +    }
 +
 +    s->reg[R_UART_RXDRDY] = 1;
 +    nrf51_uart_update_irq(s);
 +}
 +
 +static int uart_can_receive(void *opaque)
 +{
 +    NRF51UARTState *s = NRF51_UART(opaque);
 +
 +    return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0;
 +}
 +
 +static void uart_event(void *opaque, int event)
 +{
 +    NRF51UARTState *s = NRF51_UART(opaque);
 +
 +    if (event == CHR_EVENT_BREAK) {
 +        s->reg[R_UART_ERRORSRC] |= 3;
 +        s->reg[R_UART_ERROR] = 1;
 +        nrf51_uart_update_irq(s);
 +    }
 +}
 +
 +static void nrf51_uart_realize(DeviceState *dev, Error **errp)
 +{
 +    NRF51UARTState *s = NRF51_UART(dev);
 +
 +    qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
 +                             uart_event, NULL, s, NULL, true);
 +}
 +
 +static void nrf51_uart_init(Object *obj)
 +{
 +    NRF51UARTState *s = NRF51_UART(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-+
++    AwA10ClockCtlState *s = AW_A10_CCM(obj);
-+    memory_region_init_io(&s->iomem, obj, &uart_ops, s,
++
-+                          "nrf51_soc.uart", UART_SIZE);
++    /* Memory mapping */
 +    memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_ccm_ops, s,
 +                          TYPE_AW_A10_CCM, AW_A10_CCM_IOSIZE);
 +    sysbus_init_mmio(sbd, &s->iomem);
-+    sysbus_init_irq(sbd, &s->irq);
++}
-+}
++
-+
++static const VMStateDescription allwinner_a10_ccm_vmstate = {
-+static int nrf51_uart_post_load(void *opaque, int version_id)
++    .name = "allwinner-a10-ccm",
-+{
++    .version_id = 1,
-+    NRF51UARTState *s = NRF51_UART(opaque);
++    .minimum_version_id = 1,
 +
 +    if (s->pending_tx_byte) {
 +        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 +                                             uart_transmit, s);
 +    }
 +
 +    return 0;
 +}
 +
 +static const VMStateDescription nrf51_uart_vmstate = {
 +    .name = "nrf51_soc.uart",
 +    .post_load = nrf51_uart_post_load,
 +    .fields = (VMStateField[]) {
-+        VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C),
++        VMSTATE_UINT32_ARRAY(regs, AwA10ClockCtlState, AW_A10_CCM_REGS_NUM),
 +        VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH),
 +        VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState),
 +        VMSTATE_UINT32(rx_fifo_len, NRF51UARTState),
 +        VMSTATE_BOOL(rx_started, NRF51UARTState),
 +        VMSTATE_BOOL(tx_started, NRF51UARTState),
 +        VMSTATE_BOOL(pending_tx_byte, NRF51UARTState),
 +        VMSTATE_BOOL(enabled, NRF51UARTState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
-+static Property nrf51_uart_properties[] = {
++static void allwinner_a10_ccm_class_init(ObjectClass *klass, void *data)
 +    DEFINE_PROP_CHR("chardev", NRF51UARTState, chr),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void nrf51_uart_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
-+
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
-+    dc->reset = nrf51_uart_reset;
++
-+    dc->realize = nrf51_uart_realize;
++    rc->phases.enter = allwinner_a10_ccm_reset_enter;
-+    dc->props = nrf51_uart_properties;
++    dc->vmsd = &allwinner_a10_ccm_vmstate;
-+    dc->vmsd = &nrf51_uart_vmstate;
++}
-+}
++
-+
++static const TypeInfo allwinner_a10_ccm_info = {
-+static const TypeInfo nrf51_uart_info = {
++    .name          = TYPE_AW_A10_CCM,
-+    .name = TYPE_NRF51_UART,
++    .parent        = TYPE_SYS_BUS_DEVICE,
-+    .parent = TYPE_SYS_BUS_DEVICE,
++    .instance_init = allwinner_a10_ccm_init,
-+    .instance_size = sizeof(NRF51UARTState),
++    .instance_size = sizeof(AwA10ClockCtlState),
-+    .instance_init = nrf51_uart_init,
++    .class_init    = allwinner_a10_ccm_class_init,
-+    .class_init = nrf51_uart_class_init
++};
-+};
++
-+
++static void allwinner_a10_ccm_register(void)
-+static void nrf51_uart_register_types(void)
++{
-+{
++    type_register_static(&allwinner_a10_ccm_info);
-+    type_register_static(&nrf51_uart_info);
++}
-+}
++
-+
++type_init(allwinner_a10_ccm_register)
-+type_init(nrf51_uart_register_types)
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 diff --git a/hw/char/trace-events b/hw/char/trace-events
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/trace-events
+--- a/hw/arm/Kconfig
-+++ b/hw/char/trace-events
++++ b/hw/arm/Kconfig
-@@ -XXX,XX +XXX,XX @@ cmsdk_apb_uart_receive(uint8_t c) "CMSDK APB UART: got character 0x%x from backe
+@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
- cmsdk_apb_uart_tx_pending(void) "CMSDK APB UART: character send to backend pending"
+     select AHCI
- cmsdk_apb_uart_tx(uint8_t c) "CMSDK APB UART: character 0x%x sent to backend"
+     select ALLWINNER_A10_PIT
- cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
+     select ALLWINNER_A10_PIC
-+
++    select ALLWINNER_A10_CCM
-+# hw/char/nrf51_uart.c
+     select ALLWINNER_EMAC
-+nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
+     select SERIAL
-+nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
+     select UNIMP
 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config VIRT_CTRL
  config LASI
      bool
 +config ALLWINNER_A10_CCM
 +    bool
 +
  source macio/Kconfig
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ subdir('macio')
  softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c'))
 +softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c'))
  softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c'))
  specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'))
  softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
 --
-.19.1
+.34.1

-New patch
+[PULL 04/38] hw/misc: Allwinner A10 DRAM Controller Emulation
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
 During SPL boot several DRAM Controller registers are used. Most
 important registers are those related to DRAM initialization and
 calibration, where SPL initiates process and waits until certain bit is
 set/cleared.
 This patch adds these registers, initializes reset values from user's
 guide and updates state of registers as SPL expects it.
 Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
 Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
 Message-id: 20221226220303.14420-3-strahinja.p.jankovic@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/allwinner-a10.h        |   2 +
  include/hw/misc/allwinner-a10-dramc.h |  68 ++++++++++
  hw/arm/allwinner-a10.c                |   7 +
  hw/misc/allwinner-a10-dramc.c         | 179 ++++++++++++++++++++++++++
  hw/arm/Kconfig                        |   1 +
  hw/misc/Kconfig                       |   3 +
  hw/misc/meson.build                   |   1 +
 files changed, 261 insertions(+)
  create mode 100644 include/hw/misc/allwinner-a10-dramc.h
  create mode 100644 hw/misc/allwinner-a10-dramc.c
 diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/allwinner-a10.h
 +++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/usb/hcd-ehci.h"
  #include "hw/rtc/allwinner-rtc.h"
  #include "hw/misc/allwinner-a10-ccm.h"
 +#include "hw/misc/allwinner-a10-dramc.h"
  #include "target/arm/cpu.h"
  #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
      ARMCPU cpu;
      AwA10ClockCtlState ccm;
 +    AwA10DramControllerState dramc;
      AwA10PITState timer;
      AwA10PICState intc;
      AwEmacState emac;
 diff --git a/include/hw/misc/allwinner-a10-dramc.h b/include/hw/misc/allwinner-a10-dramc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/allwinner-a10-dramc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Allwinner A10 DRAM Controller emulation
 + *
 + * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
 + *
 + *  This file is derived from Allwinner H3 DRAMC,
 + *  by Niek Linnenbank.
 + *
 + * This program is free software: you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation, either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef HW_MISC_ALLWINNER_A10_DRAMC_H
 +#define HW_MISC_ALLWINNER_A10_DRAMC_H
 +
 +#include "qom/object.h"
 +#include "hw/sysbus.h"
 +#include "hw/register.h"
 +
 +/**
 + * @name Constants
 + * @{
 + */
 +
 +/** Size of register I/O address space used by DRAMC device */
 +#define AW_A10_DRAMC_IOSIZE        (0x1000)
 +
 +/** Total number of known registers */
 +#define AW_A10_DRAMC_REGS_NUM      (AW_A10_DRAMC_IOSIZE / sizeof(uint32_t))
 +
 +/** @} */
 +
 +/**
 + * @name Object model
 + * @{
 + */
 +
 +#define TYPE_AW_A10_DRAMC    "allwinner-a10-dramc"
 +OBJECT_DECLARE_SIMPLE_TYPE(AwA10DramControllerState, AW_A10_DRAMC)
 +
 +/** @} */
 +
 +/**
 + * Allwinner A10 DRAMC object instance state.
 + */
 +struct AwA10DramControllerState {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
 +    /*< public >*/
 +
 +    /** Maps I/O registers in physical memory */
 +    MemoryRegion iomem;
 +
 +    /** Array of hardware registers */
 +    uint32_t regs[AW_A10_DRAMC_REGS_NUM];
 +};
 +
 +#endif /* HW_MISC_ALLWINNER_A10_DRAMC_H */
 diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/allwinner-a10.c
 +++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/boards.h"
  #include "hw/usb/hcd-ohci.h"
 +#define AW_A10_DRAMC_BASE       0x01c01000
  #define AW_A10_MMC0_BASE        0x01c0f000
  #define AW_A10_CCM_BASE         0x01c20000
  #define AW_A10_PIC_REG_BASE     0x01c20400
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
      object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
 +    object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
 +
      object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
      object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
      sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
 +    /* DRAM Control Module */
 +    sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
 +
      /* FIXME use qdev NIC properties instead of nd_table[] */
      if (nd_table[0].used) {
          qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
 diff --git a/hw/misc/allwinner-a10-dramc.c b/hw/misc/allwinner-a10-dramc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/allwinner-a10-dramc.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Allwinner A10 DRAM Controller emulation
 + *
 + * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
 + *
 + *  This file is derived from Allwinner H3 DRAMC,
 + *  by Niek Linnenbank.
 + *
 + * This program is free software: you can redistribute it and/or modify
 + * it under the terms of the GNU General Public License as published by
 + * the Free Software Foundation, either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/units.h"
 +#include "hw/sysbus.h"
 +#include "migration/vmstate.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "hw/misc/allwinner-a10-dramc.h"
 +
 +/* DRAMC register offsets */
 +enum {
 +    REG_SDR_CCR = 0x0000,
 +    REG_SDR_ZQCR0 = 0x00a8,
 +    REG_SDR_ZQSR = 0x00b0
 +};
 +
 +#define REG_INDEX(offset)    (offset / sizeof(uint32_t))
 +
 +/* DRAMC register flags */
 +enum {
 +    REG_SDR_CCR_DATA_TRAINING = (1 << 30),
 +    REG_SDR_CCR_DRAM_INIT     = (1 << 31),
 +};
 +enum {
 +    REG_SDR_ZQSR_ZCAL         = (1 << 31),
 +};
 +
 +/* DRAMC register reset values */
 +enum {
 +    REG_SDR_CCR_RESET   = 0x80020000,
 +    REG_SDR_ZQCR0_RESET = 0x07b00000,
 +    REG_SDR_ZQSR_RESET  = 0x80000000
 +};
 +
 +static uint64_t allwinner_a10_dramc_read(void *opaque, hwaddr offset,
 +                                       unsigned size)
 +{
 +    const AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
 +    const uint32_t idx = REG_INDEX(offset);
 +
 +    switch (offset) {
 +    case REG_SDR_CCR:
 +    case REG_SDR_ZQCR0:
 +    case REG_SDR_ZQSR:
 +        break;
 +    case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
 +                      __func__, (uint32_t)offset);
 +        return 0;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
 +                      __func__, (uint32_t)offset);
 +        return 0;
 +    }
 +
 +    return s->regs[idx];
 +}
 +
 +static void allwinner_a10_dramc_write(void *opaque, hwaddr offset,
 +                                   uint64_t val, unsigned size)
 +{
 +    AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
 +    const uint32_t idx = REG_INDEX(offset);
 +
 +    switch (offset) {
 +    case REG_SDR_CCR:
 +        if (val & REG_SDR_CCR_DRAM_INIT) {
 +            /* Clear DRAM_INIT to indicate process is done. */
 +            val &= ~REG_SDR_CCR_DRAM_INIT;
 +        }
 +        if (val & REG_SDR_CCR_DATA_TRAINING) {
 +            /* Clear DATA_TRAINING to indicate process is done. */
 +            val &= ~REG_SDR_CCR_DATA_TRAINING;
 +        }
 +        break;
 +    case REG_SDR_ZQCR0:
 +        /* Set ZCAL in ZQSR to indicate calibration is done. */
 +        s->regs[REG_INDEX(REG_SDR_ZQSR)] |= REG_SDR_ZQSR_ZCAL;
 +        break;
 +    case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
 +                      __func__, (uint32_t)offset);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
 +                      __func__, (uint32_t)offset);
 +        break;
 +    }
 +
 +    s->regs[idx] = (uint32_t) val;
 +}
 +
 +static const MemoryRegionOps allwinner_a10_dramc_ops = {
 +    .read = allwinner_a10_dramc_read,
 +    .write = allwinner_a10_dramc_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +    },
 +    .impl.min_access_size = 4,
 +};
 +
 +static void allwinner_a10_dramc_reset_enter(Object *obj, ResetType type)
 +{
 +    AwA10DramControllerState *s = AW_A10_DRAMC(obj);
 +
 +    /* Set default values for registers */
 +    s->regs[REG_INDEX(REG_SDR_CCR)] = REG_SDR_CCR_RESET;
 +    s->regs[REG_INDEX(REG_SDR_ZQCR0)] = REG_SDR_ZQCR0_RESET;
 +    s->regs[REG_INDEX(REG_SDR_ZQSR)] = REG_SDR_ZQSR_RESET;
 +}
 +
 +static void allwinner_a10_dramc_init(Object *obj)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    AwA10DramControllerState *s = AW_A10_DRAMC(obj);
 +
 +    /* Memory mapping */
 +    memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_dramc_ops, s,
 +                          TYPE_AW_A10_DRAMC, AW_A10_DRAMC_IOSIZE);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +}
 +
 +static const VMStateDescription allwinner_a10_dramc_vmstate = {
 +    .name = "allwinner-a10-dramc",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, AwA10DramControllerState,
 +                             AW_A10_DRAMC_REGS_NUM),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void allwinner_a10_dramc_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +
 +    rc->phases.enter = allwinner_a10_dramc_reset_enter;
 +    dc->vmsd = &allwinner_a10_dramc_vmstate;
 +}
 +
 +static const TypeInfo allwinner_a10_dramc_info = {
 +    .name          = TYPE_AW_A10_DRAMC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_init = allwinner_a10_dramc_init,
 +    .instance_size = sizeof(AwA10DramControllerState),
 +    .class_init    = allwinner_a10_dramc_class_init,
 +};
 +
 +static void allwinner_a10_dramc_register(void)
 +{
 +    type_register_static(&allwinner_a10_dramc_info);
 +}
 +
 +type_init(allwinner_a10_dramc_register)
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
      select ALLWINNER_A10_PIT
      select ALLWINNER_A10_PIC
      select ALLWINNER_A10_CCM
 +    select ALLWINNER_A10_DRAMC
      select ALLWINNER_EMAC
      select SERIAL
      select UNIMP
 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config LASI
  config ALLWINNER_A10_CCM
      bool
 +config ALLWINNER_A10_DRAMC
 +    bool
 +
  source macio/Kconfig
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ subdir('macio')
  softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c'))
  softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c'))
 +softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_DRAMC', if_true: files('allwinner-a10-dramc.c'))
  softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c'))
  specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'))
  softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
 --
 .34.1

-[Qemu-devel] [PULL 2/6] hw/arm: versal: Add a model of Xilinx Versal SoC
+[PULL 05/38] {hw/i2c,docs/system/arm}: Allwinner TWI/I2C Emulation
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
-Add a model of Xilinx Versal SoC.
+This patch implements Allwinner TWI/I2C controller emulation. Only
 master-mode functionality is implemented.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this is
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+first part enabling the TWI/I2C bus operation.
 Since both Allwinner A10 and H3 use the same module, it is added for
 both boards.
 Docs are also updated for Cubieboard and Orangepi-PC board to indicate
 I2C availability.
 Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
 Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
 Message-id: 20221226220303.14420-4-strahinja.p.jankovic@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/Makefile.objs                |   1 +
+ docs/system/arm/cubieboard.rst |   1 +
- include/hw/arm/xlnx-versal.h        | 122 +++++++++++
+ docs/system/arm/orangepi.rst   |   1 +
- hw/arm/xlnx-versal.c                | 323 ++++++++++++++++++++++++++++
+ include/hw/arm/allwinner-a10.h |   2 +
- default-configs/aarch64-softmmu.mak |   1 +
+ include/hw/arm/allwinner-h3.h  |   3 +
-files changed, 447 insertions(+)
+ include/hw/i2c/allwinner-i2c.h |  55 ++++
- create mode 100644 include/hw/arm/xlnx-versal.h
+ hw/arm/allwinner-a10.c         |   8 +
- create mode 100644 hw/arm/xlnx-versal.c
+ hw/arm/allwinner-h3.c          |  11 +-
  hw/i2c/allwinner-i2c.c         | 459 +++++++++++++++++++++++++++++++++
  hw/arm/Kconfig                 |   2 +
  hw/i2c/Kconfig                 |   4 +
  hw/i2c/meson.build             |   1 +
  hw/i2c/trace-events            |   5 +
 files changed, 551 insertions(+), 1 deletion(-)
  create mode 100644 include/hw/i2c/allwinner-i2c.h
  create mode 100644 hw/i2c/allwinner-i2c.c
-diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
+diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/Makefile.objs
+--- a/docs/system/arm/cubieboard.rst
-+++ b/hw/arm/Makefile.objs
++++ b/docs/system/arm/cubieboard.rst
-@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
+@@ -XXX,XX +XXX,XX @@ Emulated devices:
- obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
+ - SDHCI
- obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
+ - USB controller
- obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
+ - SATA controller
-+obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o
++- TWI (I2C) controller
- obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
+diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
- obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
+index XXXXXXX..XXXXXXX 100644
- obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
+--- a/docs/system/arm/orangepi.rst
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
++++ b/docs/system/arm/orangepi.rst
@@ -XXX,XX +XXX,XX @@ The Orange Pi PC machine supports the following devices:
   * Clock Control Unit
   * System Control module
   * Security Identifier device
 + * TWI (I2C)
  Limitations
  """""""""""
 diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/allwinner-a10.h
 +++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/rtc/allwinner-rtc.h"
  #include "hw/misc/allwinner-a10-ccm.h"
  #include "hw/misc/allwinner-a10-dramc.h"
 +#include "hw/i2c/allwinner-i2c.h"
  #include "target/arm/cpu.h"
  #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
      AwEmacState emac;
      AllwinnerAHCIState sata;
      AwSdHostState mmc0;
 +    AWI2CState i2c0;
      AwRtcState rtc;
      MemoryRegion sram_a;
      EHCISysBusState ehci[AW_A10_NUM_USB];
 diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/allwinner-h3.h
 +++ b/include/hw/arm/allwinner-h3.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/sd/allwinner-sdhost.h"
  #include "hw/net/allwinner-sun8i-emac.h"
  #include "hw/rtc/allwinner-rtc.h"
 +#include "hw/i2c/allwinner-i2c.h"
  #include "target/arm/cpu.h"
  #include "sysemu/block-backend.h"
@@ -XXX,XX +XXX,XX @@ enum {
      AW_H3_DEV_UART2,
      AW_H3_DEV_UART3,
      AW_H3_DEV_EMAC,
 +    AW_H3_DEV_TWI0,
      AW_H3_DEV_DRAMCOM,
      AW_H3_DEV_DRAMCTL,
      AW_H3_DEV_DRAMPHY,
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
      AwH3SysCtrlState sysctrl;
      AwSidState sid;
      AwSdHostState mmc0;
 +    AWI2CState i2c0;
      AwSun8iEmacState emac;
      AwRtcState rtc;
      GICState gic;
 diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/arm/xlnx-versal.h
++++ b/include/hw/i2c/allwinner-i2c.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * Model of the Xilinx Versal
++ *  Allwinner I2C Bus Serial Interface registers definition
 + *
-+ * Copyright (c) 2018 Xilinx Inc.
++ *  Copyright (C) 2022 Strahinja Jankovic. <strahinja.p.jankovic@gmail.com>
-+ * Written by Edgar E. Iglesias
++ *
-+ *
++ *  This file is derived from IMX I2C controller,
-+ * This program is free software; you can redistribute it and/or modify
++ *  by Jean-Christophe DUBOIS .
-+ * it under the terms of the GNU General Public License version 2 or
++ *
-+ * (at your option) any later version.
++ *  This program is free software; you can redistribute it and/or modify it
 + *  under the terms of the GNU General Public License as published by the
 + *  Free Software Foundation; either version 2 of the License, or
 + *  (at your option) any later version.
 + *
 + *  This program is distributed in the hope that it will be useful, but WITHOUT
 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + *  for more details.
 + *
 + *  You should have received a copy of the GNU General Public License along
 + *  with this program; if not, see <http://www.gnu.org/licenses/>.
 + *
 + */
 +
-+#ifndef XLNX_VERSAL_H
++#ifndef ALLWINNER_I2C_H
-+#define XLNX_VERSAL_H
++#define ALLWINNER_I2C_H
 +
 +#include "hw/sysbus.h"
-+#include "hw/arm/arm.h"
++#include "qom/object.h"
-+#include "hw/intc/arm_gicv3.h"
++
-+
++#define TYPE_AW_I2C "allwinner.i2c"
-+#define TYPE_XLNX_VERSAL "xlnx-versal"
++OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
-+#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
++
-+
++#define AW_I2C_MEM_SIZE         0x24
-+#define XLNX_VERSAL_NR_ACPUS   2
++
-+#define XLNX_VERSAL_NR_UARTS   2
++struct AWI2CState {
 +#define XLNX_VERSAL_NR_GEMS    2
 +#define XLNX_VERSAL_NR_IRQS    256
 +
 +typedef struct Versal {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
 +
 +    /*< public >*/
-+    struct {
++    MemoryRegion iomem;
-+        struct {
++    I2CBus *bus;
-+            MemoryRegion mr;
++    qemu_irq irq;
-+            ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
++
-+            GICv3State gic;
++    uint8_t addr;
-+        } apu;
++    uint8_t xaddr;
-+    } fpd;
++    uint8_t data;
-+
++    uint8_t cntr;
-+    MemoryRegion mr_ps;
++    uint8_t stat;
-+
++    uint8_t ccr;
-+    struct {
++    uint8_t srst;
-+        /* 4 ranges to access DDR.  */
++    uint8_t efr;
-+        MemoryRegion mr_ddr_ranges[4];
++    uint8_t lcr;
-+    } noc;
++};
 +
-+    struct {
++#endif /* ALLWINNER_I2C_H */
-+        MemoryRegion mr_ocm;
+diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
-+
+index XXXXXXX..XXXXXXX 100644
-+        struct {
+--- a/hw/arm/allwinner-a10.c
-+            SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
++++ b/hw/arm/allwinner-a10.c
-+            SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
+@@ -XXX,XX +XXX,XX @@
-+        } iou;
+ #define AW_A10_OHCI_BASE        0x01c14400
-+    } lpd;
+ #define AW_A10_SATA_BASE        0x01c18000
-+
+ #define AW_A10_RTC_BASE         0x01c20d00
-+    struct {
++#define AW_A10_I2C0_BASE        0x01c2ac00
-+        MemoryRegion *mr_ddr;
-+        uint32_t psci_conduit;
+ static void aw_a10_init(Object *obj)
-+    } cfg;
+ {
-+} Versal;
+@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
-+
-+/* Memory-map and IRQ definitions. Copied a subset from
+     object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
-+ * auto-generated files.  */
-+
++    object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
-+#define VERSAL_GIC_MAINT_IRQ        9
++
-+#define VERSAL_TIMER_VIRT_IRQ       11
+     if (machine_usb(current_machine)) {
-+#define VERSAL_TIMER_S_EL1_IRQ      13
+         int i;
-+#define VERSAL_TIMER_NS_EL1_IRQ     14
-+#define VERSAL_TIMER_NS_EL2_IRQ     10
+@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
-+
+     /* RTC */
-+#define VERSAL_UART0_IRQ_0         18
+     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
-+#define VERSAL_UART1_IRQ_0         19
+     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
-+#define VERSAL_GEM0_IRQ_0          56
++
-+#define VERSAL_GEM0_WAKE_IRQ_0     57
++    /* I2C */
-+#define VERSAL_GEM1_IRQ_0          58
++    sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
-+#define VERSAL_GEM1_WAKE_IRQ_0     59
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
-+
++    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
-+/* Architecturally eserved IRQs suitable for virtualization.  */
+ }
-+#define VERSAL_RSVD_HIGH_IRQ_FIRST 160
-+#define VERSAL_RSVD_HIGH_IRQ_LAST  255
+ static void aw_a10_class_init(ObjectClass *oc, void *data)
-+
+diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
-+#define MM_TOP_RSVD                 0xa0000000U
+index XXXXXXX..XXXXXXX 100644
-+#define MM_TOP_RSVD_SIZE            0x4000000
+--- a/hw/arm/allwinner-h3.c
-+#define MM_GIC_APU_DIST_MAIN        0xf9000000U
++++ b/hw/arm/allwinner-h3.c
-+#define MM_GIC_APU_DIST_MAIN_SIZE   0x10000
+@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
-+#define MM_GIC_APU_REDIST_0         0xf9080000U
+     [AW_H3_DEV_UART1]      = 0x01c28400,
-+#define MM_GIC_APU_REDIST_0_SIZE    0x80000
+     [AW_H3_DEV_UART2]      = 0x01c28800,
-+
+     [AW_H3_DEV_UART3]      = 0x01c28c00,
-+#define MM_UART0                    0xff000000U
++    [AW_H3_DEV_TWI0]       = 0x01c2ac00,
-+#define MM_UART0_SIZE               0x10000
+     [AW_H3_DEV_EMAC]       = 0x01c30000,
-+#define MM_UART1                    0xff010000U
+     [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
-+#define MM_UART1_SIZE               0x10000
+     [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
-+
+@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
-+#define MM_GEM0                     0xff0c0000U
+     { "uart1",     0x01c28400, 1 * KiB },
-+#define MM_GEM0_SIZE                0x10000
+     { "uart2",     0x01c28800, 1 * KiB },
-+#define MM_GEM1                     0xff0d0000U
+     { "uart3",     0x01c28c00, 1 * KiB },
-+#define MM_GEM1_SIZE                0x10000
+-    { "twi0",      0x01c2ac00, 1 * KiB },
-+
+     { "twi1",      0x01c2b000, 1 * KiB },
-+#define MM_OCM                      0xfffc0000U
+     { "twi2",      0x01c2b400, 1 * KiB },
-+#define MM_OCM_SIZE                 0x40000
+     { "scr",       0x01c2c400, 1 * KiB },
-+
+@@ -XXX,XX +XXX,XX @@ enum {
-+#define MM_TOP_DDR                  0x0
+     AW_H3_GIC_SPI_UART1     =  1,
-+#define MM_TOP_DDR_SIZE             0x80000000U
+     AW_H3_GIC_SPI_UART2     =  2,
-+#define MM_TOP_DDR_2                0x800000000ULL
+     AW_H3_GIC_SPI_UART3     =  3,
-+#define MM_TOP_DDR_2_SIZE           0x800000000ULL
++    AW_H3_GIC_SPI_TWI0      =  6,
-+#define MM_TOP_DDR_3                0xc000000000ULL
+     AW_H3_GIC_SPI_TIMER0    = 18,
-+#define MM_TOP_DDR_3_SIZE           0x4000000000ULL
+     AW_H3_GIC_SPI_TIMER1    = 19,
-+#define MM_TOP_DDR_4                0x10000000000ULL
+     AW_H3_GIC_SPI_MMC0      = 60,
-+#define MM_TOP_DDR_4_SIZE           0xb780000000ULL
+@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
-+
+                               "ram-size");
-+#define MM_PSM_START                0xffc80000U
-+#define MM_PSM_END                  0xffcf0000U
+     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
 +
-+#define MM_CRL                      0xff5e0000U
++    object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
-+#define MM_CRL_SIZE                 0x300000
+ }
-+#define MM_IOU_SCNTR                0xff130000U
-+#define MM_IOU_SCNTR_SIZE           0x10000
+ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
-+#define MM_IOU_SCNTRS               0xff140000U
+@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
-+#define MM_IOU_SCNTRS_SIZE          0x10000
+     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
-+#define MM_FPD_CRF                  0xfd1a0000U
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
-+#define MM_FPD_CRF_SIZE             0x140000
-+#endif
++    /* I2C */
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
++    sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_H3_DEV_TWI0]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
 +                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
 +
      /* Unimplemented devices */
      for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
          create_unimplemented_device(unimplemented[i].device_name,
 diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/arm/xlnx-versal.c
++++ b/hw/i2c/allwinner-i2c.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * Xilinx Versal SoC model.
++ *  Allwinner I2C Bus Serial Interface Emulation
 + *
-+ * Copyright (c) 2018 Xilinx Inc.
++ *  Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
-+ * Written by Edgar E. Iglesias
++ *
-+ *
++ *  This file is derived from IMX I2C controller,
-+ * This program is free software; you can redistribute it and/or modify
++ *  by Jean-Christophe DUBOIS .
-+ * it under the terms of the GNU General Public License version 2 or
++ *
-+ * (at your option) any later version.
++ *  This program is free software; you can redistribute it and/or modify it
 + *  under the terms of the GNU General Public License as published by the
 + *  Free Software Foundation; either version 2 of the License, or
 + *  (at your option) any later version.
 + *
 + *  This program is distributed in the hope that it will be useful, but WITHOUT
 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + *  for more details.
 + *
 + *  You should have received a copy of the GNU General Public License along
 + *  with this program; if not, see <http://www.gnu.org/licenses/>.
 + *
 + * SPDX-License-Identifier: MIT
 + */
 +
 +#include "qemu/osdep.h"
-+#include "qapi/error.h"
++#include "hw/i2c/allwinner-i2c.h"
-+#include "qemu-common.h"
++#include "hw/irq.h"
 +#include "migration/vmstate.h"
 +#include "hw/i2c/i2c.h"
 +#include "qemu/log.h"
-+#include "hw/sysbus.h"
++#include "trace.h"
-+#include "net/net.h"
++#include "qemu/module.h"
-+#include "sysemu/sysemu.h"
++
-+#include "sysemu/kvm.h"
++/* Allwinner I2C memory map */
-+#include "hw/arm/arm.h"
++#define TWI_ADDR_REG            0x00  /* slave address register */
-+#include "kvm_arm.h"
++#define TWI_XADDR_REG           0x04  /* extended slave address register */
-+#include "hw/misc/unimp.h"
++#define TWI_DATA_REG            0x08  /* data register */
-+#include "hw/intc/arm_gicv3_common.h"
++#define TWI_CNTR_REG            0x0c  /* control register */
-+#include "hw/arm/xlnx-versal.h"
++#define TWI_STAT_REG            0x10  /* status register */
-+
++#define TWI_CCR_REG             0x14  /* clock control register */
-+#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
++#define TWI_SRST_REG            0x18  /* software reset register */
-+#define GEM_REVISION        0x40070106
++#define TWI_EFR_REG             0x1c  /* enhance feature register */
-+
++#define TWI_LCR_REG             0x20  /* line control register */
-+static void versal_create_apu_cpus(Versal *s)
++
-+{
++/* Used only in slave mode, do not set */
-+    int i;
++#define TWI_ADDR_RESET          0
-+
++#define TWI_XADDR_RESET         0
-+    for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
++
-+        Object *obj;
++/* Data register */
-+        char *name;
++#define TWI_DATA_MASK           0xFF
-+
++#define TWI_DATA_RESET          0
-+        obj = object_new(XLNX_VERSAL_ACPU_TYPE);
++
-+        if (!obj) {
++/* Control register */
-+            /* Secondary CPUs start in PSCI powered-down state */
++#define TWI_CNTR_INT_EN         (1 << 7)
-+            error_report("Unable to create apu.cpu[%d] of type %s",
++#define TWI_CNTR_BUS_EN         (1 << 6)
-+                         i, XLNX_VERSAL_ACPU_TYPE);
++#define TWI_CNTR_M_STA          (1 << 5)
-+            exit(EXIT_FAILURE);
++#define TWI_CNTR_M_STP          (1 << 4)
 +#define TWI_CNTR_INT_FLAG       (1 << 3)
 +#define TWI_CNTR_A_ACK          (1 << 2)
 +#define TWI_CNTR_MASK           0xFC
 +#define TWI_CNTR_RESET          0
 +
 +/* Status register */
 +#define TWI_STAT_MASK           0xF8
 +#define TWI_STAT_RESET          0xF8
 +
 +/* Clock register */
 +#define TWI_CCR_CLK_M_MASK      0x78
 +#define TWI_CCR_CLK_N_MASK      0x07
 +#define TWI_CCR_MASK            0x7F
 +#define TWI_CCR_RESET           0
 +
 +/* Soft reset */
 +#define TWI_SRST_MASK           0x01
 +#define TWI_SRST_RESET          0
 +
 +/* Enhance feature */
 +#define TWI_EFR_MASK            0x03
 +#define TWI_EFR_RESET           0
 +
 +/* Line control */
 +#define TWI_LCR_SCL_STATE       (1 << 5)
 +#define TWI_LCR_SDA_STATE       (1 << 4)
 +#define TWI_LCR_SCL_CTL         (1 << 3)
 +#define TWI_LCR_SCL_CTL_EN      (1 << 2)
 +#define TWI_LCR_SDA_CTL         (1 << 1)
 +#define TWI_LCR_SDA_CTL_EN      (1 << 0)
 +#define TWI_LCR_MASK            0x3F
 +#define TWI_LCR_RESET           0x3A
 +
 +/* Status value in STAT register is shifted by 3 bits */
 +#define TWI_STAT_SHIFT      3
 +#define STAT_FROM_STA(x)    ((x) << TWI_STAT_SHIFT)
 +#define STAT_TO_STA(x)      ((x) >> TWI_STAT_SHIFT)
 +
 +enum {
 +    STAT_BUS_ERROR = 0,
 +    /* Master mode */
 +    STAT_M_STA_TX,
 +    STAT_M_RSTA_TX,
 +    STAT_M_ADDR_WR_ACK,
 +    STAT_M_ADDR_WR_NACK,
 +    STAT_M_DATA_TX_ACK,
 +    STAT_M_DATA_TX_NACK,
 +    STAT_M_ARB_LOST,
 +    STAT_M_ADDR_RD_ACK,
 +    STAT_M_ADDR_RD_NACK,
 +    STAT_M_DATA_RX_ACK,
 +    STAT_M_DATA_RX_NACK,
 +    /* Slave mode */
 +    STAT_S_ADDR_WR_ACK,
 +    STAT_S_ARB_LOST_AW_ACK,
 +    STAT_S_GCA_ACK,
 +    STAT_S_ARB_LOST_GCA_ACK,
 +    STAT_S_DATA_RX_SA_ACK,
 +    STAT_S_DATA_RX_SA_NACK,
 +    STAT_S_DATA_RX_GCA_ACK,
 +    STAT_S_DATA_RX_GCA_NACK,
 +    STAT_S_STP_RSTA,
 +    STAT_S_ADDR_RD_ACK,
 +    STAT_S_ARB_LOST_AR_ACK,
 +    STAT_S_DATA_TX_ACK,
 +    STAT_S_DATA_TX_NACK,
 +    STAT_S_LB_TX_ACK,
 +    /* Master mode, 10-bit */
 +    STAT_M_2ND_ADDR_WR_ACK,
 +    STAT_M_2ND_ADDR_WR_NACK,
 +    /* Idle */
 +    STAT_IDLE = 0x1f
 +} TWI_STAT_STA;
 +
 +static const char *allwinner_i2c_get_regname(unsigned offset)
 +{
 +    switch (offset) {
 +    case TWI_ADDR_REG:
 +        return "ADDR";
 +    case TWI_XADDR_REG:
 +        return "XADDR";
 +    case TWI_DATA_REG:
 +        return "DATA";
 +    case TWI_CNTR_REG:
 +        return "CNTR";
 +    case TWI_STAT_REG:
 +        return "STAT";
 +    case TWI_CCR_REG:
 +        return "CCR";
 +    case TWI_SRST_REG:
 +        return "SRST";
 +    case TWI_EFR_REG:
 +        return "EFR";
 +    case TWI_LCR_REG:
 +        return "LCR";
 +    default:
 +        return "[?]";
 +    }
 +}
 +
 +static inline bool allwinner_i2c_is_reset(AWI2CState *s)
 +{
 +    return s->srst & TWI_SRST_MASK;
 +}
 +
 +static inline bool allwinner_i2c_bus_is_enabled(AWI2CState *s)
 +{
 +    return s->cntr & TWI_CNTR_BUS_EN;
 +}
 +
 +static inline bool allwinner_i2c_interrupt_is_enabled(AWI2CState *s)
 +{
 +    return s->cntr & TWI_CNTR_INT_EN;
 +}
 +
 +static void allwinner_i2c_reset_hold(Object *obj)
 +{
 +    AWI2CState *s = AW_I2C(obj);
 +
 +    if (STAT_TO_STA(s->stat) != STAT_IDLE) {
 +        i2c_end_transfer(s->bus);
 +    }
 +
 +    s->addr  = TWI_ADDR_RESET;
 +    s->xaddr = TWI_XADDR_RESET;
 +    s->data  = TWI_DATA_RESET;
 +    s->cntr  = TWI_CNTR_RESET;
 +    s->stat  = TWI_STAT_RESET;
 +    s->ccr   = TWI_CCR_RESET;
 +    s->srst  = TWI_SRST_RESET;
 +    s->efr   = TWI_EFR_RESET;
 +    s->lcr   = TWI_LCR_RESET;
 +}
 +
 +static inline void allwinner_i2c_raise_interrupt(AWI2CState *s)
 +{
 +    /*
 +     * Raise an interrupt if the device is not reset and it is configured
 +     * to generate some interrupts.
 +     */
 +    if (!allwinner_i2c_is_reset(s) && allwinner_i2c_bus_is_enabled(s)) {
 +        if (STAT_TO_STA(s->stat) != STAT_IDLE) {
 +            s->cntr |= TWI_CNTR_INT_FLAG;
 +            if (allwinner_i2c_interrupt_is_enabled(s)) {
 +                qemu_irq_raise(s->irq);
 +            }
 +        }
-+
++    }
-+        name = g_strdup_printf("apu-cpu[%d]", i);
++}
-+        object_property_add_child(OBJECT(s), name, obj, &error_fatal);
++
-+        g_free(name);
++static uint64_t allwinner_i2c_read(void *opaque, hwaddr offset,
-+
++                                   unsigned size)
-+        object_property_set_int(obj, s->cfg.psci_conduit,
++{
-+                                "psci-conduit", &error_abort);
++    uint16_t value;
-+        if (i) {
++    AWI2CState *s = AW_I2C(opaque);
-+            object_property_set_bool(obj, true,
++
-+                                     "start-powered-off", &error_abort);
++    switch (offset) {
 +    case TWI_ADDR_REG:
 +        value = s->addr;
 +        break;
 +    case TWI_XADDR_REG:
 +        value = s->xaddr;
 +        break;
 +    case TWI_DATA_REG:
 +        if ((STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) ||
 +            (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) ||
 +            (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK)) {
 +            /* Get the next byte */
 +            s->data = i2c_recv(s->bus);
 +
 +            if (s->cntr & TWI_CNTR_A_ACK) {
 +                s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
 +            } else {
 +                s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
 +            }
 +            allwinner_i2c_raise_interrupt(s);
 +        }
-+
++        value = s->data;
-+        object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu),
++        break;
-+                                "core-count", &error_abort);
++    case TWI_CNTR_REG:
-+        object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
++        value = s->cntr;
-+                                 &error_abort);
++        break;
-+        object_property_set_bool(obj, true, "realized", &error_fatal);
++    case TWI_STAT_REG:
-+        s->fpd.apu.cpu[i] = ARM_CPU(obj);
++        value = s->stat;
 +        /*
 +         * If polling when reading then change state to indicate data
 +         * is available
 +         */
 +        if (STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) {
 +            if (s->cntr & TWI_CNTR_A_ACK) {
 +                s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
 +            } else {
 +                s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
 +            }
 +            allwinner_i2c_raise_interrupt(s);
 +        }
 +        break;
 +    case TWI_CCR_REG:
 +        value = s->ccr;
 +        break;
 +    case TWI_SRST_REG:
 +        value = s->srst;
 +        break;
 +    case TWI_EFR_REG:
 +        value = s->efr;
 +        break;
 +    case TWI_LCR_REG:
 +        value = s->lcr;
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset);
 +        value = 0;
 +        break;
 +    }
-+}
++
-+
++    trace_allwinner_i2c_read(allwinner_i2c_get_regname(offset), offset, value);
-+static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
++
-+{
++    return (uint64_t)value;
-+    static const uint64_t addrs[] = {
++}
-+        MM_GIC_APU_DIST_MAIN,
++
-+        MM_GIC_APU_REDIST_0
++static void allwinner_i2c_write(void *opaque, hwaddr offset,
-+    };
++                                uint64_t value, unsigned size)
-+    SysBusDevice *gicbusdev;
++{
-+    DeviceState *gicdev;
++    AWI2CState *s = AW_I2C(opaque);
-+    int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
++
-+    int i;
++    value &= 0xff;
 +
-+    sysbus_init_child_obj(OBJECT(s), "apu-gic",
++    trace_allwinner_i2c_write(allwinner_i2c_get_regname(offset), offset, value);
-+                          &s->fpd.apu.gic, sizeof(s->fpd.apu.gic),
++
-+                          gicv3_class_name());
++    switch (offset) {
-+    gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
++    case TWI_ADDR_REG:
-+    gicdev = DEVICE(&s->fpd.apu.gic);
++        s->addr = (uint8_t)value;
-+    qdev_prop_set_uint32(gicdev, "revision", 3);
++        break;
-+    qdev_prop_set_uint32(gicdev, "num-cpu", 2);
++    case TWI_XADDR_REG:
-+    qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);
++        s->xaddr = (uint8_t)value;
-+    qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
++        break;
-+    qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2);
++    case TWI_DATA_REG:
-+    qdev_prop_set_bit(gicdev, "has-security-extensions", true);
++        /* If the device is in reset or not enabled, nothing to do */
-+
++        if (allwinner_i2c_is_reset(s) || (!allwinner_i2c_bus_is_enabled(s))) {
-+    object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized",
++            break;
-+                                    &error_fatal);
++        }
 +
-+    for (i = 0; i < ARRAY_SIZE(addrs); i++) {
++        s->data = value & TWI_DATA_MASK;
-+        MemoryRegion *mr;
++
-+
++        switch (STAT_TO_STA(s->stat)) {
-+        mr = sysbus_mmio_get_region(gicbusdev, i);
++        case STAT_M_STA_TX:
-+        memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);
++        case STAT_M_RSTA_TX:
 +            /* Send address */
 +            if (i2c_start_transfer(s->bus, extract32(s->data, 1, 7),
 +                                extract32(s->data, 0, 1))) {
 +                /* If non zero is returned, the address is not valid */
 +                s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_NACK);
 +            } else {
 +                /* Determine if read of write */
 +                if (extract32(s->data, 0, 1)) {
 +                    s->stat = STAT_FROM_STA(STAT_M_ADDR_RD_ACK);
 +                } else {
 +                    s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_ACK);
 +                }
 +                allwinner_i2c_raise_interrupt(s);
 +            }
 +            break;
 +        case STAT_M_ADDR_WR_ACK:
 +        case STAT_M_DATA_TX_ACK:
 +            if (i2c_send(s->bus, s->data)) {
 +                /* If the target return non zero then end the transfer */
 +                s->stat = STAT_FROM_STA(STAT_M_DATA_TX_NACK);
 +                i2c_end_transfer(s->bus);
 +            } else {
 +                s->stat = STAT_FROM_STA(STAT_M_DATA_TX_ACK);
 +                allwinner_i2c_raise_interrupt(s);
 +            }
 +            break;
 +        default:
 +            break;
 +        }
 +        break;
 +    case TWI_CNTR_REG:
 +        if (!allwinner_i2c_is_reset(s)) {
 +            /* Do something only if not in software reset */
 +            s->cntr = value & TWI_CNTR_MASK;
 +
 +            /* Check if start condition should be sent */
 +            if (s->cntr & TWI_CNTR_M_STA) {
 +                /* Update status */
 +                if (STAT_TO_STA(s->stat) == STAT_IDLE) {
 +                    /* Send start condition */
 +                    s->stat = STAT_FROM_STA(STAT_M_STA_TX);
 +                } else {
 +                    /* Send repeated start condition */
 +                    s->stat = STAT_FROM_STA(STAT_M_RSTA_TX);
 +                }
 +                /* Clear start condition */
 +                s->cntr &= ~TWI_CNTR_M_STA;
 +            }
 +            if (s->cntr & TWI_CNTR_M_STP) {
 +                /* Update status */
 +                i2c_end_transfer(s->bus);
 +                s->stat = STAT_FROM_STA(STAT_IDLE);
 +                s->cntr &= ~TWI_CNTR_M_STP;
 +            }
 +            if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
 +                /* Interrupt flag cleared */
 +                qemu_irq_lower(s->irq);
 +            }
 +            if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
 +                if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
 +                    s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
 +                }
 +            } else {
 +                if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK) {
 +                    s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
 +                }
 +            }
 +            allwinner_i2c_raise_interrupt(s);
 +
 +        }
 +        break;
 +    case TWI_CCR_REG:
 +        s->ccr = value & TWI_CCR_MASK;
 +        break;
 +    case TWI_SRST_REG:
 +        if (((value & TWI_SRST_MASK) == 0) && (s->srst & TWI_SRST_MASK)) {
 +            /* Perform reset */
 +            allwinner_i2c_reset_hold(OBJECT(s));
 +        }
 +        s->srst = value & TWI_SRST_MASK;
 +        break;
 +    case TWI_EFR_REG:
 +        s->efr = value & TWI_EFR_MASK;
 +        break;
 +    case TWI_LCR_REG:
 +        s->lcr = value & TWI_LCR_MASK;
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset);
 +        break;
 +    }
-+
++}
-+    for (i = 0; i < nr_apu_cpus; i++) {
++
-+        DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);
++static const MemoryRegionOps allwinner_i2c_ops = {
-+        int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
++    .read = allwinner_i2c_read,
-+        qemu_irq maint_irq;
++    .write = allwinner_i2c_write,
-+        int ti;
++    .valid.min_access_size = 1,
-+        /* Mapping from the output timer irq lines from the CPU to the
++    .valid.max_access_size = 4,
-+         * GIC PPI inputs.
++    .endianness = DEVICE_NATIVE_ENDIAN,
-+         */
++};
-+        const int timer_irq[] = {
++
-+            [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
++static const VMStateDescription allwinner_i2c_vmstate = {
-+            [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
++    .name = TYPE_AW_I2C,
-+            [GTIMER_HYP]  = VERSAL_TIMER_NS_EL2_IRQ,
++    .version_id = 1,
-+            [GTIMER_SEC]  = VERSAL_TIMER_S_EL1_IRQ,
++    .minimum_version_id = 1,
-+        };
++    .fields = (VMStateField[]) {
-+
++        VMSTATE_UINT8(addr, AWI2CState),
-+        for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {
++        VMSTATE_UINT8(xaddr, AWI2CState),
-+            qdev_connect_gpio_out(cpudev, ti,
++        VMSTATE_UINT8(data, AWI2CState),
-+                                  qdev_get_gpio_in(gicdev,
++        VMSTATE_UINT8(cntr, AWI2CState),
-+                                                   ppibase + timer_irq[ti]));
++        VMSTATE_UINT8(ccr, AWI2CState),
-+        }
++        VMSTATE_UINT8(srst, AWI2CState),
-+        maint_irq = qdev_get_gpio_in(gicdev,
++        VMSTATE_UINT8(efr, AWI2CState),
-+                                        ppibase + VERSAL_GIC_MAINT_IRQ);
++        VMSTATE_UINT8(lcr, AWI2CState),
-+        qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
++        VMSTATE_END_OF_LIST()
 +                                    0, maint_irq);
 +        sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 +        sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,
 +                           qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 +        sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,
 +                           qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 +        sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,
 +                           qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 +    }
-+
-+    for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {
-+        pic[i] = qdev_get_gpio_in(gicdev, i);
-+    }
-+}
-+
-+static void versal_create_uarts(Versal *s, qemu_irq *pic)
-+{
-+    int i;
-+
-+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
-+        static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};
-+        static const uint64_t addrs[] = { MM_UART0, MM_UART1 };
-+        char *name = g_strdup_printf("uart%d", i);
-+        DeviceState *dev;
-+        MemoryRegion *mr;
-+
-+        dev = qdev_create(NULL, "pl011");
-+        s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);
-+        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
-+        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
-+        qdev_init_nofail(dev);
-+
-+        mr = sysbus_mmio_get_region(s->lpd.iou.uart[i], 0);
-+        memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
-+
-+        sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]);
-+        g_free(name);
-+    }
-+}
-+
-+static void versal_create_gems(Versal *s, qemu_irq *pic)
-+{
-+    int i;
-+
-+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
-+        static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0};
-+        static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 };
-+        char *name = g_strdup_printf("gem%d", i);
-+        NICInfo *nd = &nd_table[i];
-+        DeviceState *dev;
-+        MemoryRegion *mr;
-+
-+        dev = qdev_create(NULL, "cadence_gem");
-+        s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);
-+        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
-+        if (nd->used) {
-+            qemu_check_nic_model(nd, "cadence_gem");
-+            qdev_set_nic_properties(dev, nd);
-+        }
-+        object_property_set_int(OBJECT(s->lpd.iou.gem[i]),
-+                                2, "num-priority-queues",
-+                                &error_abort);
-+        object_property_set_link(OBJECT(s->lpd.iou.gem[i]),
-+                                 OBJECT(&s->mr_ps), "dma",
-+                                 &error_abort);
-+        qdev_init_nofail(dev);
-+
-+        mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);
-+        memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
-+
-+        sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);
-+        g_free(name);
-+    }
-+}
-+
-+/* This takes the board allocated linear DDR memory and creates aliases
-+ * for each split DDR range/aperture on the Versal address map.
-+ */
-+static void versal_map_ddr(Versal *s)
-+{
-+    uint64_t size = memory_region_size(s->cfg.mr_ddr);
-+    /* Describes the various split DDR access regions.  */
-+    static const struct {
-+        uint64_t base;
-+        uint64_t size;
-+    } addr_ranges[] = {
-+        { MM_TOP_DDR, MM_TOP_DDR_SIZE },
-+        { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
-+        { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
-+        { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
-+    };
-+    uint64_t offset = 0;
-+    int i;
-+
-+    assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges));
-+    for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
-+        char *name;
-+        uint64_t mapsize;
-+
-+        mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
-+        name = g_strdup_printf("noc-ddr-range%d", i);
-+        /* Create the MR alias.  */
-+        memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s),
-+                                 name, s->cfg.mr_ddr,
-+                                 offset, mapsize);
-+
-+        /* Map it onto the NoC MR.  */
-+        memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base,
-+                                    &s->noc.mr_ddr_ranges[i]);
-+        offset += mapsize;
-+        size -= mapsize;
-+        g_free(name);
-+    }
-+}
-+
-+static void versal_unimp_area(Versal *s, const char *name,
-+                                MemoryRegion *mr,
-+                                hwaddr base, hwaddr size)
-+{
-+    DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
-+    MemoryRegion *mr_dev;
-+
-+    qdev_prop_set_string(dev, "name", name);
-+    qdev_prop_set_uint64(dev, "size", size);
-+    object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
-+    qdev_init_nofail(dev);
-+
-+    mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
-+    memory_region_add_subregion(mr, base, mr_dev);
-+}
-+
-+static void versal_unimp(Versal *s)
-+{
-+    versal_unimp_area(s, "psm", &s->mr_ps,
-+                        MM_PSM_START, MM_PSM_END - MM_PSM_START);
-+    versal_unimp_area(s, "crl", &s->mr_ps,
-+                        MM_CRL, MM_CRL_SIZE);
-+    versal_unimp_area(s, "crf", &s->mr_ps,
-+                        MM_FPD_CRF, MM_FPD_CRF_SIZE);
-+    versal_unimp_area(s, "iou-scntr", &s->mr_ps,
-+                        MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
-+    versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
-+                        MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);
-+}
-+
-+static void versal_realize(DeviceState *dev, Error **errp)
-+{
-+    Versal *s = XLNX_VERSAL(dev);
-+    qemu_irq pic[XLNX_VERSAL_NR_IRQS];
-+
-+    versal_create_apu_cpus(s);
-+    versal_create_apu_gic(s, pic);
-+    versal_create_uarts(s, pic);
-+    versal_create_gems(s, pic);
-+    versal_map_ddr(s);
-+    versal_unimp(s);
-+
-+    /* Create the On Chip Memory (OCM).  */
-+    memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
-+                           MM_OCM_SIZE, &error_fatal);
-+
-+    memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
-+    memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
-+}
-+
-+static void versal_init(Object *obj)
-+{
-+    Versal *s = XLNX_VERSAL(obj);
-+
-+    memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
-+    memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
-+}
-+
-+static Property versal_properties[] = {
-+    DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
-+                     MemoryRegion *),
-+    DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0),
-+    DEFINE_PROP_END_OF_LIST()
 +};
 +
-+static void versal_class_init(ObjectClass *klass, void *data)
++static void allwinner_i2c_realize(DeviceState *dev, Error **errp)
 +{
 +    AWI2CState *s = AW_I2C(dev);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_i2c_ops, s,
 +                          TYPE_AW_I2C, AW_I2C_MEM_SIZE);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 +    sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
 +    s->bus = i2c_init_bus(dev, "i2c");
 +}
 +
 +static void allwinner_i2c_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
-+
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
-+    dc->realize = versal_realize;
++
-+    dc->props = versal_properties;
++    rc->phases.hold = allwinner_i2c_reset_hold;
-+    /* No VMSD since we haven't got any top-level SoC state to save.  */
++    dc->vmsd = &allwinner_i2c_vmstate;
-+}
++    dc->realize = allwinner_i2c_realize;
-+
++    dc->desc = "Allwinner I2C Controller";
-+static const TypeInfo versal_info = {
++}
-+    .name = TYPE_XLNX_VERSAL,
++
 +static const TypeInfo allwinner_i2c_type_info = {
 +    .name = TYPE_AW_I2C,
 +    .parent = TYPE_SYS_BUS_DEVICE,
-+    .instance_size = sizeof(Versal),
++    .instance_size = sizeof(AWI2CState),
-+    .instance_init = versal_init,
++    .class_init = allwinner_i2c_class_init,
 +    .class_init = versal_class_init,
 +};
 +
-+static void versal_register_types(void)
++static void allwinner_i2c_register_types(void)
 +{
-+    type_register_static(&versal_info);
++    type_register_static(&allwinner_i2c_type_info);
 +}
 +
-+type_init(versal_register_types);
++type_init(allwinner_i2c_register_types)
-diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
---- a/default-configs/aarch64-softmmu.mak
+--- a/hw/arm/Kconfig
-+++ b/default-configs/aarch64-softmmu.mak
++++ b/hw/arm/Kconfig
-@@ -XXX,XX +XXX,XX @@ CONFIG_DDC=y
+@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
- CONFIG_DPCD=y
+     select ALLWINNER_A10_CCM
- CONFIG_XLNX_ZYNQMP=y
+     select ALLWINNER_A10_DRAMC
- CONFIG_XLNX_ZYNQMP_ARM=y
+     select ALLWINNER_EMAC
-+CONFIG_XLNX_VERSAL=y
++    select ALLWINNER_I2C
- CONFIG_ARM_SMMUV3=y
+     select SERIAL
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
      bool
      select ALLWINNER_A10_PIT
      select ALLWINNER_SUN8I_EMAC
 +    select ALLWINNER_I2C
      select SERIAL
      select ARM_TIMER
      select ARM_GIC
 diff --git a/hw/i2c/Kconfig b/hw/i2c/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/i2c/Kconfig
 +++ b/hw/i2c/Kconfig
@@ -XXX,XX +XXX,XX @@ config MPC_I2C
      bool
      select I2C
 +config ALLWINNER_I2C
 +    bool
 +    select I2C
 +
  config PCA954X
      bool
      select I2C
 diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/i2c/meson.build
 +++ b/hw/i2c/meson.build
@@ -XXX,XX +XXX,XX @@ i2c_ss.add(when: 'CONFIG_BITBANG_I2C', if_true: files('bitbang_i2c.c'))
  i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c'))
  i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c'))
  i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c'))
 +i2c_ss.add(when: 'CONFIG_ALLWINNER_I2C', if_true: files('allwinner-i2c.c'))
  i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c'))
  i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c'))
  i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c'))
 diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/i2c/trace-events
 +++ b/hw/i2c/trace-events
@@ -XXX,XX +XXX,XX @@ i2c_send_async(uint8_t address, uint8_t data) "send_async(addr:0x%02x) data:0x%0
  i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x"
  i2c_ack(void) ""
 +# allwinner_i2c.c
 +
 +allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value) "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64
 +allwinner_i2c_write(const char* reg_name, uint64_t offset, uint64_t value) "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64
 +
  # aspeed_i2c.c
  aspeed_i2c_bus_cmd(uint32_t cmd, const char *cmd_flags, uint32_t count, uint32_t intr_status) "handling cmd=0x%x %s count=%d intr=0x%x"
 --
-.19.1
+.34.1

-[Qemu-devel] [PULL 3/6] hw/arm: versal: Add a virtual Xilinx Versal board
+[PULL 06/38] hw/misc: AXP209 PMU Emulation
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
-Add a virtual Xilinx Versal board.
+This patch adds minimal support for AXP-209 PMU.
 Most important is chip ID since U-Boot SPL expects version 0x1. Besides
 the chip ID register, reset values for two more registers used by A10
 U-Boot SPL are covered.
-This board is based on the Xilinx Versal SoC. The exact
+Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
-details of what peripherals are attached to this board
+Message-id: 20221226220303.14420-5-strahinja.p.jankovic@gmail.com
 will remain in control of QEMU. QEMU will generate an
 FDT on the fly for Linux and other software to auto-discover
 peripherals.
 Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 [PMM: removed stray blank line at EOF]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/Makefile.objs      |   2 +-
+ hw/misc/axp209.c     | 238 +++++++++++++++++++++++++++++++++++++++++++
- hw/arm/xlnx-versal-virt.c | 493 ++++++++++++++++++++++++++++++++++++++
+ MAINTAINERS          |   2 +
-files changed, 494 insertions(+), 1 deletion(-)
+ hw/misc/Kconfig      |   4 +
- create mode 100644 hw/arm/xlnx-versal-virt.c
+ hw/misc/meson.build  |   1 +
  hw/misc/trace-events |   5 +
 files changed, 250 insertions(+)
  create mode 100644 hw/misc/axp209.c
-diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
+diff --git a/hw/misc/axp209.c b/hw/misc/axp209.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Makefile.objs
 +++ b/hw/arm/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
  obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
  obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
  obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
 -obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o
 +obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
  obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
  obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
  obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/arm/xlnx-versal-virt.c
++++ b/hw/misc/axp209.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * Xilinx Versal Virtual board.
++ * AXP-209 PMU Emulation
 + *
-+ * Copyright (c) 2018 Xilinx Inc.
++ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
-+ * Written by Edgar E. Iglesias
++ *
-+ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
-+ * This program is free software; you can redistribute it and/or modify
++ * copy of this software and associated documentation files (the "Software"),
-+ * it under the terms of the GNU General Public License version 2 or
++ * to deal in the Software without restriction, including without limitation
-+ * (at your option) any later version.
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 + * DEALINGS IN THE SOFTWARE.
 + *
 + * SPDX-License-Identifier: MIT
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
-+#include "qemu/error-report.h"
++#include "trace.h"
-+#include "qapi/error.h"
++#include "hw/i2c/i2c.h"
-+#include "sysemu/device_tree.h"
++#include "migration/vmstate.h"
-+#include "exec/address-spaces.h"
++
-+#include "hw/boards.h"
++#define TYPE_AXP209_PMU "axp209_pmu"
-+#include "hw/sysbus.h"
++
-+#include "hw/arm/sysbus-fdt.h"
++#define AXP209(obj) \
-+#include "hw/arm/fdt.h"
++    OBJECT_CHECK(AXP209I2CState, (obj), TYPE_AXP209_PMU)
-+#include "cpu.h"
++
-+#include "hw/arm/xlnx-versal.h"
++/* registers */
-+
++enum {
-+#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
++    REG_POWER_STATUS = 0x0u,
-+#define XLNX_VERSAL_VIRT_MACHINE(obj) \
++    REG_OPERATING_MODE,
-+    OBJECT_CHECK(VersalVirt, (obj), TYPE_XLNX_VERSAL_VIRT_MACHINE)
++    REG_OTG_VBUS_STATUS,
-+
++    REG_CHIP_VERSION,
-+typedef struct VersalVirt {
++    REG_DATA_CACHE_0,
-+    MachineState parent_obj;
++    REG_DATA_CACHE_1,
-+
++    REG_DATA_CACHE_2,
-+    Versal soc;
++    REG_DATA_CACHE_3,
-+    MemoryRegion mr_ddr;
++    REG_DATA_CACHE_4,
-+
++    REG_DATA_CACHE_5,
-+    void *fdt;
++    REG_DATA_CACHE_6,
-+    int fdt_size;
++    REG_DATA_CACHE_7,
-+    struct {
++    REG_DATA_CACHE_8,
-+        uint32_t gic;
++    REG_DATA_CACHE_9,
-+        uint32_t ethernet_phy[2];
++    REG_DATA_CACHE_A,
-+        uint32_t clk_125Mhz;
++    REG_DATA_CACHE_B,
-+        uint32_t clk_25Mhz;
++    REG_POWER_OUTPUT_CTRL = 0x12u,
-+    } phandle;
++    REG_DC_DC2_OUT_V_CTRL = 0x23u,
-+    struct arm_boot_info binfo;
++    REG_DC_DC2_DVS_CTRL = 0x25u,
-+
++    REG_DC_DC3_OUT_V_CTRL = 0x27u,
-+    struct {
++    REG_LDO2_4_OUT_V_CTRL,
-+        bool secure;
++    REG_LDO3_OUT_V_CTRL,
-+    } cfg;
++    REG_VBUS_CH_MGMT = 0x30u,
-+} VersalVirt;
++    REG_SHUTDOWN_V_CTRL,
-+
++    REG_SHUTDOWN_CTRL,
-+static void fdt_create(VersalVirt *s)
++    REG_CHARGE_CTRL_1,
-+{
++    REG_CHARGE_CTRL_2,
-+    MachineClass *mc = MACHINE_GET_CLASS(s);
++    REG_SPARE_CHARGE_CTRL,
-+    int i;
++    REG_PEK_KEY_CTRL,
-+
++    REG_DC_DC_FREQ_SET,
-+    s->fdt = create_device_tree(&s->fdt_size);
++    REG_CHR_TEMP_TH_SET,
-+    if (!s->fdt) {
++    REG_CHR_HIGH_TEMP_TH_CTRL,
-+        error_report("create_device_tree() failed");
++    REG_IPSOUT_WARN_L1,
-+        exit(1);
++    REG_IPSOUT_WARN_L2,
 +    REG_DISCHR_TEMP_TH_SET,
 +    REG_DISCHR_HIGH_TEMP_TH_CTRL,
 +    REG_IRQ_BANK_1_CTRL = 0x40u,
 +    REG_IRQ_BANK_2_CTRL,
 +    REG_IRQ_BANK_3_CTRL,
 +    REG_IRQ_BANK_4_CTRL,
 +    REG_IRQ_BANK_5_CTRL,
 +    REG_IRQ_BANK_1_STAT = 0x48u,
 +    REG_IRQ_BANK_2_STAT,
 +    REG_IRQ_BANK_3_STAT,
 +    REG_IRQ_BANK_4_STAT,
 +    REG_IRQ_BANK_5_STAT,
 +    REG_ADC_ACIN_V_H = 0x56u,
 +    REG_ADC_ACIN_V_L,
 +    REG_ADC_ACIN_CURR_H,
 +    REG_ADC_ACIN_CURR_L,
 +    REG_ADC_VBUS_V_H,
 +    REG_ADC_VBUS_V_L,
 +    REG_ADC_VBUS_CURR_H,
 +    REG_ADC_VBUS_CURR_L,
 +    REG_ADC_INT_TEMP_H,
 +    REG_ADC_INT_TEMP_L,
 +    REG_ADC_TEMP_SENS_V_H = 0x62u,
 +    REG_ADC_TEMP_SENS_V_L,
 +    REG_ADC_BAT_V_H = 0x78u,
 +    REG_ADC_BAT_V_L,
 +    REG_ADC_BAT_DISCHR_CURR_H,
 +    REG_ADC_BAT_DISCHR_CURR_L,
 +    REG_ADC_BAT_CHR_CURR_H,
 +    REG_ADC_BAT_CHR_CURR_L,
 +    REG_ADC_IPSOUT_V_H,
 +    REG_ADC_IPSOUT_V_L,
 +    REG_DC_DC_MOD_SEL = 0x80u,
 +    REG_ADC_EN_1,
 +    REG_ADC_EN_2,
 +    REG_ADC_SR_CTRL,
 +    REG_ADC_IN_RANGE,
 +    REG_GPIO1_ADC_IRQ_RISING_TH,
 +    REG_GPIO1_ADC_IRQ_FALLING_TH,
 +    REG_TIMER_CTRL = 0x8au,
 +    REG_VBUS_CTRL_MON_SRP,
 +    REG_OVER_TEMP_SHUTDOWN = 0x8fu,
 +    REG_GPIO0_FEAT_SET,
 +    REG_GPIO_OUT_HIGH_SET,
 +    REG_GPIO1_FEAT_SET,
 +    REG_GPIO2_FEAT_SET,
 +    REG_GPIO_SIG_STATE_SET_MON,
 +    REG_GPIO3_SET,
 +    REG_COULOMB_CNTR_CTRL = 0xb8u,
 +    REG_POWER_MEAS_RES,
 +    NR_REGS
 +};
 +
 +#define AXP209_CHIP_VERSION_ID             (0x01)
 +#define AXP209_DC_DC2_OUT_V_CTRL_RESET     (0x16)
 +#define AXP209_IRQ_BANK_1_CTRL_RESET       (0xd8)
 +
 +/* A simple I2C slave which returns values of ID or CNT register. */
 +typedef struct AXP209I2CState {
 +    /*< private >*/
 +    I2CSlave i2c;
 +    /*< public >*/
 +    uint8_t regs[NR_REGS];  /* peripheral registers */
 +    uint8_t ptr;            /* current register index */
 +    uint8_t count;          /* counter used for tx/rx */
 +} AXP209I2CState;
 +
 +/* Reset all counters and load ID register */
 +static void axp209_reset_enter(Object *obj, ResetType type)
 +{
 +    AXP209I2CState *s = AXP209(obj);
 +
 +    memset(s->regs, 0, NR_REGS);
 +    s->ptr = 0;
 +    s->count = 0;
 +    s->regs[REG_CHIP_VERSION] = AXP209_CHIP_VERSION_ID;
 +    s->regs[REG_DC_DC2_OUT_V_CTRL] = AXP209_DC_DC2_OUT_V_CTRL_RESET;
 +    s->regs[REG_IRQ_BANK_1_CTRL] = AXP209_IRQ_BANK_1_CTRL_RESET;
 +}
 +
 +/* Handle events from master. */
 +static int axp209_event(I2CSlave *i2c, enum i2c_event event)
 +{
 +    AXP209I2CState *s = AXP209(i2c);
 +
 +    s->count = 0;
 +
 +    return 0;
 +}
 +
 +/* Called when master requests read */
 +static uint8_t axp209_rx(I2CSlave *i2c)
 +{
 +    AXP209I2CState *s = AXP209(i2c);
 +    uint8_t ret = 0xff;
 +
 +    if (s->ptr < NR_REGS) {
 +        ret = s->regs[s->ptr++];
 +    }
 +
-+    /* Allocate all phandles.  */
++    trace_axp209_rx(s->ptr - 1, ret);
-+    s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt);
++
-+    for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) {
++    return ret;
-+        s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt);
++}
-+    }
++
-+    s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
++/*
-+    s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
++ * Called when master sends write.
-+
++ * Update ptr with byte 0, then perform write with second byte.
-+    /* Create /chosen node for load_dtb.  */
++ */
-+    qemu_fdt_add_subnode(s->fdt, "/chosen");
++static int axp209_tx(I2CSlave *i2c, uint8_t data)
-+
++{
-+    /* Header */
++    AXP209I2CState *s = AXP209(i2c);
-+    qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic);
++
-+    qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2);
++    if (s->count == 0) {
-+    qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2);
++        /* Store register address */
-+    qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc);
++        s->ptr = data;
-+    qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt");
++        s->count++;
-+}
++        trace_axp209_select(data);
 +
 +static void fdt_add_clk_node(VersalVirt *s, const char *name,
 +                             unsigned int freq_hz, uint32_t phandle)
 +{
 +    qemu_fdt_add_subnode(s->fdt, name);
 +    qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
 +    qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
 +    qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
 +    qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
 +    qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
 +}
 +
 +static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
 +{
 +    int i;
 +
 +    qemu_fdt_add_subnode(s->fdt, "/cpus");
 +    qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0);
 +    qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1);
 +
 +    for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
 +        char *name = g_strdup_printf("/cpus/cpu@%d", i);
 +        ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
 +
 +        qemu_fdt_add_subnode(s->fdt, name);
 +        qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
 +        if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
 +            qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
 +        }
 +        qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu");
 +        qemu_fdt_setprop_string(s->fdt, name, "compatible",
 +                                armcpu->dtb_compatible);
 +        g_free(name);
 +    }
 +}
 +
 +static void fdt_add_gic_nodes(VersalVirt *s)
 +{
 +    char *nodename;
 +
 +    nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN);
 +    qemu_fdt_add_subnode(s->fdt, nodename);
 +    qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic);
 +    qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts",
 +                           GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ,
 +                           GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 +    qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0);
 +    qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
 +                                 2, MM_GIC_APU_DIST_MAIN,
 +                                 2, MM_GIC_APU_DIST_MAIN_SIZE,
 +                                 2, MM_GIC_APU_REDIST_0,
 +                                 2, MM_GIC_APU_REDIST_0_SIZE);
 +    qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3);
 +    qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3");
 +}
 +
 +static void fdt_add_timer_nodes(VersalVirt *s)
 +{
 +    const char compat[] = "arm,armv8-timer";
 +    uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
 +
 +    qemu_fdt_add_subnode(s->fdt, "/timer");
 +    qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts",
 +            GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags,
 +            GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags,
 +            GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags,
 +            GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags);
 +    qemu_fdt_setprop(s->fdt, "/timer", "compatible",
 +                     compat, sizeof(compat));
 +}
 +
 +static void fdt_add_uart_nodes(VersalVirt *s)
 +{
 +    uint64_t addrs[] = { MM_UART1, MM_UART0 };
 +    unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 };
 +    const char compat[] = "arm,pl011\0arm,sbsa-uart";
 +    const char clocknames[] = "uartclk\0apb_pclk";
 +    int i;
 +
 +    for (i = 0; i < ARRAY_SIZE(addrs); i++) {
 +        char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]);
 +        qemu_fdt_add_subnode(s->fdt, name);
 +        qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200);
 +        qemu_fdt_setprop_cells(s->fdt, name, "clocks",
 +                               s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
 +        qemu_fdt_setprop(s->fdt, name, "clock-names",
 +                         clocknames, sizeof(clocknames));
 +
 +        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 +                               GIC_FDT_IRQ_TYPE_SPI, irqs[i],
 +                               GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 +        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 +                                     2, addrs[i], 2, 0x1000);
 +        qemu_fdt_setprop(s->fdt, name, "compatible",
 +                         compat, sizeof(compat));
 +        qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
 +
 +        if (addrs[i] == MM_UART0) {
 +            /* Select UART0.  */
 +            qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name);
 +        }
 +        g_free(name);
 +    }
 +}
 +
 +static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname,
 +                                     uint32_t phandle)
 +{
 +    char *name = g_strdup_printf("%s/fixed-link", gemname);
 +
 +    qemu_fdt_add_subnode(s->fdt, name);
 +    qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
 +    qemu_fdt_setprop_cells(s->fdt, name, "full-duplex");
 +    qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000);
 +    g_free(name);
 +}
 +
 +static void fdt_add_gem_nodes(VersalVirt *s)
 +{
 +    uint64_t addrs[] = { MM_GEM1, MM_GEM0 };
 +    unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 };
 +    const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk";
 +    const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem";
 +    int i;
 +
 +    for (i = 0; i < ARRAY_SIZE(addrs); i++) {
 +        char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]);
 +        qemu_fdt_add_subnode(s->fdt, name);
 +
 +        fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]);
 +        qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id");
 +        qemu_fdt_setprop_cell(s->fdt, name, "phy-handle",
 +                              s->phandle.ethernet_phy[i]);
 +        qemu_fdt_setprop_cells(s->fdt, name, "clocks",
 +                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
 +                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
 +        qemu_fdt_setprop(s->fdt, name, "clock-names",
 +                         clocknames, sizeof(clocknames));
 +        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 +                               GIC_FDT_IRQ_TYPE_SPI, irqs[i],
 +                               GIC_FDT_IRQ_FLAGS_LEVEL_HI,
 +                               GIC_FDT_IRQ_TYPE_SPI, irqs[i],
 +                               GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 +        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 +                                     2, addrs[i], 2, 0x1000);
 +        qemu_fdt_setprop(s->fdt, name, "compatible",
 +                         compat_gem, sizeof(compat_gem));
 +        qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1);
 +        qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0);
 +        g_free(name);
 +    }
 +}
 +
 +static void fdt_nop_memory_nodes(void *fdt, Error **errp)
 +{
 +    Error *err = NULL;
 +    char **node_path;
 +    int n = 0;
 +
 +    node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
 +    if (err) {
 +        error_propagate(errp, err);
 +        return;
 +    }
 +    while (node_path[n]) {
 +        if (g_str_has_prefix(node_path[n], "/memory")) {
 +            qemu_fdt_nop_node(fdt, node_path[n]);
 +        }
 +        n++;
 +    }
 +    g_strfreev(node_path);
 +}
 +
 +static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size)
 +{
 +    /* Describes the various split DDR access regions.  */
 +    static const struct {
 +        uint64_t base;
 +        uint64_t size;
 +    } addr_ranges[] = {
 +        { MM_TOP_DDR, MM_TOP_DDR_SIZE },
 +        { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
 +        { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
 +        { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
 +    };
 +    uint64_t mem_reg_prop[8] = {0};
 +    uint64_t size = ram_size;
 +    Error *err = NULL;
 +    char *name;
 +    int i;
 +
 +    fdt_nop_memory_nodes(fdt, &err);
 +    if (err) {
 +        error_report_err(err);
 +        return;
 +    }
 +
 +    name = g_strdup_printf("/memory@%x", MM_TOP_DDR);
 +    for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
 +        uint64_t mapsize;
 +
 +        mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
 +
 +        mem_reg_prop[i * 2] = addr_ranges[i].base;
 +        mem_reg_prop[i * 2 + 1] = mapsize;
 +        size -= mapsize;
 +    }
 +    qemu_fdt_add_subnode(fdt, name);
 +    qemu_fdt_setprop_string(fdt, name, "device_type", "memory");
 +
 +    switch (i) {
 +    case 1:
 +        qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 +                                     2, mem_reg_prop[0],
 +                                     2, mem_reg_prop[1]);
 +        break;
 +    case 2:
 +        qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 +                                     2, mem_reg_prop[0],
 +                                     2, mem_reg_prop[1],
 +                                     2, mem_reg_prop[2],
 +                                     2, mem_reg_prop[3]);
 +        break;
 +    case 3:
 +        qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 +                                     2, mem_reg_prop[0],
 +                                     2, mem_reg_prop[1],
 +                                     2, mem_reg_prop[2],
 +                                     2, mem_reg_prop[3],
 +                                     2, mem_reg_prop[4],
 +                                     2, mem_reg_prop[5]);
 +        break;
 +    case 4:
 +        qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 +                                     2, mem_reg_prop[0],
 +                                     2, mem_reg_prop[1],
 +                                     2, mem_reg_prop[2],
 +                                     2, mem_reg_prop[3],
 +                                     2, mem_reg_prop[4],
 +                                     2, mem_reg_prop[5],
 +                                     2, mem_reg_prop[6],
 +                                     2, mem_reg_prop[7]);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +    g_free(name);
 +}
 +
 +static void versal_virt_modify_dtb(const struct arm_boot_info *binfo,
 +                                    void *fdt)
 +{
 +    VersalVirt *s = container_of(binfo, VersalVirt, binfo);
 +
 +    fdt_add_memory_nodes(s, fdt, binfo->ram_size);
 +}
 +
 +static void *versal_virt_get_dtb(const struct arm_boot_info *binfo,
 +                                  int *fdt_size)
 +{
 +    const VersalVirt *board = container_of(binfo, VersalVirt, binfo);
 +
 +    *fdt_size = board->fdt_size;
 +    return board->fdt;
 +}
 +
 +#define NUM_VIRTIO_TRANSPORT 32
 +static void create_virtio_regions(VersalVirt *s)
 +{
 +    int virtio_mmio_size = 0x200;
 +    int i;
 +
 +    for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
 +        char *name = g_strdup_printf("virtio%d", i);;
 +        hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
 +        int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i;
 +        MemoryRegion *mr;
 +        DeviceState *dev;
 +        qemu_irq pic_irq;
 +
 +        pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
 +        dev = qdev_create(NULL, "virtio-mmio");
 +        object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev),
 +                                  &error_fatal);
 +        qdev_init_nofail(dev);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
 +        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 +        memory_region_add_subregion(&s->soc.mr_ps, base, mr);
 +        sysbus_create_simple("virtio-mmio", base, pic_irq);
 +    }
 +
 +    for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
 +        hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
 +        int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i;
 +        char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
 +
 +        qemu_fdt_add_subnode(s->fdt, name);
 +        qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0);
 +        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 +                               GIC_FDT_IRQ_TYPE_SPI, irq,
 +                               GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
 +        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 +                                     2, base, 2, virtio_mmio_size);
 +        qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio");
 +        g_free(name);
 +    }
 +}
 +
 +static void versal_virt_init(MachineState *machine)
 +{
 +    VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
 +    int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
 +
 +    /*
 +     * If the user provides an Operating System to be loaded, we expect them
 +     * to use the -kernel command line option.
 +     *
 +     * Users can load firmware or boot-loaders with the -device loader options.
 +     *
 +     * When loading an OS, we generate a dtb and let arm_load_kernel() select
 +     * where it gets loaded. This dtb will be passed to the kernel in x0.
 +     *
 +     * If there's no -kernel option, we generate a DTB and place it at 0x1000
 +     * for the bootloaders or firmware to pick up.
 +     *
 +     * If users want to provide their own DTB, they can use the -dtb option.
 +     * These dtb's will have their memory nodes modified to match QEMU's
 +     * selected ram_size option before they get passed to the kernel or fw.
 +     *
 +     * When loading an OS, we turn on QEMU's PSCI implementation with SMC
 +     * as the PSCI conduit. When there's no -kernel, we assume the user
 +     * provides EL3 firmware to handle PSCI.
 +     */
 +    if (machine->kernel_filename) {
 +        psci_conduit = QEMU_PSCI_CONDUIT_SMC;
 +    }
 +
 +    memory_region_allocate_system_memory(&s->mr_ddr, NULL, "ddr",
 +                                         machine->ram_size);
 +
 +    sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
 +                          sizeof(s->soc), TYPE_XLNX_VERSAL);
 +    object_property_set_link(OBJECT(&s->soc), OBJECT(&s->mr_ddr),
 +                             "ddr", &error_abort);
 +    object_property_set_int(OBJECT(&s->soc), psci_conduit,
 +                            "psci-conduit", &error_abort);
 +    object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
 +
 +    fdt_create(s);
 +    create_virtio_regions(s);
 +    fdt_add_gem_nodes(s);
 +    fdt_add_uart_nodes(s);
 +    fdt_add_gic_nodes(s);
 +    fdt_add_timer_nodes(s);
 +    fdt_add_cpu_nodes(s, psci_conduit);
 +    fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
 +    fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
 +
 +    /* Make the APU cpu address space visible to virtio and other
 +     * modules unaware of muliple address-spaces.  */
 +    memory_region_add_subregion_overlap(get_system_memory(),
 +                                        0, &s->soc.fpd.apu.mr, 0);
 +
 +    s->binfo.ram_size = machine->ram_size;
 +    s->binfo.kernel_filename = machine->kernel_filename;
 +    s->binfo.kernel_cmdline = machine->kernel_cmdline;
 +    s->binfo.initrd_filename = machine->initrd_filename;
 +    s->binfo.loader_start = 0x0;
 +    s->binfo.get_dtb = versal_virt_get_dtb;
 +    s->binfo.modify_dtb = versal_virt_modify_dtb;
 +    if (machine->kernel_filename) {
 +        arm_load_kernel(s->soc.fpd.apu.cpu[0], &s->binfo);
 +    } else {
-+        AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
++        trace_axp209_tx(s->ptr, data);
-+                                                  &s->binfo);
++        if (s->ptr == REG_DC_DC2_OUT_V_CTRL) {
-+        /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
++            s->regs[s->ptr++] = data;
 +         * Offset things by 4K.  */
 +        s->binfo.loader_start = 0x1000;
 +        s->binfo.dtb_limit = 0x1000000;
 +        if (arm_load_dtb(s->binfo.loader_start,
 +                         &s->binfo, s->binfo.dtb_limit, as) < 0) {
 +            exit(EXIT_FAILURE);
 +        }
 +    }
-+}
++
-+
++    return 0;
-+static void versal_virt_machine_instance_init(Object *obj)
++}
-+{
++
-+}
++static const VMStateDescription vmstate_axp209 = {
-+
++    .name = TYPE_AXP209_PMU,
-+static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
++    .version_id = 1,
-+{
++    .fields = (VMStateField[]) {
-+    MachineClass *mc = MACHINE_CLASS(oc);
++        VMSTATE_UINT8_ARRAY(regs, AXP209I2CState, NR_REGS),
-+
++        VMSTATE_UINT8(count, AXP209I2CState),
-+    mc->desc = "Xilinx Versal Virtual development board";
++        VMSTATE_UINT8(ptr, AXP209I2CState),
-+    mc->init = versal_virt_init;
++        VMSTATE_END_OF_LIST()
-+    mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
++    }
 +    mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
 +    mc->no_cdrom = true;
 +}
 +
 +static const TypeInfo versal_virt_machine_init_typeinfo = {
 +    .name       = TYPE_XLNX_VERSAL_VIRT_MACHINE,
 +    .parent     = TYPE_MACHINE,
 +    .class_init = versal_virt_machine_class_init,
 +    .instance_init = versal_virt_machine_instance_init,
 +    .instance_size = sizeof(VersalVirt),
 +};
 +
-+static void versal_virt_machine_init_register_types(void)
++static void axp209_class_init(ObjectClass *oc, void *data)
 +{
-+    type_register_static(&versal_virt_machine_init_typeinfo);
++    DeviceClass *dc = DEVICE_CLASS(oc);
-+}
++    I2CSlaveClass *isc = I2C_SLAVE_CLASS(oc);
-+
++    ResettableClass *rc = RESETTABLE_CLASS(oc);
-+type_init(versal_virt_machine_init_register_types)
++
 +    rc->phases.enter = axp209_reset_enter;
 +    dc->vmsd = &vmstate_axp209;
 +    isc->event = axp209_event;
 +    isc->recv = axp209_rx;
 +    isc->send = axp209_tx;
 +}
 +
 +static const TypeInfo axp209_info = {
 +    .name = TYPE_AXP209_PMU,
 +    .parent = TYPE_I2C_SLAVE,
 +    .instance_size = sizeof(AXP209I2CState),
 +    .class_init = axp209_class_init
 +};
 +
 +static void axp209_register_devices(void)
 +{
 +    type_register_static(&axp209_info);
 +}
 +
 +type_init(axp209_register_devices);
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ ARM Machines
  Allwinner-a10
  M: Beniamino Galvani <b.galvani@gmail.com>
  M: Peter Maydell <peter.maydell@linaro.org>
 +R: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
  L: qemu-arm@nongnu.org
  S: Odd Fixes
  F: hw/*/allwinner*
  F: include/hw/*/allwinner*
  F: hw/arm/cubieboard.c
  F: docs/system/arm/cubieboard.rst
 +F: hw/misc/axp209.c
  Allwinner-h3
  M: Niek Linnenbank <nieklinnenbank@gmail.com>
 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10_CCM
  config ALLWINNER_A10_DRAMC
      bool
 +config AXP209_PMU
 +    bool
 +    depends on I2C
 +
  source macio/Kconfig
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'
  softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
  softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-sysctrl.c'))
  softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sid.c'))
 +softmmu_ss.add(when: 'CONFIG_AXP209_PMU', if_true: files('axp209.c'))
  softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
  softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c'))
  softmmu_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c'))
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%"
  avr_power_read(uint8_t value) "power_reduc read value:%u"
  avr_power_write(uint8_t value) "power_reduc write value:%u"
 +# axp209.c
 +axp209_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
 +axp209_select(uint8_t reg) "Accessing reg 0x%" PRIx8
 +axp209_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
 +
  # eccmemctl.c
  ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
  ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
 --
-.19.1
+.34.1

-New patch
+[PULL 07/38] hw/arm: Add AXP209 to Cubieboard
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
+SPL Boot for Cubieboard expects AXP209 connected to I2C0 bus.
+Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20221226220303.14420-6-strahinja.p.jankovic@gmail.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/cubieboard.c | 6 ++++++
+ hw/arm/Kconfig      | 1 +
+files changed, 7 insertions(+)
+diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/cubieboard.c
++++ b/hw/arm/cubieboard.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/boards.h"
+ #include "hw/qdev-properties.h"
+ #include "hw/arm/allwinner-a10.h"
++#include "hw/i2c/i2c.h"
+ static struct arm_boot_info cubieboard_binfo = {
+     .loader_start = AW_A10_SDRAM_BASE,
+@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
+     BlockBackend *blk;
+     BusState *bus;
+     DeviceState *carddev;
++    I2CBus *i2c;
+     /* BIOS is not supported by this board */
+     if (machine->firmware) {
+@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
+         exit(1);
+     }
++    /* Connect AXP 209 */
++    i2c = I2C_BUS(qdev_get_child_bus(DEVICE(&a10->i2c0), "i2c"));
++    i2c_slave_create_simple(i2c, "axp209_pmu", 0x34);
++
+     /* Retrieve SD bus */
+     di = drive_get(IF_SD, 0, 0);
+     blk = di ? blk_by_legacy_dinfo(di) : NULL;
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/Kconfig
++++ b/hw/arm/Kconfig
+@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
+     select ALLWINNER_A10_DRAMC
+     select ALLWINNER_EMAC
+     select ALLWINNER_I2C
++    select AXP209_PMU
+     select SERIAL
+     select UNIMP
+--
+.34.1

-New patch
+[PULL 08/38] hw/arm: Allwinner A10 enable SPL load from MMC
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
+This patch enables copying of SPL from MMC if `-kernel` parameter is not
+passed when starting QEMU. SPL is copied to SRAM_A.
+The approach is reused from Allwinner H3 implementation.
+Tested with Armbian and custom Yocto image.
+Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
+Message-id: 20221226220303.14420-7-strahinja.p.jankovic@gmail.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/allwinner-a10.h | 21 +++++++++++++++++++++
+ hw/arm/allwinner-a10.c         | 18 ++++++++++++++++++
+ hw/arm/cubieboard.c            |  5 +++++
+files changed, 44 insertions(+)
+diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/allwinner-a10.h
++++ b/include/hw/arm/allwinner-a10.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/misc/allwinner-a10-ccm.h"
+ #include "hw/misc/allwinner-a10-dramc.h"
+ #include "hw/i2c/allwinner-i2c.h"
++#include "sysemu/block-backend.h"
+ #include "target/arm/cpu.h"
+ #include "qom/object.h"
+@@ -XXX,XX +XXX,XX @@ struct AwA10State {
+     OHCISysBusState ohci[AW_A10_NUM_USB];
+ };
++/**
++ * Emulate Boot ROM firmware setup functionality.
++ *
++ * A real Allwinner A10 SoC contains a Boot ROM
++ * which is the first code that runs right after
++ * the SoC is powered on. The Boot ROM is responsible
++ * for loading user code (e.g. a bootloader) from any
++ * of the supported external devices and writing the
++ * downloaded code to internal SRAM. After loading the SoC
++ * begins executing the code written to SRAM.
++ *
++ * This function emulates the Boot ROM by copying 32 KiB
++ * of data at offset 8 KiB from the given block device and writes it to
++ * the start of the first internal SRAM memory.
++ *
++ * @s: Allwinner A10 state object pointer
++ * @blk: Block backend device object pointer
++ */
++void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk);
++
+ #endif
+diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/allwinner-a10.c
++++ b/hw/arm/allwinner-a10.c
+@@ -XXX,XX +XXX,XX @@
+ #include "sysemu/sysemu.h"
+ #include "hw/boards.h"
+ #include "hw/usb/hcd-ohci.h"
++#include "hw/loader.h"
++#define AW_A10_SRAM_A_BASE      0x00000000
+ #define AW_A10_DRAMC_BASE       0x01c01000
+ #define AW_A10_MMC0_BASE        0x01c0f000
+ #define AW_A10_CCM_BASE         0x01c20000
+@@ -XXX,XX +XXX,XX @@
+ #define AW_A10_RTC_BASE         0x01c20d00
+ #define AW_A10_I2C0_BASE        0x01c2ac00
++void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
++{
++    const int64_t rom_size = 32 * KiB;
++    g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
++
++    if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
++        error_setg(&error_fatal, "%s: failed to read BlockBackend data",
++                   __func__);
++        return;
++    }
++
++    rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
++                  rom_size, AW_A10_SRAM_A_BASE,
++                  NULL, NULL, NULL, NULL, false);
++}
++
+ static void aw_a10_init(Object *obj)
+ {
+     AwA10State *s = AW_A10(obj);
+diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/cubieboard.c
++++ b/hw/arm/cubieboard.c
+@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
+     memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
+                                 machine->ram);
++    /* Load target kernel or start using BootROM */
++    if (!machine->kernel_filename && blk && blk_is_available(blk)) {
++        /* Use Boot ROM to copy data from SD card to SRAM */
++        allwinner_a10_bootrom_setup(a10, blk);
++    }
+     /* TODO create and connect IDE devices for ide_drive_get() */
+     cubieboard_binfo.ram_size = machine->ram_size;
+--
+.34.1

-New patch
+[PULL 09/38] tests/avocado: Add SD boot test to Cubieboard
+From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
+Cubieboard now can boot directly from SD card, without the need to pass
+`-kernel` parameter. Update Avocado tests to cover this functionality.
+Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
+Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
+Message-id: 20221226220303.14420-8-strahinja.p.jankovic@gmail.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/avocado/boot_linux_console.py | 47 +++++++++++++++++++++++++++++
+file changed, 47 insertions(+)
+diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/avocado/boot_linux_console.py
++++ b/tests/avocado/boot_linux_console.py
+@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
+                                                 'sda')
+         # cubieboard's reboot is not functioning; omit reboot test.
++    @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
++    def test_arm_cubieboard_openwrt_22_03_2(self):
++        """
++        :avocado: tags=arch:arm
++        :avocado: tags=machine:cubieboard
++        :avocado: tags=device:sd
++        """
++
++        # This test download a 7.5 MiB compressed image and expand it
++        # to 126 MiB.
++        image_url = ('https://downloads.openwrt.org/releases/22.03.2/targets/'
++                     'sunxi/cortexa8/openwrt-22.03.2-sunxi-cortexa8-'
++                     'cubietech_a10-cubieboard-ext4-sdcard.img.gz')
++        image_hash = ('94b5ecbfbc0b3b56276e5146b899eafa'
++                      '2ac5dc2d08733d6705af9f144f39f554')
++        image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash,
++                                         algorithm='sha256')
++        image_path = archive.extract(image_path_gz, self.workdir)
++        image_pow2ceil_expand(image_path)
++
++        self.vm.set_console()
++        self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
++                         '-nic', 'user',
++                         '-no-reboot')
++        self.vm.launch()
++
++        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
++                               'usbcore.nousb '
++                               'noreboot')
++
++        self.wait_for_console_pattern('U-Boot SPL')
++
++        interrupt_interactive_console_until_pattern(
++                self, 'Hit any key to stop autoboot:', '=>')
++        exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
++                                                kernel_command_line + "'", '=>')
++        exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
++
++        self.wait_for_console_pattern(
++            'Please press Enter to activate this console.')
++
++        exec_command_and_wait_for_pattern(self, ' ', 'root@')
++
++        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
++                                                'Allwinner sun4i/sun5i')
++        # cubieboard's reboot is not functioning; omit reboot test.
++
+     @skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout')
+     def test_arm_quanta_gsj(self):
+         """
+--
+.34.1

-New patch
+[PULL 10/38] target/arm: Fix sve_probe_page
+From: Richard Henderson <richard.henderson@linaro.org>
+Don't dereference CPUTLBEntryFull until we verify that
+the page is valid.  Move the other user-only info field
+updates after the valid check to match.
+Cc: qemu-stable@nongnu.org
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1412
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230104190056.305143-1-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/sve_helper.c | 14 +++++++++-----
+file changed, 9 insertions(+), 5 deletions(-)
+diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/sve_helper.c
++++ b/target/arm/sve_helper.c
+@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
+ #ifdef CONFIG_USER_ONLY
+     flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
+                                &info->host, retaddr);
+-    memset(&info->attrs, 0, sizeof(info->attrs));
+-    /* Require both ANON and MTE; see allocation_tag_mem(). */
+-    info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
+ #else
+     CPUTLBEntryFull *full;
+     flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
+                               &info->host, &full, retaddr);
+-    info->attrs = full->attrs;
+-    info->tagged = full->pte_attrs == 0xf0;
+ #endif
+     info->flags = flags;
+@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
+         return false;
+     }
++#ifdef CONFIG_USER_ONLY
++    memset(&info->attrs, 0, sizeof(info->attrs));
++    /* Require both ANON and MTE; see allocation_tag_mem(). */
++    info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
++#else
++    info->attrs = full->attrs;
++    info->tagged = full->pte_attrs == 0xf0;
++#endif
++
+     /* Ensure that info->host[] is relative to addr, not addr + mem_off. */
+     info->host -= mem_off;
+     return true;
+--
+.34.1

-New patch
+[PULL 11/38] hw/arm/pxa2xx: Simplify pxa255_init()
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Since pxa255_init() must map the device in the system memory,
+there is no point in passing get_system_memory() by argument.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-2-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/pxa.h | 2 +-
+ hw/arm/gumstix.c     | 3 +--
+ hw/arm/pxa2xx.c      | 4 +++-
+ hw/arm/tosa.c        | 2 +-
+files changed, 6 insertions(+), 5 deletions(-)
+diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/pxa.h
++++ b/include/hw/arm/pxa.h
+@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
+ PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
+                          const char *revision);
+-PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
++PXA2xxState *pxa255_init(unsigned int sdram_size);
+ #endif /* PXA_H */
+diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/gumstix.c
++++ b/hw/arm/gumstix.c
+@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
+ {
+     PXA2xxState *cpu;
+     DriveInfo *dinfo;
+-    MemoryRegion *address_space_mem = get_system_memory();
+     uint32_t connex_rom = 0x01000000;
+     uint32_t connex_ram = 0x04000000;
+-    cpu = pxa255_init(address_space_mem, connex_ram);
++    cpu = pxa255_init(connex_ram);
+     dinfo = drive_get(IF_PFLASH, 0, 0);
+     if (!dinfo && !qtest_enabled()) {
+diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/pxa2xx.c
++++ b/hw/arm/pxa2xx.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/error-report.h"
+ #include "qemu/module.h"
+ #include "qapi/error.h"
++#include "exec/address-spaces.h"
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+ #include "migration/vmstate.h"
+@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
+ }
+ /* Initialise a PXA255 integrated chip (ARM based core).  */
+-PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
++PXA2xxState *pxa255_init(unsigned int sdram_size)
+ {
++    MemoryRegion *address_space = get_system_memory();
+     PXA2xxState *s;
+     int i;
+     DriveInfo *dinfo;
+diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/tosa.c
++++ b/hw/arm/tosa.c
+@@ -XXX,XX +XXX,XX @@ static void tosa_init(MachineState *machine)
+     TC6393xbState *tmio;
+     DeviceState *scp0, *scp1;
+-    mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
++    mpu = pxa255_init(tosa_binfo.ram_size);
+     memory_region_init_rom(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal);
+     memory_region_add_subregion(address_space_mem, 0, rom);
+--
+.34.1

-New patch
+[PULL 12/38] hw/arm/pxa2xx: Simplify pxa270_init()
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Since pxa270_init() must map the device in the system memory,
+there is no point in passing get_system_memory() by argument.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-3-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/pxa.h |  3 +--
+ hw/arm/gumstix.c     |  3 +--
+ hw/arm/mainstone.c   | 10 ++++------
+ hw/arm/pxa2xx.c      |  4 ++--
+ hw/arm/spitz.c       |  6 ++----
+ hw/arm/z2.c          |  3 +--
+files changed, 11 insertions(+), 18 deletions(-)
+diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/pxa.h
++++ b/include/hw/arm/pxa.h
+@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
+ # define PA_FMT            "0x%08lx"
+-PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
+-                         const char *revision);
++PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
+ PXA2xxState *pxa255_init(unsigned int sdram_size);
+ #endif /* PXA_H */
+diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/gumstix.c
++++ b/hw/arm/gumstix.c
+@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
+ {
+     PXA2xxState *cpu;
+     DriveInfo *dinfo;
+-    MemoryRegion *address_space_mem = get_system_memory();
+     uint32_t verdex_rom = 0x02000000;
+     uint32_t verdex_ram = 0x10000000;
+-    cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);
++    cpu = pxa270_init(verdex_ram, machine->cpu_type);
+     dinfo = drive_get(IF_PFLASH, 0, 0);
+     if (!dinfo && !qtest_enabled()) {
+diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/mainstone.c
++++ b/hw/arm/mainstone.c
+@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info mainstone_binfo = {
+     .ram_size = 0x04000000,
+ };
+-static void mainstone_common_init(MemoryRegion *address_space_mem,
+-                                  MachineState *machine,
++static void mainstone_common_init(MachineState *machine,
+                                   enum mainstone_model_e model, int arm_id)
+ {
+     uint32_t sector_len = 256 * 1024;
+@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
+     MemoryRegion *rom = g_new(MemoryRegion, 1);
+     /* Setup CPU & memory */
+-    mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
+-                      machine->cpu_type);
++    mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
+     memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
+                            &error_fatal);
+-    memory_region_add_subregion(address_space_mem, 0, rom);
++    memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
+     /* There are two 32MiB flash devices on the board */
+     for (i = 0; i < 2; i ++) {
+@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
+ static void mainstone_init(MachineState *machine)
+ {
+-    mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
++    mainstone_common_init(machine, mainstone, 0x196);
+ }
+ static void mainstone2_machine_init(MachineClass *mc)
+diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/pxa2xx.c
++++ b/hw/arm/pxa2xx.c
+@@ -XXX,XX +XXX,XX @@ static void pxa2xx_reset(void *opaque, int line, int level)
+ }
+ /* Initialise a PXA270 integrated chip (ARM based core).  */
+-PXA2xxState *pxa270_init(MemoryRegion *address_space,
+-                         unsigned int sdram_size, const char *cpu_type)
++PXA2xxState *pxa270_init(unsigned int sdram_size, const char *cpu_type)
+ {
++    MemoryRegion *address_space = get_system_memory();
+     PXA2xxState *s;
+     int i;
+     DriveInfo *dinfo;
+diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/spitz.c
++++ b/hw/arm/spitz.c
+@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
+     SpitzMachineState *sms = SPITZ_MACHINE(machine);
+     enum spitz_model_e model = smc->model;
+     PXA2xxState *mpu;
+-    MemoryRegion *address_space_mem = get_system_memory();
+     MemoryRegion *rom = g_new(MemoryRegion, 1);
+     /* Setup CPU & memory */
+-    mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
+-                      machine->cpu_type);
++    mpu = pxa270_init(spitz_binfo.ram_size, machine->cpu_type);
+     sms->mpu = mpu;
+     sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
+     memory_region_init_rom(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal);
+-    memory_region_add_subregion(address_space_mem, 0, rom);
++    memory_region_add_subregion(get_system_memory(), 0, rom);
+     /* Setup peripherals */
+     spitz_keyboard_register(mpu);
+diff --git a/hw/arm/z2.c b/hw/arm/z2.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/z2.c
++++ b/hw/arm/z2.c
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo aer915_info = {
+ static void z2_init(MachineState *machine)
+ {
+-    MemoryRegion *address_space_mem = get_system_memory();
+     uint32_t sector_len = 0x10000;
+     PXA2xxState *mpu;
+     DriveInfo *dinfo;
+@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
+     DeviceState *wm;
+     /* Setup CPU & memory */
+-    mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);
++    mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type);
+     dinfo = drive_get(IF_PFLASH, 0, 0);
+     if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
+--
+.34.1

-New patch
+[PULL 13/38] hw/arm/collie: Use the IEC binary prefix definitions
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+IEC binary prefixes ease code review: the unit is explicit.
+Add definitions for RAM / Flash / Flash blocksize.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-4-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/collie.c | 16 ++++++++++------
+file changed, 10 insertions(+), 6 deletions(-)
+diff --git a/hw/arm/collie.c b/hw/arm/collie.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/collie.c
++++ b/hw/arm/collie.c
+@@ -XXX,XX +XXX,XX @@
+ #include "cpu.h"
+ #include "qom/object.h"
++#define RAM_SIZE            (512 * MiB)
++#define FLASH_SIZE          (32 * MiB)
++#define FLASH_SECTOR_SIZE   (64 * KiB)
++
+ struct CollieMachineState {
+     MachineState parent;
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(CollieMachineState, COLLIE_MACHINE)
+ static struct arm_boot_info collie_binfo = {
+     .loader_start = SA_SDCS0,
+-    .ram_size = 0x20000000,
++    .ram_size = RAM_SIZE,
+ };
+ static void collie_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
+     memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
+     dinfo = drive_get(IF_PFLASH, 0, 0);
+-    pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000,
++    pflash_cfi01_register(SA_CS0, "collie.fl1", FLASH_SIZE,
+                     dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                    64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
++                    FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
+     dinfo = drive_get(IF_PFLASH, 0, 1);
+-    pflash_cfi01_register(SA_CS1, "collie.fl2", 0x02000000,
++    pflash_cfi01_register(SA_CS1, "collie.fl2", FLASH_SIZE,
+                     dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                    64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
++                    FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
+     sysbus_create_simple("scoop", 0x40800000, NULL);
+@@ -XXX,XX +XXX,XX @@ static void collie_machine_class_init(ObjectClass *oc, void *data)
+     mc->init = collie_init;
+     mc->ignore_memory_transaction_failures = true;
+     mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110");
+-    mc->default_ram_size = 0x20000000;
++    mc->default_ram_size = RAM_SIZE;
+     mc->default_ram_id = "strongarm.sdram";
+ }
+--
+.34.1

-New patch
+[PULL 14/38] hw/arm/collie: Simplify flash creation using for() loop
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-5-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/collie.c | 17 +++++++----------
+file changed, 7 insertions(+), 10 deletions(-)
+diff --git a/hw/arm/collie.c b/hw/arm/collie.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/collie.c
++++ b/hw/arm/collie.c
+@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info collie_binfo = {
+ static void collie_init(MachineState *machine)
+ {
+-    DriveInfo *dinfo;
+     MachineClass *mc = MACHINE_GET_CLASS(machine);
+     CollieMachineState *cms = COLLIE_MACHINE(machine);
+@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
+     memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
+-    dinfo = drive_get(IF_PFLASH, 0, 0);
+-    pflash_cfi01_register(SA_CS0, "collie.fl1", FLASH_SIZE,
+-                    dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                    FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
+-
+-    dinfo = drive_get(IF_PFLASH, 0, 1);
+-    pflash_cfi01_register(SA_CS1, "collie.fl2", FLASH_SIZE,
+-                    dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                    FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
++    for (unsigned i = 0; i < 2; i++) {
++        DriveInfo *dinfo = drive_get(IF_PFLASH, 0, i);
++        pflash_cfi01_register(i ? SA_CS1 : SA_CS0,
++                              i ? "collie.fl2" : "collie.fl1", FLASH_SIZE,
++                              dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
++                              FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
++    }
+     sysbus_create_simple("scoop", 0x40800000, NULL);
+--
+.34.1

-New patch
+[PULL 15/38] hw/arm/gumstix: Improve documentation
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Add a comment describing the Connex uses a Numonyx RC28F128J3F75
+flash, and the Verdex uses a Micron RC28F256P30TFA.
+Correct the Verdex machine description (we model the 'Pro' board).
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-6-philmd@linaro.org
+Message-Id: <20200223231044.8003-3-philmd@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/gumstix.c | 6 ++++--
+file changed, 4 insertions(+), 2 deletions(-)
+diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/gumstix.c
++++ b/hw/arm/gumstix.c
+@@ -XXX,XX +XXX,XX @@
+  * Contributions after 2012-01-13 are licensed under the terms of the
+  * GNU GPL, version 2 or (at your option) any later version.
+  */
+-
++
+ /*
+  * Example usage:
+  *
+@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
+         exit(1);
+     }
++    /* Numonyx RC28F128J3F75 */
+     if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom,
+                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+                                sector_len, 2, 0, 0, 0, 0, 0)) {
+@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
+         exit(1);
+     }
++    /* Micron RC28F256P30TFA */
+     if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom,
+                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+                                sector_len, 2, 0, 0, 0, 0, 0)) {
+@@ -XXX,XX +XXX,XX @@ static void verdex_class_init(ObjectClass *oc, void *data)
+ {
+     MachineClass *mc = MACHINE_CLASS(oc);
+-    mc->desc = "Gumstix Verdex (PXA270)";
++    mc->desc = "Gumstix Verdex Pro XL6P COMs (PXA270)";
+     mc->init = verdex_init;
+     mc->ignore_memory_transaction_failures = true;
+     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
+--
+.34.1

-New patch
+[PULL 16/38] hw/arm/gumstix: Use the IEC binary prefix definitions
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+IEC binary prefixes ease code review: the unit is explicit.
+Add definitions for RAM / Flash / Flash blocksize.
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-7-philmd@linaro.org
+Message-Id: <20200223231044.8003-3-philmd@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/gumstix.c | 27 ++++++++++++++-------------
+file changed, 14 insertions(+), 13 deletions(-)
+diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/gumstix.c
++++ b/hw/arm/gumstix.c
+@@ -XXX,XX +XXX,XX @@
+  */
+ #include "qemu/osdep.h"
++#include "qemu/units.h"
+ #include "qemu/error-report.h"
+ #include "hw/arm/pxa.h"
+ #include "net/net.h"
+@@ -XXX,XX +XXX,XX @@
+ #include "sysemu/qtest.h"
+ #include "cpu.h"
+-static const int sector_len = 128 * 1024;
++#define CONNEX_FLASH_SIZE   (16 * MiB)
++#define CONNEX_RAM_SIZE     (64 * MiB)
++
++#define VERDEX_FLASH_SIZE   (32 * MiB)
++#define VERDEX_RAM_SIZE     (256 * MiB)
++
++#define FLASH_SECTOR_SIZE   (128 * KiB)
+ static void connex_init(MachineState *machine)
+ {
+     PXA2xxState *cpu;
+     DriveInfo *dinfo;
+-    uint32_t connex_rom = 0x01000000;
+-    uint32_t connex_ram = 0x04000000;
+-
+-    cpu = pxa255_init(connex_ram);
++    cpu = pxa255_init(CONNEX_RAM_SIZE);
+     dinfo = drive_get(IF_PFLASH, 0, 0);
+     if (!dinfo && !qtest_enabled()) {
+@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
+     }
+     /* Numonyx RC28F128J3F75 */
+-    if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom,
++    if (!pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
+                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                               sector_len, 2, 0, 0, 0, 0, 0)) {
++                               FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
+         error_report("Error registering flash memory");
+         exit(1);
+     }
+@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
+     PXA2xxState *cpu;
+     DriveInfo *dinfo;
+-    uint32_t verdex_rom = 0x02000000;
+-    uint32_t verdex_ram = 0x10000000;
+-
+-    cpu = pxa270_init(verdex_ram, machine->cpu_type);
++    cpu = pxa270_init(VERDEX_RAM_SIZE, machine->cpu_type);
+     dinfo = drive_get(IF_PFLASH, 0, 0);
+     if (!dinfo && !qtest_enabled()) {
+@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
+     }
+     /* Micron RC28F256P30TFA */
+-    if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom,
++    if (!pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
+                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                               sector_len, 2, 0, 0, 0, 0, 0)) {
++                               FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
+         error_report("Error registering flash memory");
+         exit(1);
+     }
+--
+.34.1

-New patch
+[PULL 17/38] hw/arm/mainstone: Use the IEC binary prefix definitions
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+IEC binary prefixes ease code review: the unit is explicit.
+Add the FLASH_SECTOR_SIZE definition.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-8-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/mainstone.c | 18 ++++++++++--------
+file changed, 10 insertions(+), 8 deletions(-)
+diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/mainstone.c
++++ b/hw/arm/mainstone.c
+@@ -XXX,XX +XXX,XX @@
+  * GNU GPL, version 2 or (at your option) any later version.
+  */
+ #include "qemu/osdep.h"
++#include "qemu/units.h"
+ #include "qemu/error-report.h"
+ #include "qapi/error.h"
+ #include "hw/arm/pxa.h"
+@@ -XXX,XX +XXX,XX @@ static const struct keymap map[0xE0] = {
+ enum mainstone_model_e { mainstone };
+-#define MAINSTONE_RAM    0x04000000
+-#define MAINSTONE_ROM    0x00800000
+-#define MAINSTONE_FLASH    0x02000000
++#define MAINSTONE_RAM_SIZE      (64 * MiB)
++#define MAINSTONE_ROM_SIZE      (8 * MiB)
++#define MAINSTONE_FLASH_SIZE    (32 * MiB)
+ static struct arm_boot_info mainstone_binfo = {
+     .loader_start = PXA2XX_SDRAM_BASE,
+-    .ram_size = 0x04000000,
++    .ram_size = MAINSTONE_RAM_SIZE,
+ };
++#define FLASH_SECTOR_SIZE   (256 * KiB)
++
+ static void mainstone_common_init(MachineState *machine,
+                                   enum mainstone_model_e model, int arm_id)
+ {
+-    uint32_t sector_len = 256 * 1024;
+     hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
+     PXA2xxState *mpu;
+     DeviceState *mst_irq;
+@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
+     /* Setup CPU & memory */
+     mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
+-    memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
++    memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM_SIZE,
+                            &error_fatal);
+     memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
+@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
+         dinfo = drive_get(IF_PFLASH, 0, i);
+         if (!pflash_cfi01_register(mainstone_flash_base[i],
+                                    i ? "mainstone.flash1" : "mainstone.flash0",
+-                                   MAINSTONE_FLASH,
++                                   MAINSTONE_FLASH_SIZE,
+                                    dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                                   sector_len, 4, 0, 0, 0, 0, 0)) {
++                                   FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
+             error_report("Error registering flash memory");
+             exit(1);
+         }
+--
+.34.1

-New patch
+[PULL 18/38] hw/arm/musicpal: Use the IEC binary prefix definitions
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+IEC binary prefixes ease code review: the unit is explicit.
+Add the FLASH_SECTOR_SIZE definition.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-9-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/musicpal.c | 9 ++++++---
+file changed, 6 insertions(+), 3 deletions(-)
+diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/musicpal.c
++++ b/hw/arm/musicpal.c
+@@ -XXX,XX +XXX,XX @@
+  */
+ #include "qemu/osdep.h"
++#include "qemu/units.h"
+ #include "qapi/error.h"
+ #include "cpu.h"
+ #include "hw/sysbus.h"
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo musicpal_key_info = {
+     .class_init    = musicpal_key_class_init,
+ };
++#define FLASH_SECTOR_SIZE   (64 * KiB)
++
+ static struct arm_boot_info musicpal_binfo = {
+     .loader_start = 0x0,
+     .board_id = 0x20e,
+@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
+         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
+         flash_size = blk_getlength(blk);
+-        if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
+-            flash_size != 32*1024*1024) {
++        if (flash_size != 8 * MiB && flash_size != 16 * MiB &&
++            flash_size != 32 * MiB) {
+             error_report("Invalid flash image size");
+             exit(1);
+         }
+@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
+          */
+         pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX,
+                               "musicpal.flash", flash_size,
+-                              blk, 0x10000,
++                              blk, FLASH_SECTOR_SIZE,
+                               MP_FLASH_SIZE_MAX / flash_size,
+, 0x00BF, 0x236D, 0x0000, 0x0000,
+x5555, 0x2AAA, 0);
+--
+.34.1

-New patch
+[PULL 19/38] hw/arm/omap_sx1: Remove unused 'total_ram' definitions
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+The total_ram_v1/total_ram_v2 definitions were never used.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-10-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/omap_sx1.c | 2 --
+file changed, 2 deletions(-)
+diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap_sx1.c
++++ b/hw/arm/omap_sx1.c
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps static_ops = {
+ #define flash0_size    (16 * 1024 * 1024)
+ #define flash1_size    ( 8 * 1024 * 1024)
+ #define flash2_size    (32 * 1024 * 1024)
+-#define total_ram_v1    (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE)
+-#define total_ram_v2    (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE)
+ static struct arm_boot_info sx1_binfo = {
+     .loader_start = OMAP_EMIFF_BASE,
+--
+.34.1

-New patch
+[PULL 20/38] hw/arm/omap_sx1: Use the IEC binary prefix definitions
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+IEC binary prefixes ease code review: the unit is explicit.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-11-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/omap_sx1.c | 33 +++++++++++++++++----------------
+file changed, 17 insertions(+), 16 deletions(-)
+diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap_sx1.c
++++ b/hw/arm/omap_sx1.c
+@@ -XXX,XX +XXX,XX @@
+  * with this program; if not, see <http://www.gnu.org/licenses/>.
+  */
+ #include "qemu/osdep.h"
++#include "qemu/units.h"
+ #include "qapi/error.h"
+ #include "ui/console.h"
+ #include "hw/arm/omap.h"
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps static_ops = {
+     .endianness = DEVICE_NATIVE_ENDIAN,
+ };
+-#define sdram_size    0x02000000
+-#define sector_size    (128 * 1024)
+-#define flash0_size    (16 * 1024 * 1024)
+-#define flash1_size    ( 8 * 1024 * 1024)
+-#define flash2_size    (32 * 1024 * 1024)
++#define SDRAM_SIZE      (32 * MiB)
++#define SECTOR_SIZE     (128 * KiB)
++#define FLASH0_SIZE     (16 * MiB)
++#define FLASH1_SIZE     (8 * MiB)
++#define FLASH2_SIZE     (32 * MiB)
+ static struct arm_boot_info sx1_binfo = {
+     .loader_start = OMAP_EMIFF_BASE,
+-    .ram_size = sdram_size,
++    .ram_size = SDRAM_SIZE,
+     .board_id = 0x265,
+ };
+@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
+     static uint32_t cs3val = 0x00001139;
+     DriveInfo *dinfo;
+     int fl_idx;
+-    uint32_t flash_size = flash0_size;
++    uint32_t flash_size = FLASH0_SIZE;
+     if (machine->ram_size != mc->default_ram_size) {
+         char *sz = size_to_str(mc->default_ram_size);
+@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
+     }
+     if (version == 2) {
+-        flash_size = flash2_size;
++        flash_size = FLASH2_SIZE;
+     }
+     memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram);
+@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
+         if (!pflash_cfi01_register(OMAP_CS0_BASE,
+                                    "omap_sx1.flash0-1", flash_size,
+                                    blk_by_legacy_dinfo(dinfo),
+-                                   sector_size, 4, 0, 0, 0, 0, 0)) {
++                                   SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
+             fprintf(stderr, "qemu: Error registering flash memory %d.\n",
+                            fl_idx);
+         }
+@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
+             (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
+         MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
+         memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0",
+-                               flash1_size, &error_fatal);
++                               FLASH1_SIZE, &error_fatal);
+         memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
+         memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
+-                              "sx1.cs1", OMAP_CS1_SIZE - flash1_size);
++                              "sx1.cs1", OMAP_CS1_SIZE - FLASH1_SIZE);
+         memory_region_add_subregion(address_space,
+-                                OMAP_CS1_BASE + flash1_size, &cs[1]);
++                                OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
+         if (!pflash_cfi01_register(OMAP_CS1_BASE,
+-                                   "omap_sx1.flash1-1", flash1_size,
++                                   "omap_sx1.flash1-1", FLASH1_SIZE,
+                                    blk_by_legacy_dinfo(dinfo),
+-                                   sector_size, 4, 0, 0, 0, 0, 0)) {
++                                   SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
+             fprintf(stderr, "qemu: Error registering flash memory %d.\n",
+                            fl_idx);
+         }
+@@ -XXX,XX +XXX,XX @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
+     mc->init = sx1_init_v2;
+     mc->ignore_memory_transaction_failures = true;
+     mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
+-    mc->default_ram_size = sdram_size;
++    mc->default_ram_size = SDRAM_SIZE;
+     mc->default_ram_id = "omap1.dram";
+ }
+@@ -XXX,XX +XXX,XX @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
+     mc->init = sx1_init_v1;
+     mc->ignore_memory_transaction_failures = true;
+     mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
+-    mc->default_ram_size = sdram_size;
++    mc->default_ram_size = SDRAM_SIZE;
+     mc->default_ram_id = "omap1.dram";
+ }
+--
+.34.1

-New patch
+[PULL 21/38] hw/arm/z2: Use the IEC binary prefix definitions
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+IEC binary prefixes ease code review: the unit is explicit.
+Add the FLASH_SECTOR_SIZE definition.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-12-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/z2.c | 6 ++++--
+file changed, 4 insertions(+), 2 deletions(-)
+diff --git a/hw/arm/z2.c b/hw/arm/z2.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/z2.c
++++ b/hw/arm/z2.c
+@@ -XXX,XX +XXX,XX @@
+  */
+ #include "qemu/osdep.h"
++#include "qemu/units.h"
+ #include "hw/arm/pxa.h"
+ #include "hw/arm/boot.h"
+ #include "hw/i2c/i2c.h"
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo aer915_info = {
+     .class_init    = aer915_class_init,
+ };
++#define FLASH_SECTOR_SIZE   (64 * KiB)
++
+ static void z2_init(MachineState *machine)
+ {
+-    uint32_t sector_len = 0x10000;
+     PXA2xxState *mpu;
+     DriveInfo *dinfo;
+     void *z2_lcd;
+@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
+     dinfo = drive_get(IF_PFLASH, 0, 0);
+     if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
+                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                               sector_len, 4, 0, 0, 0, 0, 0)) {
++                               FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
+         error_report("Error registering flash memory");
+         exit(1);
+     }
+--
+.34.1

-New patch
+[PULL 22/38] hw/arm/vexpress: Remove dead code in vexpress_common_init()
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Upon introduction in commit b8433303fb ("Set proper device-width
+for vexpress flash"), ve_pflash_cfi01_register() was calling
+qdev_init_nofail() which can not fail. This call was later
+converted with a script to use &error_fatal, still unable to
+fail. Remove the unreachable code.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-13-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/vexpress.c | 10 +---------
+file changed, 1 insertion(+), 9 deletions(-)
+diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/vexpress.c
++++ b/hw/arm/vexpress.c
+@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
+     dinfo = drive_get(IF_PFLASH, 0, 0);
+     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
+                                        dinfo);
+-    if (!pflash0) {
+-        error_report("vexpress: error registering flash 0");
+-        exit(1);
+-    }
+     if (map[VE_NORFLASHALIAS] != -1) {
+         /* Map flash 0 as an alias into low memory */
+@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
+     }
+     dinfo = drive_get(IF_PFLASH, 0, 1);
+-    if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
+-                                  dinfo)) {
+-        error_report("vexpress: error registering flash 1");
+-        exit(1);
+-    }
++    ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo);
+     sram_size = 0x2000000;
+     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
+--
+.34.1

-New patch
+[PULL 23/38] hw/arm: Remove unreachable code calling pflash_cfi01_register()
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Since its QOM'ification in commit 368a354f02 ("pflash_cfi0x:
+QOMified") the pflash_cfi01_register() function does not fail.
+This call was later converted with a script to use &error_fatal,
+still unable to fail. Remove the unreachable code.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109115316.2235-14-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/gumstix.c     | 18 ++++++------------
+ hw/arm/mainstone.c   | 13 +++++--------
+ hw/arm/omap_sx1.c    | 22 ++++++++--------------
+ hw/arm/versatilepb.c |  6 ++----
+ hw/arm/z2.c          |  9 +++------
+files changed, 24 insertions(+), 44 deletions(-)
+diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/gumstix.c
++++ b/hw/arm/gumstix.c
+@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
+     }
+     /* Numonyx RC28F128J3F75 */
+-    if (!pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
+-                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                               FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
+-        error_report("Error registering flash memory");
+-        exit(1);
+-    }
++    pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
++                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
++                          FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
+     /* Interrupt line of NIC is connected to GPIO line 36 */
+     smc91c111_init(&nd_table[0], 0x04000300,
+@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
+     }
+     /* Micron RC28F256P30TFA */
+-    if (!pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
+-                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                               FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
+-        error_report("Error registering flash memory");
+-        exit(1);
+-    }
++    pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
++                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
++                          FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
+     /* Interrupt line of NIC is connected to GPIO line 99 */
+     smc91c111_init(&nd_table[0], 0x04000300,
+diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/mainstone.c
++++ b/hw/arm/mainstone.c
+@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
+     /* There are two 32MiB flash devices on the board */
+     for (i = 0; i < 2; i ++) {
+         dinfo = drive_get(IF_PFLASH, 0, i);
+-        if (!pflash_cfi01_register(mainstone_flash_base[i],
+-                                   i ? "mainstone.flash1" : "mainstone.flash0",
+-                                   MAINSTONE_FLASH_SIZE,
+-                                   dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                                   FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
+-            error_report("Error registering flash memory");
+-            exit(1);
+-        }
++        pflash_cfi01_register(mainstone_flash_base[i],
++                              i ? "mainstone.flash1" : "mainstone.flash0",
++                              MAINSTONE_FLASH_SIZE,
++                              dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
++                              FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
+     }
+     mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
+diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap_sx1.c
++++ b/hw/arm/omap_sx1.c
+@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
+     fl_idx = 0;
+     if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
+-        if (!pflash_cfi01_register(OMAP_CS0_BASE,
+-                                   "omap_sx1.flash0-1", flash_size,
+-                                   blk_by_legacy_dinfo(dinfo),
+-                                   SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
+-            fprintf(stderr, "qemu: Error registering flash memory %d.\n",
+-                           fl_idx);
+-        }
++        pflash_cfi01_register(OMAP_CS0_BASE,
++                              "omap_sx1.flash0-1", flash_size,
++                              blk_by_legacy_dinfo(dinfo),
++                              SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
+         fl_idx++;
+     }
+@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
+         memory_region_add_subregion(address_space,
+                                 OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
+-        if (!pflash_cfi01_register(OMAP_CS1_BASE,
+-                                   "omap_sx1.flash1-1", FLASH1_SIZE,
+-                                   blk_by_legacy_dinfo(dinfo),
+-                                   SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
+-            fprintf(stderr, "qemu: Error registering flash memory %d.\n",
+-                           fl_idx);
+-        }
++        pflash_cfi01_register(OMAP_CS1_BASE,
++                              "omap_sx1.flash1-1", FLASH1_SIZE,
++                              blk_by_legacy_dinfo(dinfo),
++                              SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
+         fl_idx++;
+     } else {
+         memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
+diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/versatilepb.c
++++ b/hw/arm/versatilepb.c
+@@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id)
+     /* 0x34000000 NOR Flash */
+     dinfo = drive_get(IF_PFLASH, 0, 0);
+-    if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
++    pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
+                           VERSATILE_FLASH_SIZE,
+                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+                           VERSATILE_FLASH_SECT_SIZE,
+-                          4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
+-        fprintf(stderr, "qemu: Error registering flash memory.\n");
+-    }
++                          4, 0x0089, 0x0018, 0x0000, 0x0, 0);
+     versatile_binfo.ram_size = machine->ram_size;
+     versatile_binfo.board_id = board_id;
+diff --git a/hw/arm/z2.c b/hw/arm/z2.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/z2.c
++++ b/hw/arm/z2.c
+@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
+     mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type);
+     dinfo = drive_get(IF_PFLASH, 0, 0);
+-    if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
+-                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+-                               FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
+-        error_report("Error registering flash memory");
+-        exit(1);
+-    }
++    pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
++                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
++                          FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
+     /* setup keypad */
+     pxa27x_register_keypad(mpu->kp, map, 0x100);
+--
+.34.1

-New patch
+[PULL 24/38] hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+To avoid forward-declaring PXA2xxI2CState, declare
+PXA2XX_I2C before its use in pxa2xx_i2c_init() prototype.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109140306.23161-2-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/pxa.h | 6 +++---
+file changed, 3 insertions(+), 3 deletions(-)
+diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/pxa.h
++++ b/include/hw/arm/pxa.h
+@@ -XXX,XX +XXX,XX @@ void pxa27x_register_keypad(PXA2xxKeyPadState *kp,
+                             const struct keymap *map, int size);
+ /* pxa2xx.c */
+-typedef struct PXA2xxI2CState PXA2xxI2CState;
++#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
++OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
++
+ PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
+                 qemu_irq irq, uint32_t page_size);
+ I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
+-#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
+ typedef struct PXA2xxI2SState PXA2xxI2SState;
+-OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
+ #define TYPE_PXA2XX_FIR "pxa2xx-fir"
+ OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState, PXA2XX_FIR)
+--
+.34.1

-New patch
+[PULL 25/38] hw/gpio/omap_gpio: Add local variable to avoid embedded cast
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Add a local 'struct omap_gpif_s *' variable to improve readability.
+(This also eases next commit conversion).
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109140306.23161-3-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/gpio/omap_gpio.c | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/gpio/omap_gpio.c
++++ b/hw/gpio/omap_gpio.c
+@@ -XXX,XX +XXX,XX @@ struct omap_gpif_s {
+ /* General-Purpose I/O of OMAP1 */
+ static void omap_gpio_set(void *opaque, int line, int level)
+ {
+-    struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1;
++    struct omap_gpif_s *p = opaque;
++    struct omap_gpio_s *s = &p->omap1;
+     uint16_t prev = s->inputs;
+     if (level)
+--
+.34.1

-New patch
+[PULL 26/38] hw/arm/omap: Drop useless casts from void * to pointer
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109140306.23161-4-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/omap1.c            | 115 ++++++++++++++++++--------------------
+ hw/arm/omap2.c            |  40 ++++++-------
+ hw/arm/omap_sx1.c         |   2 +-
+ hw/arm/palm.c             |   2 +-
+ hw/char/omap_uart.c       |   7 +--
+ hw/display/omap_dss.c     |  15 +++--
+ hw/display/omap_lcdc.c    |   9 ++-
+ hw/dma/omap_dma.c         |  15 +++--
+ hw/gpio/omap_gpio.c       |  15 +++--
+ hw/intc/omap_intc.c       |  12 ++--
+ hw/misc/omap_gpmc.c       |  12 ++--
+ hw/misc/omap_l4.c         |   7 +--
+ hw/misc/omap_sdrc.c       |   7 +--
+ hw/misc/omap_tap.c        |   5 +-
+ hw/sd/omap_mmc.c          |   9 ++-
+ hw/ssi/omap_spi.c         |   7 +--
+ hw/timer/omap_gptimer.c   |  22 ++++----
+ hw/timer/omap_synctimer.c |   4 +-
+files changed, 142 insertions(+), 163 deletions(-)
+diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap1.c
++++ b/hw/arm/omap1.c
+@@ -XXX,XX +XXX,XX @@ static void omap_timer_fire(void *opaque)
+ static void omap_timer_tick(void *opaque)
+ {
+-    struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
++    struct omap_mpu_timer_s *timer = opaque;
+     omap_timer_sync(timer);
+     omap_timer_fire(timer);
+@@ -XXX,XX +XXX,XX @@ static void omap_timer_tick(void *opaque)
+ static void omap_timer_clk_update(void *opaque, int line, int on)
+ {
+-    struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
++    struct omap_mpu_timer_s *timer = opaque;
+     omap_timer_sync(timer);
+     timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
+@@ -XXX,XX +XXX,XX @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
+ static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
+                                     unsigned size)
+ {
+-    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
++    struct omap_mpu_timer_s *s = opaque;
+     if (size != 4) {
+         return omap_badwidth_read32(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
+ static void omap_mpu_timer_write(void *opaque, hwaddr addr,
+                                  uint64_t value, unsigned size)
+ {
+-    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
++    struct omap_mpu_timer_s *s = opaque;
+     if (size != 4) {
+         omap_badwidth_write32(opaque, addr, value);
+@@ -XXX,XX +XXX,XX @@ struct omap_watchdog_timer_s {
+ static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
+                                    unsigned size)
+ {
+-    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
++    struct omap_watchdog_timer_s *s = opaque;
+     if (size != 2) {
+         return omap_badwidth_read16(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
+ static void omap_wd_timer_write(void *opaque, hwaddr addr,
+                                 uint64_t value, unsigned size)
+ {
+-    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
++    struct omap_watchdog_timer_s *s = opaque;
+     if (size != 2) {
+         omap_badwidth_write16(opaque, addr, value);
+@@ -XXX,XX +XXX,XX @@ struct omap_32khz_timer_s {
+ static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
+                                    unsigned size)
+ {
+-    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
++    struct omap_32khz_timer_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 4) {
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
+ static void omap_os_timer_write(void *opaque, hwaddr addr,
+                                 uint64_t value, unsigned size)
+ {
+-    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
++    struct omap_32khz_timer_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 4) {
+@@ -XXX,XX +XXX,XX @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
+ static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
+                                   unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     uint16_t ret;
+     if (size != 2) {
+@@ -XXX,XX +XXX,XX @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
+ static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
+                                uint64_t value, unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     int64_t now, ticks;
+     int div, mult;
+     static const int bypass_div[4] = { 1, 2, 4, 4 };
+@@ -XXX,XX +XXX,XX @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory,
+ static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
+                                   unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     if (size != 4) {
+         return omap_badwidth_read32(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
+ static void omap_pin_cfg_write(void *opaque, hwaddr addr,
+                                uint64_t value, unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     uint32_t diff;
+     if (size != 4) {
+@@ -XXX,XX +XXX,XX @@ static void omap_pin_cfg_init(MemoryRegion *system_memory,
+ static uint64_t omap_id_read(void *opaque, hwaddr addr,
+                              unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     if (size != 4) {
+         return omap_badwidth_read32(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
+ static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     if (size != 4) {
+         return omap_badwidth_read32(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
+ static void omap_mpui_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     if (size != 4) {
+         omap_badwidth_write32(opaque, addr, value);
+@@ -XXX,XX +XXX,XX @@ struct omap_tipb_bridge_s {
+ static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
+                                       unsigned size)
+ {
+-    struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
++    struct omap_tipb_bridge_s *s = opaque;
+     if (size < 2) {
+         return omap_badwidth_read16(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
+ static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
+                                    uint64_t value, unsigned size)
+ {
+-    struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
++    struct omap_tipb_bridge_s *s = opaque;
+     if (size < 2) {
+         omap_badwidth_write16(opaque, addr, value);
+@@ -XXX,XX +XXX,XX @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
+ static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     uint32_t ret;
+     if (size != 4) {
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
+ static void omap_tcmi_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     if (size != 4) {
+         omap_badwidth_write32(opaque, addr, value);
+@@ -XXX,XX +XXX,XX @@ struct dpll_ctl_s {
+ static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
++    struct dpll_ctl_s *s = opaque;
+     if (size != 2) {
+         return omap_badwidth_read16(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
+ static void omap_dpll_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
++    struct dpll_ctl_s *s = opaque;
+     uint16_t diff;
+     static const int bypass_div[4] = { 1, 2, 4, 4 };
+     int div, mult;
+@@ -XXX,XX +XXX,XX @@ static struct dpll_ctl_s  *omap_dpll_init(MemoryRegion *memory,
+ static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     if (size != 2) {
+         return omap_badwidth_read16(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
+ static void omap_clkm_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     uint16_t diff;
+     omap_clk clk;
+     static const char *clkschemename[8] = {
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_clkm_ops = {
+ static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
+                                  unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     CPUState *cpu = CPU(s->cpu);
+     if (size != 2) {
+@@ -XXX,XX +XXX,XX @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
+ static void omap_clkdsp_write(void *opaque, hwaddr addr,
+                               uint64_t value, unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     uint16_t diff;
+     if (size != 2) {
+@@ -XXX,XX +XXX,XX @@ struct omap_mpuio_s {
+ static void omap_mpuio_set(void *opaque, int line, int level)
+ {
+-    struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
++    struct omap_mpuio_s *s = opaque;
+     uint16_t prev = s->inputs;
+     if (level)
+@@ -XXX,XX +XXX,XX @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
+ static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
+                                 unsigned size)
+ {
+-    struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
++    struct omap_mpuio_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     uint16_t ret;
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
+ static void omap_mpuio_write(void *opaque, hwaddr addr,
+                              uint64_t value, unsigned size)
+ {
+-    struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
++    struct omap_mpuio_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     uint16_t diff;
+     int ln;
+@@ -XXX,XX +XXX,XX @@ static void omap_mpuio_reset(struct omap_mpuio_s *s)
+ static void omap_mpuio_onoff(void *opaque, int line, int on)
+ {
+-    struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
++    struct omap_mpuio_s *s = opaque;
+     s->clk = on;
+     if (on)
+@@ -XXX,XX +XXX,XX @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
+     }
+ }
+-static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
+-                                unsigned size)
++static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
++    struct omap_uwire_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 2) {
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
+ static void omap_uwire_write(void *opaque, hwaddr addr,
+                              uint64_t value, unsigned size)
+ {
+-    struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
++    struct omap_uwire_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 2) {
+@@ -XXX,XX +XXX,XX @@ static void omap_pwl_update(struct omap_pwl_s *s)
+     }
+ }
+-static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
+-                              unsigned size)
++static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
++    struct omap_pwl_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 1) {
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
+ static void omap_pwl_write(void *opaque, hwaddr addr,
+                            uint64_t value, unsigned size)
+ {
+-    struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
++    struct omap_pwl_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 1) {
+@@ -XXX,XX +XXX,XX @@ static void omap_pwl_reset(struct omap_pwl_s *s)
+ static void omap_pwl_clk_update(void *opaque, int line, int on)
+ {
+-    struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
++    struct omap_pwl_s *s = opaque;
+     s->clk = on;
+     omap_pwl_update(s);
+@@ -XXX,XX +XXX,XX @@ struct omap_pwt_s {
+     omap_clk clk;
+ };
+-static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
+-                              unsigned size)
++static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
++    struct omap_pwt_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 1) {
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
+ static void omap_pwt_write(void *opaque, hwaddr addr,
+                            uint64_t value, unsigned size)
+ {
+-    struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
++    struct omap_pwt_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 1) {
+@@ -XXX,XX +XXX,XX @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s)
+         printf("%s: conversion failed\n", __func__);
+ }
+-static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
+-                              unsigned size)
++static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
++    struct omap_rtc_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     uint8_t i;
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
+ static void omap_rtc_write(void *opaque, hwaddr addr,
+                            uint64_t value, unsigned size)
+ {
+-    struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
++    struct omap_rtc_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     struct tm new_tm;
+     time_t ti[2];
+@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
+ static void omap_mcbsp_source_tick(void *opaque)
+ {
+-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
++    struct omap_mcbsp_s *s = opaque;
+     static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
+     if (!s->rx_rate)
+@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
+ static void omap_mcbsp_sink_tick(void *opaque)
+ {
+-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
++    struct omap_mcbsp_s *s = opaque;
+     static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
+     if (!s->tx_rate)
+@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
+ static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
+                                 unsigned size)
+ {
+-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
++    struct omap_mcbsp_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     uint16_t ret;
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
+ static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
+                 uint32_t value)
+ {
+-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
++    struct omap_mcbsp_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     switch (offset) {
+@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
+ static void omap_mcbsp_writew(void *opaque, hwaddr addr,
+                 uint32_t value)
+ {
+-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
++    struct omap_mcbsp_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (offset == 0x04) {                /* DXR */
+@@ -XXX,XX +XXX,XX @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
+ static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
+ {
+-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
++    struct omap_mcbsp_s *s = opaque;
+     if (s->rx_rate) {
+         s->rx_req = s->codec->in.len;
+@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
+ static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
+ {
+-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
++    struct omap_mcbsp_s *s = opaque;
+     if (s->tx_rate) {
+         s->tx_req = s->codec->out.size;
+@@ -XXX,XX +XXX,XX @@ static void omap_lpg_reset(struct omap_lpg_s *s)
+     omap_lpg_update(s);
+ }
+-static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
+-                              unsigned size)
++static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
++    struct omap_lpg_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 1) {
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
+ static void omap_lpg_write(void *opaque, hwaddr addr,
+                            uint64_t value, unsigned size)
+ {
+-    struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
++    struct omap_lpg_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 1) {
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_lpg_ops = {
+ static void omap_lpg_clk_update(void *opaque, int line, int on)
+ {
+-    struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
++    struct omap_lpg_s *s = opaque;
+     s->clk = on;
+     omap_lpg_update(s);
+@@ -XXX,XX +XXX,XX @@ static void omap_setup_mpui_io(MemoryRegion *system_memory,
+ /* General chip reset */
+ static void omap1_mpu_reset(void *opaque)
+ {
+-    struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *mpu = opaque;
+     omap_dma_reset(mpu->dma);
+     omap_mpu_timer_reset(mpu->timer[0]);
+@@ -XXX,XX +XXX,XX @@ static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
+ void omap_mpu_wakeup(void *opaque, int irq, int req)
+ {
+-    struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *mpu = opaque;
+     CPUState *cpu = CPU(mpu->cpu);
+     if (cpu->halted) {
+diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap2.c
++++ b/hw/arm/omap2.c
+@@ -XXX,XX +XXX,XX @@ static inline void omap_eac_out_empty(struct omap_eac_s *s)
+ static void omap_eac_in_cb(void *opaque, int avail_b)
+ {
+-    struct omap_eac_s *s = (struct omap_eac_s *) opaque;
++    struct omap_eac_s *s = opaque;
+     s->codec.rxavail = avail_b >> 2;
+     omap_eac_in_refill(s);
+@@ -XXX,XX +XXX,XX @@ static void omap_eac_in_cb(void *opaque, int avail_b)
+ static void omap_eac_out_cb(void *opaque, int free_b)
+ {
+-    struct omap_eac_s *s = (struct omap_eac_s *) opaque;
++    struct omap_eac_s *s = opaque;
+     s->codec.txavail = free_b >> 2;
+     if (s->codec.txlen)
+@@ -XXX,XX +XXX,XX @@ static void omap_eac_reset(struct omap_eac_s *s)
+     omap_eac_interrupt_update(s);
+ }
+-static uint64_t omap_eac_read(void *opaque, hwaddr addr,
+-                              unsigned size)
++static uint64_t omap_eac_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_eac_s *s = (struct omap_eac_s *) opaque;
++    struct omap_eac_s *s = opaque;
+     uint32_t ret;
+     if (size != 2) {
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_eac_read(void *opaque, hwaddr addr,
+ static void omap_eac_write(void *opaque, hwaddr addr,
+                            uint64_t value, unsigned size)
+ {
+-    struct omap_eac_s *s = (struct omap_eac_s *) opaque;
++    struct omap_eac_s *s = opaque;
+     if (size != 2) {
+         omap_badwidth_write16(opaque, addr, value);
+@@ -XXX,XX +XXX,XX @@ static void omap_sti_reset(struct omap_sti_s *s)
+ static uint64_t omap_sti_read(void *opaque, hwaddr addr,
+                               unsigned size)
+ {
+-    struct omap_sti_s *s = (struct omap_sti_s *) opaque;
++    struct omap_sti_s *s = opaque;
+     if (size != 4) {
+         return omap_badwidth_read32(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sti_read(void *opaque, hwaddr addr,
+ static void omap_sti_write(void *opaque, hwaddr addr,
+                            uint64_t value, unsigned size)
+ {
+-    struct omap_sti_s *s = (struct omap_sti_s *) opaque;
++    struct omap_sti_s *s = opaque;
+     if (size != 4) {
+         omap_badwidth_write32(opaque, addr, value);
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_sti_ops = {
+     .endianness = DEVICE_NATIVE_ENDIAN,
+ };
+-static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
+-                                   unsigned size)
++static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, unsigned size)
+ {
+     OMAP_BAD_REG(addr);
+     return 0;
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
+ static void omap_sti_fifo_write(void *opaque, hwaddr addr,
+                                 uint64_t value, unsigned size)
+ {
+-    struct omap_sti_s *s = (struct omap_sti_s *) opaque;
++    struct omap_sti_s *s = opaque;
+     int ch = addr >> 6;
+     uint8_t byte = value;
+@@ -XXX,XX +XXX,XX @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
+ static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
++    struct omap_prcm_s *s = opaque;
+     uint32_t ret;
+     if (size != 4) {
+@@ -XXX,XX +XXX,XX @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
+ static void omap_prcm_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
++    struct omap_prcm_s *s = opaque;
+     if (size != 4) {
+         omap_badwidth_write32(opaque, addr, value);
+@@ -XXX,XX +XXX,XX @@ struct omap_sysctl_s {
+ static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
+ {
+-    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
++    struct omap_sysctl_s *s = opaque;
+     int pad_offset, byte_offset;
+     int value;
+@@ -XXX,XX +XXX,XX @@ static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
+ static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
+ {
+-    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
++    struct omap_sysctl_s *s = opaque;
+     switch (addr) {
+     case 0x000:    /* CONTROL_REVISION */
+@@ -XXX,XX +XXX,XX @@ static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
+     return 0;
+ }
+-static void omap_sysctl_write8(void *opaque, hwaddr addr,
+-                uint32_t value)
++static void omap_sysctl_write8(void *opaque, hwaddr addr, uint32_t value)
+ {
+-    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
++    struct omap_sysctl_s *s = opaque;
+     int pad_offset, byte_offset;
+     int prev_value;
+@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write8(void *opaque, hwaddr addr,
+     }
+ }
+-static void omap_sysctl_write(void *opaque, hwaddr addr,
+-                uint32_t value)
++static void omap_sysctl_write(void *opaque, hwaddr addr, uint32_t value)
+ {
+-    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
++    struct omap_sysctl_s *s = opaque;
+     switch (addr) {
+     case 0x000:    /* CONTROL_REVISION */
+@@ -XXX,XX +XXX,XX @@ static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
+ /* General chip reset */
+ static void omap2_mpu_reset(void *opaque)
+ {
+-    struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *mpu = opaque;
+     omap_dma_reset(mpu->dma);
+     omap_prcm_reset(mpu->prcm);
+diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/omap_sx1.c
++++ b/hw/arm/omap_sx1.c
+@@ -XXX,XX +XXX,XX @@
+ static uint64_t static_read(void *opaque, hwaddr offset,
+                             unsigned size)
+ {
+-    uint32_t *val = (uint32_t *) opaque;
++    uint32_t *val = opaque;
+     uint32_t mask = (4 / size) - 1;
+     return *val >> ((offset & mask) << 3);
+diff --git a/hw/arm/palm.c b/hw/arm/palm.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/palm.c
++++ b/hw/arm/palm.c
+@@ -XXX,XX +XXX,XX @@ static struct {
+ static void palmte_button_event(void *opaque, int keycode)
+ {
+-    struct omap_mpu_state_s *cpu = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *cpu = opaque;
+     if (palmte_keymap[keycode & 0x7f].row != -1)
+         omap_mpuio_key(cpu->mpuio,
+diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/char/omap_uart.c
++++ b/hw/char/omap_uart.c
+@@ -XXX,XX +XXX,XX @@ struct omap_uart_s *omap_uart_init(hwaddr base,
+     return s;
+ }
+-static uint64_t omap_uart_read(void *opaque, hwaddr addr,
+-                               unsigned size)
++static uint64_t omap_uart_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_uart_s *s = (struct omap_uart_s *) opaque;
++    struct omap_uart_s *s = opaque;
+     if (size == 4) {
+         return omap_badwidth_read8(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_uart_read(void *opaque, hwaddr addr,
+ static void omap_uart_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_uart_s *s = (struct omap_uart_s *) opaque;
++    struct omap_uart_s *s = opaque;
+     if (size == 4) {
+         omap_badwidth_write8(opaque, addr, value);
+diff --git a/hw/display/omap_dss.c b/hw/display/omap_dss.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/display/omap_dss.c
++++ b/hw/display/omap_dss.c
+@@ -XXX,XX +XXX,XX @@ void omap_dss_reset(struct omap_dss_s *s)
+ static uint64_t omap_diss_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
++    struct omap_dss_s *s = opaque;
+     if (size != 4) {
+         return omap_badwidth_read32(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_diss_read(void *opaque, hwaddr addr,
+ static void omap_diss_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
++    struct omap_dss_s *s = opaque;
+     if (size != 4) {
+         omap_badwidth_write32(opaque, addr, value);
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_diss_ops = {
+ static uint64_t omap_disc_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
++    struct omap_dss_s *s = opaque;
+     if (size != 4) {
+         return omap_badwidth_read32(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_disc_read(void *opaque, hwaddr addr,
+ static void omap_disc_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
++    struct omap_dss_s *s = opaque;
+     if (size != 4) {
+         omap_badwidth_write32(opaque, addr, value);
+@@ -XXX,XX +XXX,XX @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
+     omap_dispc_interrupt_update(s);
+ }
+-static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
+-                               unsigned size)
++static uint64_t omap_rfbi_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
++    struct omap_dss_s *s = opaque;
+     if (size != 4) {
+         return omap_badwidth_read32(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
+ static void omap_rfbi_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
++    struct omap_dss_s *s = opaque;
+     if (size != 4) {
+         omap_badwidth_write32(opaque, addr, value);
+diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/display/omap_lcdc.c
++++ b/hw/display/omap_lcdc.c
+@@ -XXX,XX +XXX,XX @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s,
+ static void omap_update_display(void *opaque)
+ {
+-    struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
++    struct omap_lcd_panel_s *omap_lcd = opaque;
+     DisplaySurface *surface;
+     drawfn draw_line;
+     int size, height, first, last;
+@@ -XXX,XX +XXX,XX @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
+     }
+ }
+-static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
+-                               unsigned size)
++static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
++    struct omap_lcd_panel_s *s = opaque;
+     switch (addr) {
+     case 0x00:    /* LCD_CONTROL */
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
+ static void omap_lcdc_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
++    struct omap_lcd_panel_s *s = opaque;
+     switch (addr) {
+     case 0x00:    /* LCD_CONTROL */
+diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/dma/omap_dma.c
++++ b/hw/dma/omap_dma.c
+@@ -XXX,XX +XXX,XX @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
+     return 0;
+ }
+-static uint64_t omap_dma_read(void *opaque, hwaddr addr,
+-                              unsigned size)
++static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
++    struct omap_dma_s *s = opaque;
+     int reg, ch;
+     uint16_t ret;
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr,
+ static void omap_dma_write(void *opaque, hwaddr addr,
+                            uint64_t value, unsigned size)
+ {
+-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
++    struct omap_dma_s *s = opaque;
+     int reg, ch;
+     if (size != 2) {
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_dma_ops = {
+ static void omap_dma_request(void *opaque, int drq, int req)
+ {
+-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
++    struct omap_dma_s *s = opaque;
+     /* The request pins are level triggered in QEMU.  */
+     if (req) {
+         if (~s->dma->drqbmp & (1ULL << drq)) {
+@@ -XXX,XX +XXX,XX @@ static void omap_dma_request(void *opaque, int drq, int req)
+ /* XXX: this won't be needed once soc_dma knows about clocks.  */
+ static void omap_dma_clk_update(void *opaque, int line, int on)
+ {
+-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
++    struct omap_dma_s *s = opaque;
+     int i;
+     s->dma->freq = omap_clk_getrate(s->clk);
+@@ -XXX,XX +XXX,XX @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
+ static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
++    struct omap_dma_s *s = opaque;
+     int irqn = 0, chnum;
+     struct omap_dma_channel_s *ch;
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
+ static void omap_dma4_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
++    struct omap_dma_s *s = opaque;
+     int chnum, irqn = 0;
+     struct omap_dma_channel_s *ch;
+diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/gpio/omap_gpio.c
++++ b/hw/gpio/omap_gpio.c
+@@ -XXX,XX +XXX,XX @@ static void omap_gpio_set(void *opaque, int line, int level)
+ static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
++    struct omap_gpio_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     if (size != 2) {
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
+ static void omap_gpio_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
++    struct omap_gpio_s *s = opaque;
+     int offset = addr & OMAP_MPUI_REG_MASK;
+     uint16_t diff;
+     int ln;
+@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
+ static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
+ {
+-    struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
++    struct omap2_gpio_s *s = opaque;
+     switch (addr) {
+     case 0x00:    /* GPIO_REVISION */
+@@ -XXX,XX +XXX,XX @@ static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
+ static void omap2_gpio_module_write(void *opaque, hwaddr addr,
+                 uint32_t value)
+ {
+-    struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
++    struct omap2_gpio_s *s = opaque;
+     uint32_t diff;
+     int ln;
+@@ -XXX,XX +XXX,XX @@ static void omap2_gpif_reset(DeviceState *dev)
+     s->gpo = 0;
+ }
+-static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
+-                                    unsigned size)
++static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
++    struct omap2_gpif_s *s = opaque;
+     switch (addr) {
+     case 0x00:    /* IPGENERICOCPSPL_REVISION */
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
+ static void omap2_gpif_top_write(void *opaque, hwaddr addr,
+                                  uint64_t value, unsigned size)
+ {
+-    struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
++    struct omap2_gpif_s *s = opaque;
+     switch (addr) {
+     case 0x00:    /* IPGENERICOCPSPL_REVISION */
+diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/omap_intc.c
++++ b/hw/intc/omap_intc.c
+@@ -XXX,XX +XXX,XX @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
+ static void omap_set_intr(void *opaque, int irq, int req)
+ {
+-    struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
++    struct omap_intr_handler_s *ih = opaque;
+     uint32_t rise;
+     struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
+@@ -XXX,XX +XXX,XX @@ static void omap_set_intr(void *opaque, int irq, int req)
+ /* Simplified version with no edge detection */
+ static void omap_set_intr_noedge(void *opaque, int irq, int req)
+ {
+-    struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
++    struct omap_intr_handler_s *ih = opaque;
+     uint32_t rise;
+     struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
+@@ -XXX,XX +XXX,XX @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
+ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
++    struct omap_intr_handler_s *s = opaque;
+     int i, offset = addr;
+     int bank_no = offset >> 8;
+     int line_no;
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
+ static void omap_inth_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
++    struct omap_intr_handler_s *s = opaque;
+     int i, offset = addr;
+     int bank_no = offset >> 8;
+     struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_intc_info = {
+ static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
+                                 unsigned size)
+ {
+-    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
++    struct omap_intr_handler_s *s = opaque;
+     int offset = addr;
+     int bank_no, line_no;
+     struct omap_intr_handler_bank_s *bank = NULL;
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
+ static void omap2_inth_write(void *opaque, hwaddr addr,
+                              uint64_t value, unsigned size)
+ {
+-    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
++    struct omap_intr_handler_s *s = opaque;
+     int offset = addr;
+     int bank_no, line_no;
+     struct omap_intr_handler_bank_s *bank = NULL;
+diff --git a/hw/misc/omap_gpmc.c b/hw/misc/omap_gpmc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/misc/omap_gpmc.c
++++ b/hw/misc/omap_gpmc.c
+@@ -XXX,XX +XXX,XX @@ static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int value)
+ static uint64_t omap_nand_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
++    struct omap_gpmc_cs_file_s *f = opaque;
+     uint64_t v;
+     nand_setpins(f->dev, 0, 0, 0, 1, 0);
+     switch (omap_gpmc_devsize(f)) {
+@@ -XXX,XX +XXX,XX @@ static void omap_nand_setio(DeviceState *dev, uint64_t value,
+ static void omap_nand_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
++    struct omap_gpmc_cs_file_s *f = opaque;
+     nand_setpins(f->dev, 0, 0, 0, 1, 0);
+     omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
+ }
+@@ -XXX,XX +XXX,XX @@ static void fill_prefetch_fifo(struct omap_gpmc_s *s)
+ static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
+                                         unsigned size)
+ {
+-    struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
++    struct omap_gpmc_s *s = opaque;
+     uint32_t data;
+     if (s->prefetch.config1 & 1) {
+         /* The TRM doesn't define the behaviour if you read from the
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
+ static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr,
+                                      uint64_t value, unsigned size)
+ {
+-    struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
++    struct omap_gpmc_s *s = opaque;
+     int cs = prefetch_cs(s->prefetch.config1);
+     if ((s->prefetch.config1 & 1) == 0) {
+         /* The TRM doesn't define the behaviour of writing to the
+@@ -XXX,XX +XXX,XX @@ static int gpmc_wordaccess_only(hwaddr addr)
+ static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
+                                unsigned size)
+ {
+-    struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
++    struct omap_gpmc_s *s = opaque;
+     int cs;
+     struct omap_gpmc_cs_file_s *f;
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
+ static void omap_gpmc_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
++    struct omap_gpmc_s *s = opaque;
+     int cs;
+     struct omap_gpmc_cs_file_s *f;
+diff --git a/hw/misc/omap_l4.c b/hw/misc/omap_l4.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/misc/omap_l4.c
++++ b/hw/misc/omap_l4.c
+@@ -XXX,XX +XXX,XX @@ hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
+     return ta->start[region].size;
+ }
+-static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
+-                               unsigned size)
++static uint64_t omap_l4ta_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
++    struct omap_target_agent_s *s = opaque;
+     if (size != 2) {
+         return omap_badwidth_read16(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
+ static void omap_l4ta_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
++    struct omap_target_agent_s *s = opaque;
+     if (size != 4) {
+         omap_badwidth_write32(opaque, addr, value);
+diff --git a/hw/misc/omap_sdrc.c b/hw/misc/omap_sdrc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/misc/omap_sdrc.c
++++ b/hw/misc/omap_sdrc.c
+@@ -XXX,XX +XXX,XX @@ void omap_sdrc_reset(struct omap_sdrc_s *s)
+     s->config = 0x10;
+ }
+-static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
+-                               unsigned size)
++static uint64_t omap_sdrc_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
++    struct omap_sdrc_s *s = opaque;
+     if (size != 4) {
+         return omap_badwidth_read32(opaque, addr);
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
+ static void omap_sdrc_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+ {
+-    struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
++    struct omap_sdrc_s *s = opaque;
+     if (size != 4) {
+         omap_badwidth_write32(opaque, addr, value);
+diff --git a/hw/misc/omap_tap.c b/hw/misc/omap_tap.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/misc/omap_tap.c
++++ b/hw/misc/omap_tap.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/arm/omap.h"
+ /* TEST-Chip-level TAP */
+-static uint64_t omap_tap_read(void *opaque, hwaddr addr,
+-                              unsigned size)
++static uint64_t omap_tap_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
++    struct omap_mpu_state_s *s = opaque;
+     if (size != 4) {
+         return omap_badwidth_read32(opaque, addr);
+diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/sd/omap_mmc.c
++++ b/hw/sd/omap_mmc.c
+@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
+     device_cold_reset(DEVICE(host->card));
+ }
+-static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
+-                              unsigned size)
++static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size)
+ {
+     uint16_t i;
+-    struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
++    struct omap_mmc_s *s = opaque;
+     if (size != 2) {
+         return omap_badwidth_read16(opaque, offset);
+@@ -XXX,XX +XXX,XX @@ static void omap_mmc_write(void *opaque, hwaddr offset,
+                            uint64_t value, unsigned size)
+ {
+     int i;
+-    struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
++    struct omap_mmc_s *s = opaque;
+     if (size != 2) {
+         omap_badwidth_write16(opaque, offset, value);
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_mmc_ops = {
+ static void omap_mmc_cover_cb(void *opaque, int line, int level)
+ {
+-    struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
++    struct omap_mmc_s *host = opaque;
+     if (!host->cdet_state && level) {
+         host->status |= 0x0002;
+diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/ssi/omap_spi.c
++++ b/hw/ssi/omap_spi.c
+@@ -XXX,XX +XXX,XX @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
+     omap_mcspi_interrupt_update(s);
+ }
+-static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
+-                                unsigned size)
++static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, unsigned size)
+ {
+-    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
++    struct omap_mcspi_s *s = opaque;
+     int ch = 0;
+     uint32_t ret;
+@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
+ static void omap_mcspi_write(void *opaque, hwaddr addr,
+                              uint64_t value, unsigned size)
+ {
+-    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
++    struct omap_mcspi_s *s = opaque;
+     int ch = 0;
+     if (size != 4) {
+diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/timer/omap_gptimer.c
++++ b/hw/timer/omap_gptimer.c
+@@ -XXX,XX +XXX,XX @@ static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
+ static void omap_gp_timer_tick(void *opaque)
+ {
+-    struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
++    struct omap_gp_timer_s *timer = opaque;
+     if (!timer->ar) {
+         timer->st = 0;
+@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_tick(void *opaque)
+ static void omap_gp_timer_match(void *opaque)
+ {
+-    struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
++    struct omap_gp_timer_s *timer = opaque;
+     if (timer->trigger == gpt_trigger_both)
+         omap_gp_timer_trigger(timer);
+@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_match(void *opaque)
+ static void omap_gp_timer_input(void *opaque, int line, int on)
+ {
+-    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
++    struct omap_gp_timer_s *s = opaque;
+     int trigger;
+     switch (s->capture) {
+@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_input(void *opaque, int line, int on)
+ static void omap_gp_timer_clk_update(void *opaque, int line, int on)
+ {
+-    struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
++    struct omap_gp_timer_s *timer = opaque;
+     omap_gp_timer_sync(timer);
+     timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
+@@ -XXX,XX +XXX,XX @@ void omap_gp_timer_reset(struct omap_gp_timer_s *s)
+ static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
+ {
+-    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
++    struct omap_gp_timer_s *s = opaque;
+     switch (addr) {
+     case 0x00:    /* TIDR */
+@@ -XXX,XX +XXX,XX @@ static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
+ static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
+ {
+-    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
++    struct omap_gp_timer_s *s = opaque;
+     uint32_t ret;
+     if (addr & 2)
+@@ -XXX,XX +XXX,XX @@ static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
+     }
+ }
+-static void omap_gp_timer_write(void *opaque, hwaddr addr,
+-                uint32_t value)
++static void omap_gp_timer_write(void *opaque, hwaddr addr, uint32_t value)
+ {
+-    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
++    struct omap_gp_timer_s *s = opaque;
+     switch (addr) {
+     case 0x00:    /* TIDR */
+@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_write(void *opaque, hwaddr addr,
+     }
+ }
+-static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
+-                uint32_t value)
++static void omap_gp_timer_writeh(void *opaque, hwaddr addr, uint32_t value)
+ {
+-    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
++    struct omap_gp_timer_s *s = opaque;
+     if (addr & 2)
+         omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
+diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/timer/omap_synctimer.c
++++ b/hw/timer/omap_synctimer.c
+@@ -XXX,XX +XXX,XX @@ void omap_synctimer_reset(struct omap_synctimer_s *s)
+ static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
+ {
+-    struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
++    struct omap_synctimer_s *s = opaque;
+     switch (addr) {
+     case 0x00:    /* 32KSYNCNT_REV */
+@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
+ static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
+ {
+-    struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
++    struct omap_synctimer_s *s = opaque;
+     uint32_t ret;
+     if (addr & 2)
+--
+.34.1

-New patch
+[PULL 27/38] hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Following docs/devel/style.rst guidelines, rename omap_gpif_s ->
+Omap1GpioState. This also remove a use of 'struct' in the
+DECLARE_INSTANCE_CHECKER() macro call.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109140306.23161-5-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/omap.h |  6 +++---
+ hw/gpio/omap_gpio.c   | 16 ++++++++--------
+files changed, 11 insertions(+), 11 deletions(-)
+diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/omap.h
++++ b/include/hw/arm/omap.h
+@@ -XXX,XX +XXX,XX @@ void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk);
+ /* omap_gpio.c */
+ #define TYPE_OMAP1_GPIO "omap-gpio"
+-DECLARE_INSTANCE_CHECKER(struct omap_gpif_s, OMAP1_GPIO,
++typedef struct Omap1GpioState Omap1GpioState;
++DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO,
+                          TYPE_OMAP1_GPIO)
+ #define TYPE_OMAP2_GPIO "omap2-gpio"
+ DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
+                          TYPE_OMAP2_GPIO)
+-typedef struct omap_gpif_s omap_gpif;
+ typedef struct omap2_gpif_s omap2_gpif;
+ /* TODO: clock framework (see above) */
+-void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk);
++void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
+ void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
+ void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
+diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/gpio/omap_gpio.c
++++ b/hw/gpio/omap_gpio.c
+@@ -XXX,XX +XXX,XX @@ struct omap_gpio_s {
+     uint16_t pins;
+ };
+-struct omap_gpif_s {
++struct Omap1GpioState {
+     SysBusDevice parent_obj;
+     MemoryRegion iomem;
+@@ -XXX,XX +XXX,XX @@ struct omap_gpif_s {
+ /* General-Purpose I/O of OMAP1 */
+ static void omap_gpio_set(void *opaque, int line, int level)
+ {
+-    struct omap_gpif_s *p = opaque;
++    Omap1GpioState *p = opaque;
+     struct omap_gpio_s *s = &p->omap1;
+     uint16_t prev = s->inputs;
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_gpio_module_ops = {
+ static void omap_gpif_reset(DeviceState *dev)
+ {
+-    struct omap_gpif_s *s = OMAP1_GPIO(dev);
++    Omap1GpioState *s = OMAP1_GPIO(dev);
+     omap_gpio_reset(&s->omap1);
+ }
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_gpif_top_ops = {
+ static void omap_gpio_init(Object *obj)
+ {
+     DeviceState *dev = DEVICE(obj);
+-    struct omap_gpif_s *s = OMAP1_GPIO(obj);
++    Omap1GpioState *s = OMAP1_GPIO(obj);
+     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+     qdev_init_gpio_in(dev, omap_gpio_set, 16);
+@@ -XXX,XX +XXX,XX @@ static void omap_gpio_init(Object *obj)
+ static void omap_gpio_realize(DeviceState *dev, Error **errp)
+ {
+-    struct omap_gpif_s *s = OMAP1_GPIO(dev);
++    Omap1GpioState *s = OMAP1_GPIO(dev);
+     if (!s->clk) {
+         error_setg(errp, "omap-gpio: clk not connected");
+@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_realize(DeviceState *dev, Error **errp)
+     }
+ }
+-void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk)
++void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk)
+ {
+     gpio->clk = clk;
+ }
+ static Property omap_gpio_properties[] = {
+-    DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
++    DEFINE_PROP_INT32("mpu_model", Omap1GpioState, mpu_model, 0),
+     DEFINE_PROP_END_OF_LIST(),
+ };
+@@ -XXX,XX +XXX,XX @@ static void omap_gpio_class_init(ObjectClass *klass, void *data)
+ static const TypeInfo omap_gpio_info = {
+     .name          = TYPE_OMAP1_GPIO,
+     .parent        = TYPE_SYS_BUS_DEVICE,
+-    .instance_size = sizeof(struct omap_gpif_s),
++    .instance_size = sizeof(Omap1GpioState),
+     .instance_init = omap_gpio_init,
+     .class_init    = omap_gpio_class_init,
+ };
+--
+.34.1

-[Qemu-devel] [PULL 1/6] hw/arm/virt: Set VIRT_COMPAT_3_0 compat
+[PULL 28/38] hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name
-From: Eric Auger <eric.auger@redhat.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-We are missing the VIRT_COMPAT_3_0 definition and setting.
+Following docs/devel/style.rst guidelines, rename omap2_gpif_s ->
-Let's add them.
+Omap2GpioState. This also remove a use of 'struct' in the
 DECLARE_INSTANCE_CHECKER() macro call.
-Signed-off-by: Eric Auger <eric.auger@redhat.com>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Andrew Jones <drjones@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20181024085602.16611-1-eric.auger@redhat.com
+Message-id: 20230109140306.23161-6-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 4 ++++
+ include/hw/arm/omap.h |  9 ++++-----
-file changed, 4 insertions(+)
+ hw/gpio/omap_gpio.c   | 20 ++++++++++----------
 files changed, 14 insertions(+), 15 deletions(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/include/hw/arm/omap.h
-+++ b/hw/arm/virt.c
++++ b/include/hw/arm/omap.h
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_3_1_options(MachineClass *mc)
+@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO,
                           TYPE_OMAP1_GPIO)
  #define TYPE_OMAP2_GPIO "omap2-gpio"
 -DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
 +typedef struct Omap2GpioState Omap2GpioState;
 +DECLARE_INSTANCE_CHECKER(Omap2GpioState, OMAP2_GPIO,
                           TYPE_OMAP2_GPIO)
 -typedef struct omap2_gpif_s omap2_gpif;
 -
  /* TODO: clock framework (see above) */
  void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
 -void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
 -void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
 +void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk);
 +void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk);
  /* OMAP2 l4 Interconnect */
  struct omap_l4_s;
 diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/omap_gpio.c
 +++ b/hw/gpio/omap_gpio.c
@@ -XXX,XX +XXX,XX @@ struct omap2_gpio_s {
      uint8_t delay;
  };
 -struct omap2_gpif_s {
 +struct Omap2GpioState {
      SysBusDevice parent_obj;
      MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
  static void omap2_gpio_set(void *opaque, int line, int level)
  {
 -    struct omap2_gpif_s *p = opaque;
 +    Omap2GpioState *p = opaque;
      struct omap2_gpio_s *s = &p->modules[line >> 5];
      line &= 31;
@@ -XXX,XX +XXX,XX @@ static void omap_gpif_reset(DeviceState *dev)
  static void omap2_gpif_reset(DeviceState *dev)
  {
 -    struct omap2_gpif_s *s = OMAP2_GPIO(dev);
 +    Omap2GpioState *s = OMAP2_GPIO(dev);
      int i;
      for (i = 0; i < s->modulecount; i++) {
@@ -XXX,XX +XXX,XX @@ static void omap2_gpif_reset(DeviceState *dev)
  static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
  {
 -    struct omap2_gpif_s *s = opaque;
 +    Omap2GpioState *s = opaque;
      switch (addr) {
      case 0x00:    /* IPGENERICOCPSPL_REVISION */
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
  static void omap2_gpif_top_write(void *opaque, hwaddr addr,
                                   uint64_t value, unsigned size)
  {
 -    struct omap2_gpif_s *s = opaque;
 +    Omap2GpioState *s = opaque;
      switch (addr) {
      case 0x00:    /* IPGENERICOCPSPL_REVISION */
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_realize(DeviceState *dev, Error **errp)
  static void omap2_gpio_realize(DeviceState *dev, Error **errp)
  {
 -    struct omap2_gpif_s *s = OMAP2_GPIO(dev);
 +    Omap2GpioState *s = OMAP2_GPIO(dev);
      SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
      int i;
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_gpio_info = {
      .class_init    = omap_gpio_class_init,
  };
 -void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk)
 +void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk)
  {
      gpio->iclk = clk;
  }
- DEFINE_VIRT_MACHINE_AS_LATEST(3, 1)
+-void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk)
-+#define VIRT_COMPAT_3_0 \
++void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk)
 +    HW_COMPAT_3_0
 +
  static void virt_3_0_instance_init(Object *obj)
  {
-     virt_3_1_instance_init(obj);
+     assert(i <= 5);
-@@ -XXX,XX +XXX,XX @@ static void virt_3_0_instance_init(Object *obj)
+     gpio->fclk[i] = clk;
  static void virt_machine_3_0_options(MachineClass *mc)
  {
      virt_machine_3_1_options(mc);
 +    SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_0);
  }
- DEFINE_VIRT_MACHINE(3, 0)
  static Property omap2_gpio_properties[] = {
 -    DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
 +    DEFINE_PROP_INT32("mpu_model", Omap2GpioState, mpu_model, 0),
      DEFINE_PROP_END_OF_LIST(),
  };
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_class_init(ObjectClass *klass, void *data)
  static const TypeInfo omap2_gpio_info = {
      .name          = TYPE_OMAP2_GPIO,
      .parent        = TYPE_SYS_BUS_DEVICE,
 -    .instance_size = sizeof(struct omap2_gpif_s),
 +    .instance_size = sizeof(Omap2GpioState),
      .class_init    = omap2_gpio_class_init,
  };
 --
-.19.1
+.34.1

-New patch
+[PULL 29/38] hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 Following docs/devel/style.rst guidelines, rename
 omap_intr_handler_s -> OMAPIntcState. This also remove a
 use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230109140306.23161-7-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/omap.h |  9 ++++-----
  hw/intc/omap_intc.c   | 38 +++++++++++++++++++-------------------
 files changed, 23 insertions(+), 24 deletions(-)
 diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/omap.h
 +++ b/include/hw/arm/omap.h
@@ -XXX,XX +XXX,XX @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
  /* omap_intc.c */
  #define TYPE_OMAP_INTC "common-omap-intc"
 -typedef struct omap_intr_handler_s omap_intr_handler;
 -DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
 -                         TYPE_OMAP_INTC)
 +typedef struct OMAPIntcState OMAPIntcState;
 +DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC)
  /*
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
   * (ie the struct omap_mpu_state_s*) to do the clockname to pointer
   * translation.)
   */
 -void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk);
 -void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
 +void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk);
 +void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk);
  /* omap_i2c.c */
  #define TYPE_OMAP_I2C "omap_i2c"
 diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/omap_intc.c
 +++ b/hw/intc/omap_intc.c
@@ -XXX,XX +XXX,XX @@ struct omap_intr_handler_bank_s {
      unsigned char priority[32];
  };
 -struct omap_intr_handler_s {
 +struct OMAPIntcState {
      SysBusDevice parent_obj;
      qemu_irq *pins;
@@ -XXX,XX +XXX,XX @@ struct omap_intr_handler_s {
      struct omap_intr_handler_bank_s bank[3];
  };
 -static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
 +static void omap_inth_sir_update(OMAPIntcState *s, int is_fiq)
  {
      int i, j, sir_intr, p_intr, p;
      uint32_t level;
@@ -XXX,XX +XXX,XX @@ static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
      s->sir_intr[is_fiq] = sir_intr;
  }
 -static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
 +static inline void omap_inth_update(OMAPIntcState *s, int is_fiq)
  {
      int i;
      uint32_t has_intr = 0;
@@ -XXX,XX +XXX,XX @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
  static void omap_set_intr(void *opaque, int irq, int req)
  {
 -    struct omap_intr_handler_s *ih = opaque;
 +    OMAPIntcState *ih = opaque;
      uint32_t rise;
      struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr(void *opaque, int irq, int req)
  /* Simplified version with no edge detection */
  static void omap_set_intr_noedge(void *opaque, int irq, int req)
  {
 -    struct omap_intr_handler_s *ih = opaque;
 +    OMAPIntcState *ih = opaque;
      uint32_t rise;
      struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
  static uint64_t omap_inth_read(void *opaque, hwaddr addr,
                                 unsigned size)
  {
 -    struct omap_intr_handler_s *s = opaque;
 +    OMAPIntcState *s = opaque;
      int i, offset = addr;
      int bank_no = offset >> 8;
      int line_no;
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
  static void omap_inth_write(void *opaque, hwaddr addr,
                              uint64_t value, unsigned size)
  {
 -    struct omap_intr_handler_s *s = opaque;
 +    OMAPIntcState *s = opaque;
      int i, offset = addr;
      int bank_no = offset >> 8;
      struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_inth_mem_ops = {
  static void omap_inth_reset(DeviceState *dev)
  {
 -    struct omap_intr_handler_s *s = OMAP_INTC(dev);
 +    OMAPIntcState *s = OMAP_INTC(dev);
      int i;
      for (i = 0; i < s->nbanks; ++i){
@@ -XXX,XX +XXX,XX @@ static void omap_inth_reset(DeviceState *dev)
  static void omap_intc_init(Object *obj)
  {
      DeviceState *dev = DEVICE(obj);
 -    struct omap_intr_handler_s *s = OMAP_INTC(obj);
 +    OMAPIntcState *s = OMAP_INTC(obj);
      SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
      s->nbanks = 1;
@@ -XXX,XX +XXX,XX @@ static void omap_intc_init(Object *obj)
  static void omap_intc_realize(DeviceState *dev, Error **errp)
  {
 -    struct omap_intr_handler_s *s = OMAP_INTC(dev);
 +    OMAPIntcState *s = OMAP_INTC(dev);
      if (!s->iclk) {
          error_setg(errp, "omap-intc: clk not connected");
      }
  }
 -void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk)
 +void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk)
  {
      intc->iclk = clk;
  }
 -void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk)
 +void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk)
  {
      intc->fclk = clk;
  }
  static Property omap_intc_properties[] = {
 -    DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
 +    DEFINE_PROP_UINT32("size", OMAPIntcState, size, 0x100),
      DEFINE_PROP_END_OF_LIST(),
  };
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_intc_info = {
  static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
                                  unsigned size)
  {
 -    struct omap_intr_handler_s *s = opaque;
 +    OMAPIntcState *s = opaque;
      int offset = addr;
      int bank_no, line_no;
      struct omap_intr_handler_bank_s *bank = NULL;
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
  static void omap2_inth_write(void *opaque, hwaddr addr,
                               uint64_t value, unsigned size)
  {
 -    struct omap_intr_handler_s *s = opaque;
 +    OMAPIntcState *s = opaque;
      int offset = addr;
      int bank_no, line_no;
      struct omap_intr_handler_bank_s *bank = NULL;
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_inth_mem_ops = {
  static void omap2_intc_init(Object *obj)
  {
      DeviceState *dev = DEVICE(obj);
 -    struct omap_intr_handler_s *s = OMAP_INTC(obj);
 +    OMAPIntcState *s = OMAP_INTC(obj);
      SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
      s->level_only = 1;
@@ -XXX,XX +XXX,XX @@ static void omap2_intc_init(Object *obj)
  static void omap2_intc_realize(DeviceState *dev, Error **errp)
  {
 -    struct omap_intr_handler_s *s = OMAP_INTC(dev);
 +    OMAPIntcState *s = OMAP_INTC(dev);
      if (!s->iclk) {
          error_setg(errp, "omap2-intc: iclk not connected");
@@ -XXX,XX +XXX,XX @@ static void omap2_intc_realize(DeviceState *dev, Error **errp)
  }
  static Property omap2_intc_properties[] = {
 -    DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
 +    DEFINE_PROP_UINT8("revision", OMAPIntcState,
      revision, 0x21),
      DEFINE_PROP_END_OF_LIST(),
  };
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap2_intc_info = {
  static const TypeInfo omap_intc_type_info = {
      .name          = TYPE_OMAP_INTC,
      .parent        = TYPE_SYS_BUS_DEVICE,
 -    .instance_size = sizeof(omap_intr_handler),
 +    .instance_size = sizeof(OMAPIntcState),
      .abstract      = true,
  };
 --
 .34.1

-New patch
+[PULL 30/38] hw/arm/stellaris: Drop useless casts from void * to pointer
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109140306.23161-8-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/stellaris.c | 6 +++---
+file changed, 3 insertions(+), 3 deletions(-)
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/stellaris.c
++++ b/hw/arm/stellaris.c
+@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_update(stellaris_adc_state *s)
+ static void stellaris_adc_trigger(void *opaque, int irq, int level)
+ {
+-    stellaris_adc_state *s = (stellaris_adc_state *)opaque;
++    stellaris_adc_state *s = opaque;
+     int n;
+     for (n = 0; n < 4; n++) {
+@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_reset(stellaris_adc_state *s)
+ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
+                                    unsigned size)
+ {
+-    stellaris_adc_state *s = (stellaris_adc_state *)opaque;
++    stellaris_adc_state *s = opaque;
+     /* TODO: Implement this.  */
+     if (offset >= 0x40 && offset < 0xc0) {
+@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
+ static void stellaris_adc_write(void *opaque, hwaddr offset,
+                                 uint64_t value, unsigned size)
+ {
+-    stellaris_adc_state *s = (stellaris_adc_state *)opaque;
++    stellaris_adc_state *s = opaque;
+     /* TODO: Implement this.  */
+     if (offset >= 0x40 && offset < 0xc0) {
+--
+.34.1

-New patch
+[PULL 31/38] hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Following docs/devel/style.rst guidelines, rename
+stellaris_adc_state -> StellarisADCState. This also remove a
+use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109140306.23161-9-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/stellaris.c | 73 +++++++++++++++++++++++-----------------------
+file changed, 36 insertions(+), 37 deletions(-)
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/stellaris.c
++++ b/hw/arm/stellaris.c
+@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
+ #define STELLARIS_ADC_FIFO_FULL     0x1000
+ #define TYPE_STELLARIS_ADC "stellaris-adc"
+-typedef struct StellarisADCState stellaris_adc_state;
+-DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
+-                         TYPE_STELLARIS_ADC)
++typedef struct StellarisADCState StellarisADCState;
++DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC)
+ struct StellarisADCState {
+     SysBusDevice parent_obj;
+@@ -XXX,XX +XXX,XX @@ struct StellarisADCState {
+     qemu_irq irq[4];
+ };
+-static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
++static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n)
+ {
+     int tail;
+@@ -XXX,XX +XXX,XX @@ static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
+     return s->fifo[n].data[tail];
+ }
+-static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
++static void stellaris_adc_fifo_write(StellarisADCState *s, int n,
+                                      uint32_t value)
+ {
+     int head;
+@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
+         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
+ }
+-static void stellaris_adc_update(stellaris_adc_state *s)
++static void stellaris_adc_update(StellarisADCState *s)
+ {
+     int level;
+     int n;
+@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_update(stellaris_adc_state *s)
+ static void stellaris_adc_trigger(void *opaque, int irq, int level)
+ {
+-    stellaris_adc_state *s = opaque;
++    StellarisADCState *s = opaque;
+     int n;
+     for (n = 0; n < 4; n++) {
+@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
+     }
+ }
+-static void stellaris_adc_reset(stellaris_adc_state *s)
++static void stellaris_adc_reset(StellarisADCState *s)
+ {
+     int n;
+@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_reset(stellaris_adc_state *s)
+ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
+                                    unsigned size)
+ {
+-    stellaris_adc_state *s = opaque;
++    StellarisADCState *s = opaque;
+     /* TODO: Implement this.  */
+     if (offset >= 0x40 && offset < 0xc0) {
+@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
+ static void stellaris_adc_write(void *opaque, hwaddr offset,
+                                 uint64_t value, unsigned size)
+ {
+-    stellaris_adc_state *s = opaque;
++    StellarisADCState *s = opaque;
+     /* TODO: Implement this.  */
+     if (offset >= 0x40 && offset < 0xc0) {
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_adc = {
+     .version_id = 1,
+     .minimum_version_id = 1,
+     .fields = (VMStateField[]) {
+-        VMSTATE_UINT32(actss, stellaris_adc_state),
+-        VMSTATE_UINT32(ris, stellaris_adc_state),
+-        VMSTATE_UINT32(im, stellaris_adc_state),
+-        VMSTATE_UINT32(emux, stellaris_adc_state),
+-        VMSTATE_UINT32(ostat, stellaris_adc_state),
+-        VMSTATE_UINT32(ustat, stellaris_adc_state),
+-        VMSTATE_UINT32(sspri, stellaris_adc_state),
+-        VMSTATE_UINT32(sac, stellaris_adc_state),
+-        VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
+-        VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
+-        VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
+-        VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
+-        VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
+-        VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
+-        VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
+-        VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
+-        VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
+-        VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
+-        VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
+-        VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
+-        VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
+-        VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
+-        VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
+-        VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
+-        VMSTATE_UINT32(noise, stellaris_adc_state),
++        VMSTATE_UINT32(actss, StellarisADCState),
++        VMSTATE_UINT32(ris, StellarisADCState),
++        VMSTATE_UINT32(im, StellarisADCState),
++        VMSTATE_UINT32(emux, StellarisADCState),
++        VMSTATE_UINT32(ostat, StellarisADCState),
++        VMSTATE_UINT32(ustat, StellarisADCState),
++        VMSTATE_UINT32(sspri, StellarisADCState),
++        VMSTATE_UINT32(sac, StellarisADCState),
++        VMSTATE_UINT32(fifo[0].state, StellarisADCState),
++        VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16),
++        VMSTATE_UINT32(ssmux[0], StellarisADCState),
++        VMSTATE_UINT32(ssctl[0], StellarisADCState),
++        VMSTATE_UINT32(fifo[1].state, StellarisADCState),
++        VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16),
++        VMSTATE_UINT32(ssmux[1], StellarisADCState),
++        VMSTATE_UINT32(ssctl[1], StellarisADCState),
++        VMSTATE_UINT32(fifo[2].state, StellarisADCState),
++        VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16),
++        VMSTATE_UINT32(ssmux[2], StellarisADCState),
++        VMSTATE_UINT32(ssctl[2], StellarisADCState),
++        VMSTATE_UINT32(fifo[3].state, StellarisADCState),
++        VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16),
++        VMSTATE_UINT32(ssmux[3], StellarisADCState),
++        VMSTATE_UINT32(ssctl[3], StellarisADCState),
++        VMSTATE_UINT32(noise, StellarisADCState),
+         VMSTATE_END_OF_LIST()
+     }
+ };
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_adc = {
+ static void stellaris_adc_init(Object *obj)
+ {
+     DeviceState *dev = DEVICE(obj);
+-    stellaris_adc_state *s = STELLARIS_ADC(obj);
++    StellarisADCState *s = STELLARIS_ADC(obj);
+     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+     int n;
+@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_class_init(ObjectClass *klass, void *data)
+ static const TypeInfo stellaris_adc_info = {
+     .name          = TYPE_STELLARIS_ADC,
+     .parent        = TYPE_SYS_BUS_DEVICE,
+-    .instance_size = sizeof(stellaris_adc_state),
++    .instance_size = sizeof(StellarisADCState),
+     .instance_init = stellaris_adc_init,
+     .class_init    = stellaris_adc_class_init,
+ };
+--
+.34.1

-New patch
+[PULL 32/38] hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE()
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+The typedef and definitions are generated by the OBJECT_DECLARE_TYPE
+macro in "hw/arm/bcm2836.h":
+#define TYPE_BCM283X "bcm283x"
+OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
+The script ran in commit a489d1951c ("Use OBJECT_DECLARE_TYPE when
+possible") missed them because they are declared in a different
+file unit. Remove them.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109140306.23161-10-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/bcm2836.c | 9 ++-------
+file changed, 2 insertions(+), 7 deletions(-)
+diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/bcm2836.c
++++ b/hw/arm/bcm2836.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/arm/raspi_platform.h"
+ #include "hw/sysbus.h"
+-typedef struct BCM283XClass {
++struct BCM283XClass {
+     /*< private >*/
+     DeviceClass parent_class;
+     /*< public >*/
+@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XClass {
+     hwaddr peri_base; /* Peripheral base address seen by the CPU */
+     hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
+     int clusterid;
+-} BCM283XClass;
+-
+-#define BCM283X_CLASS(klass) \
+-    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
+-#define BCM283X_GET_CLASS(obj) \
+-    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
++};
+ static Property bcm2836_enabled_cores_property =
+     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
+--
+.34.1

-New patch
+[PULL 33/38] hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 NPCM7XX models have been commited after the conversion from
 commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
 Manually convert them.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230109140306.23161-11-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/adc/npcm7xx_adc.h   |  7 +++----
  include/hw/arm/npcm7xx.h       | 18 ++++++------------
  include/hw/i2c/npcm7xx_smbus.h |  7 +++----
  include/hw/misc/npcm7xx_clk.h  |  2 +-
  include/hw/misc/npcm7xx_gcr.h  |  6 +++---
  include/hw/misc/npcm7xx_mft.h  |  7 +++----
  include/hw/misc/npcm7xx_pwm.h  |  3 +--
  include/hw/misc/npcm7xx_rng.h  |  6 +++---
  include/hw/net/npcm7xx_emc.h   |  5 +----
  include/hw/sd/npcm7xx_sdhci.h  |  4 ++--
 files changed, 26 insertions(+), 39 deletions(-)
 diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/adc/npcm7xx_adc.h
 +++ b/include/hw/adc/npcm7xx_adc.h
@@ -XXX,XX +XXX,XX @@
   * @iref: The internal reference voltage, initialized at launch time.
   * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
   */
 -typedef struct {
 +struct NPCM7xxADCState {
      SysBusDevice parent;
      MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct {
      uint32_t     iref;
      uint16_t     calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
 -} NPCM7xxADCState;
 +};
  #define TYPE_NPCM7XX_ADC "npcm7xx-adc"
 -#define NPCM7XX_ADC(obj) \
 -    OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
 +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxADCState, NPCM7XX_ADC)
  #endif /* NPCM7XX_ADC_H */
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/npcm7xx.h
 +++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
  #define NPCM7XX_NR_PWM_MODULES 2
 -typedef struct NPCM7xxMachine {
 +struct NPCM7xxMachine {
      MachineState        parent;
      /*
       * PWM fan splitter. each splitter connects to one PWM output and
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMachine {
       */
      SplitIRQ            fan_splitter[NPCM7XX_NR_PWM_MODULES *
                                       NPCM7XX_PWM_PER_MODULE];
 -} NPCM7xxMachine;
 +};
  #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
 -#define NPCM7XX_MACHINE(obj)                                            \
 -    OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
 +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMachine, NPCM7XX_MACHINE)
  typedef struct NPCM7xxMachineClass {
      MachineClass        parent;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMachineClass {
  #define NPCM7XX_MACHINE_GET_CLASS(obj)                                  \
      OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
 -typedef struct NPCM7xxState {
 +struct NPCM7xxState {
      DeviceState         parent;
      ARMCPU              cpu[NPCM7XX_MAX_NUM_CPUS];
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
      NPCM7xxFIUState     fiu[2];
      NPCM7xxEMCState     emc[2];
      NPCM7xxSDHCIState   mmc;
 -} NPCM7xxState;
 +};
  #define TYPE_NPCM7XX    "npcm7xx"
 -#define NPCM7XX(obj)    OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
 +OBJECT_DECLARE_TYPE(NPCM7xxState, NPCM7xxClass, NPCM7XX)
  #define TYPE_NPCM730    "npcm730"
  #define TYPE_NPCM750    "npcm750"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxClass {
      uint32_t            num_cpus;
  } NPCM7xxClass;
 -#define NPCM7XX_CLASS(klass)                                            \
 -    OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
 -#define NPCM7XX_GET_CLASS(obj)                                          \
 -    OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
 -
  /**
   * npcm7xx_load_kernel - Loads memory with everything needed to boot
   * @machine - The machine containing the SoC to be booted.
 diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/i2c/npcm7xx_smbus.h
 +++ b/include/hw/i2c/npcm7xx_smbus.h
@@ -XXX,XX +XXX,XX @@ typedef enum NPCM7xxSMBusStatus {
   * @rx_cur: The current position of rx_fifo.
   * @status: The current status of the SMBus.
   */
 -typedef struct NPCM7xxSMBusState {
 +struct NPCM7xxSMBusState {
      SysBusDevice parent;
      MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxSMBusState {
      uint8_t      rx_cur;
      NPCM7xxSMBusStatus status;
 -} NPCM7xxSMBusState;
 +};
  #define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
 -#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \
 -                                        TYPE_NPCM7XX_SMBUS)
 +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxSMBusState, NPCM7XX_SMBUS)
  #endif /* NPCM7XX_SMBUS_H */
 diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/misc/npcm7xx_clk.h
 +++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxCLKState {
  };
  #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
 -#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
 +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
  #endif /* NPCM7XX_CLK_H */
 diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/misc/npcm7xx_gcr.h
 +++ b/include/hw/misc/npcm7xx_gcr.h
@@ -XXX,XX +XXX,XX @@
   */
  #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
 -typedef struct NPCM7xxGCRState {
 +struct NPCM7xxGCRState {
      SysBusDevice parent;
      MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxGCRState {
      uint32_t reset_pwron;
      uint32_t reset_mdlr;
      uint32_t reset_intcr3;
 -} NPCM7xxGCRState;
 +};
  #define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
 -#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
 +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR)
  #endif /* NPCM7XX_GCR_H */
 diff --git a/include/hw/misc/npcm7xx_mft.h b/include/hw/misc/npcm7xx_mft.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/misc/npcm7xx_mft.h
 +++ b/include/hw/misc/npcm7xx_mft.h
@@ -XXX,XX +XXX,XX @@
   * @max_rpm: The maximum rpm for fans. Order: A0, B0, A1, B1.
   * @duty: The duty cycles for fans, relative to NPCM7XX_PWM_MAX_DUTY.
   */
 -typedef struct NPCM7xxMFTState {
 +struct NPCM7xxMFTState {
      SysBusDevice parent;
      MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMFTState {
      uint32_t    max_rpm[NPCM7XX_MFT_FANIN_COUNT];
      uint32_t    duty[NPCM7XX_MFT_FANIN_COUNT];
 -} NPCM7xxMFTState;
 +};
  #define TYPE_NPCM7XX_MFT "npcm7xx-mft"
 -#define NPCM7XX_MFT(obj) \
 -    OBJECT_CHECK(NPCM7xxMFTState, (obj), TYPE_NPCM7XX_MFT)
 +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMFTState, NPCM7XX_MFT)
  #endif /* NPCM7XX_MFT_H */
 diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/misc/npcm7xx_pwm.h
 +++ b/include/hw/misc/npcm7xx_pwm.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxPWMState {
  };
  #define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
 -#define NPCM7XX_PWM(obj) \
 -    OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
 +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxPWMState, NPCM7XX_PWM)
  #endif /* NPCM7XX_PWM_H */
 diff --git a/include/hw/misc/npcm7xx_rng.h b/include/hw/misc/npcm7xx_rng.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/misc/npcm7xx_rng.h
 +++ b/include/hw/misc/npcm7xx_rng.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/sysbus.h"
 -typedef struct NPCM7xxRNGState {
 +struct NPCM7xxRNGState {
      SysBusDevice parent;
      MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxRNGState {
      uint8_t rngcs;
      uint8_t rngd;
      uint8_t rngmode;
 -} NPCM7xxRNGState;
 +};
  #define TYPE_NPCM7XX_RNG "npcm7xx-rng"
 -#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
 +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxRNGState, NPCM7XX_RNG)
  #endif /* NPCM7XX_RNG_H */
 diff --git a/include/hw/net/npcm7xx_emc.h b/include/hw/net/npcm7xx_emc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/net/npcm7xx_emc.h
 +++ b/include/hw/net/npcm7xx_emc.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxEMCState {
      bool rx_active;
  };
 -typedef struct NPCM7xxEMCState NPCM7xxEMCState;
 -
  #define TYPE_NPCM7XX_EMC "npcm7xx-emc"
 -#define NPCM7XX_EMC(obj) \
 -    OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC)
 +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxEMCState, NPCM7XX_EMC)
  #endif /* NPCM7XX_EMC_H */
 diff --git a/include/hw/sd/npcm7xx_sdhci.h b/include/hw/sd/npcm7xx_sdhci.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/sd/npcm7xx_sdhci.h
 +++ b/include/hw/sd/npcm7xx_sdhci.h
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxRegs {
      uint32_t boottoctrl;
  } NPCM7xxRegisters;
 -typedef struct NPCM7xxSDHCIState {
 +struct NPCM7xxSDHCIState {
      SysBusDevice parent;
      MemoryRegion container;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxSDHCIState {
      NPCM7xxRegisters regs;
      SDHCIState sdhci;
 -} NPCM7xxSDHCIState;
 +};
  #endif /* NPCM7XX_SDHCI_H */
 --
 .34.1

-New patch
+[PULL 34/38] hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+The structure is named SECUREECState. Rename the type accordingly.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109140306.23161-12-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/misc/sbsa_ec.c | 13 +++++++------
+file changed, 7 insertions(+), 6 deletions(-)
+diff --git a/hw/misc/sbsa_ec.c b/hw/misc/sbsa_ec.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/misc/sbsa_ec.c
++++ b/hw/misc/sbsa_ec.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "sysemu/runstate.h"
+-typedef struct {
++typedef struct SECUREECState {
+     SysBusDevice parent_obj;
+     MemoryRegion iomem;
+ } SECUREECState;
+-#define TYPE_SBSA_EC      "sbsa-ec"
+-#define SECURE_EC(obj) OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_EC)
++#define TYPE_SBSA_SECURE_EC "sbsa-ec"
++#define SBSA_SECURE_EC(obj) \
++        OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_SECURE_EC)
+ enum sbsa_ec_powerstates {
+     SBSA_EC_CMD_POWEROFF = 0x01,
+@@ -XXX,XX +XXX,XX @@ static uint64_t sbsa_ec_read(void *opaque, hwaddr offset, unsigned size)
+ }
+ static void sbsa_ec_write(void *opaque, hwaddr offset,
+-                     uint64_t value, unsigned size)
++                          uint64_t value, unsigned size)
+ {
+     if (offset == 0) { /* PSCI machine power command register */
+         switch (value) {
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sbsa_ec_ops = {
+ static void sbsa_ec_init(Object *obj)
+ {
+-    SECUREECState *s = SECURE_EC(obj);
++    SECUREECState *s = SBSA_SECURE_EC(obj);
+     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+     memory_region_init_io(&s->iomem, obj, &sbsa_ec_ops, s, "sbsa-ec",
+@@ -XXX,XX +XXX,XX @@ static void sbsa_ec_class_init(ObjectClass *klass, void *data)
+ }
+ static const TypeInfo sbsa_ec_info = {
+-    .name          = TYPE_SBSA_EC,
++    .name          = TYPE_SBSA_SECURE_EC,
+     .parent        = TYPE_SYS_BUS_DEVICE,
+     .instance_size = sizeof(SECUREECState),
+     .instance_init = sbsa_ec_init,
+--
+.34.1

-New patch
+[PULL 35/38] hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+This model was merged few days before the QOM cleanup from
+commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible")
+was pulled and merged. Manually adapt.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230109140306.23161-13-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/misc/sbsa_ec.c | 3 +--
+file changed, 1 insertion(+), 2 deletions(-)
+diff --git a/hw/misc/sbsa_ec.c b/hw/misc/sbsa_ec.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/misc/sbsa_ec.c
++++ b/hw/misc/sbsa_ec.c
+@@ -XXX,XX +XXX,XX @@ typedef struct SECUREECState {
+ } SECUREECState;
+ #define TYPE_SBSA_SECURE_EC "sbsa-ec"
+-#define SBSA_SECURE_EC(obj) \
+-        OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_SECURE_EC)
++OBJECT_DECLARE_SIMPLE_TYPE(SECUREECState, SBSA_SECURE_EC)
+ enum sbsa_ec_powerstates {
+     SBSA_EC_CMD_POWEROFF = 0x01,
+--
+.34.1

-New patch
+[PULL 36/38] hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic'
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
+macro call, to avoid after a QOM refactor:
+  hw/intc/xilinx_intc.c:45:1: error: declaration of anonymous struct must be a definition
+  DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
+                           ^
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
+Message-id: 20230109140306.23161-14-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/intc/xilinx_intc.c | 28 +++++++++++++---------------
+file changed, 13 insertions(+), 15 deletions(-)
+diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/xilinx_intc.c
++++ b/hw/intc/xilinx_intc.c
+@@ -XXX,XX +XXX,XX @@
+ #define R_MAX       8
+ #define TYPE_XILINX_INTC "xlnx.xps-intc"
+-DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
+-                         TYPE_XILINX_INTC)
++typedef struct XpsIntc XpsIntc;
++DECLARE_INSTANCE_CHECKER(XpsIntc, XILINX_INTC, TYPE_XILINX_INTC)
+-struct xlx_pic
++struct XpsIntc
+ {
+     SysBusDevice parent_obj;
+@@ -XXX,XX +XXX,XX @@ struct xlx_pic
+     uint32_t irq_pin_state;
+ };
+-static void update_irq(struct xlx_pic *p)
++static void update_irq(XpsIntc *p)
+ {
+     uint32_t i;
+@@ -XXX,XX +XXX,XX @@ static void update_irq(struct xlx_pic *p)
+     qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
+ }
+-static uint64_t
+-pic_read(void *opaque, hwaddr addr, unsigned int size)
++static uint64_t pic_read(void *opaque, hwaddr addr, unsigned int size)
+ {
+-    struct xlx_pic *p = opaque;
++    XpsIntc *p = opaque;
+     uint32_t r = 0;
+     addr >>= 2;
+@@ -XXX,XX +XXX,XX @@ pic_read(void *opaque, hwaddr addr, unsigned int size)
+     return r;
+ }
+-static void
+-pic_write(void *opaque, hwaddr addr,
+-          uint64_t val64, unsigned int size)
++static void pic_write(void *opaque, hwaddr addr,
++                      uint64_t val64, unsigned int size)
+ {
+-    struct xlx_pic *p = opaque;
++    XpsIntc *p = opaque;
+     uint32_t value = val64;
+     addr >>= 2;
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pic_ops = {
+ static void irq_handler(void *opaque, int irq, int level)
+ {
+-    struct xlx_pic *p = opaque;
++    XpsIntc *p = opaque;
+     /* edge triggered interrupt */
+     if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
+@@ -XXX,XX +XXX,XX @@ static void irq_handler(void *opaque, int irq, int level)
+ static void xilinx_intc_init(Object *obj)
+ {
+-    struct xlx_pic *p = XILINX_INTC(obj);
++    XpsIntc *p = XILINX_INTC(obj);
+     qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
+     sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
+@@ -XXX,XX +XXX,XX @@ static void xilinx_intc_init(Object *obj)
+ }
+ static Property xilinx_intc_properties[] = {
+-    DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
++    DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
+     DEFINE_PROP_END_OF_LIST(),
+ };
+@@ -XXX,XX +XXX,XX @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data)
+ static const TypeInfo xilinx_intc_info = {
+     .name          = TYPE_XILINX_INTC,
+     .parent        = TYPE_SYS_BUS_DEVICE,
+-    .instance_size = sizeof(struct xlx_pic),
++    .instance_size = sizeof(XpsIntc),
+     .instance_init = xilinx_intc_init,
+     .class_init    = xilinx_intc_class_init,
+ };
+--
+.34.1

-[Qemu-devel] [PULL 6/6] tests/boot-serial-test: Add microbit board testcase
+[PULL 37/38] hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock'
-From: Julia Suvorova via Qemu-devel <qemu-devel@nongnu.org>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-New mini-kernel test for nRF51 SoC UART.
+This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
 macro call, to avoid after a QOM refactor:
-Signed-off-by: Julia Suvorova <jusual@mail.ru>
+  hw/timer/xilinx_timer.c:65:1: error: declaration of anonymous struct must be a definition
-Acked-by: Thomas Huth <thuth@redhat.com>
+  DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
-Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
+                           ^
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
 Message-id: 20230109140306.23161-15-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/boot-serial-test.c | 19 +++++++++++++++++++
+ hw/timer/xilinx_timer.c | 27 +++++++++++++--------------
-file changed, 19 insertions(+)
+file changed, 13 insertions(+), 14 deletions(-)
-diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
+diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/boot-serial-test.c
+--- a/hw/timer/xilinx_timer.c
-+++ b/tests/boot-serial-test.c
++++ b/hw/timer/xilinx_timer.c
-@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_aarch64[] = {
+@@ -XXX,XX +XXX,XX @@ struct xlx_timer
 xfd, 0xff, 0xff, 0x17,                 /* b       -12 (loop) */
  };
-+static const uint8_t kernel_nrf51[] = {
+ #define TYPE_XILINX_TIMER "xlnx.xps-timer"
-+    0x00, 0x00, 0x00, 0x00,                 /* Stack top address */
+-DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
-+    0x09, 0x00, 0x00, 0x00,                 /* Reset handler address */
+-                         TYPE_XILINX_TIMER)
-+    0x04, 0x4a,                             /* ldr  r2, [pc, #16] Get ENABLE */
++typedef struct XpsTimerState XpsTimerState;
-+    0x04, 0x21,                             /* movs r1, #4 */
++DECLARE_INSTANCE_CHECKER(XpsTimerState, XILINX_TIMER, TYPE_XILINX_TIMER)
-+    0x11, 0x60,                             /* str  r1, [r2] */
-+    0x04, 0x4a,                             /* ldr  r2, [pc, #16] Get STARTTX */
+-struct timerblock
-+    0x01, 0x21,                             /* movs r1, #1 */
++struct XpsTimerState
-+    0x11, 0x60,                             /* str  r1, [r2] */
+ {
-+    0x03, 0x4a,                             /* ldr  r2, [pc, #12] Get TXD */
+     SysBusDevice parent_obj;
-+    0x54, 0x21,                             /* movs r1, 'T' */
-+    0x11, 0x60,                             /* str  r1, [r2] */
+@@ -XXX,XX +XXX,XX @@ struct timerblock
-+    0xfe, 0xe7,                             /* b    . */
+     struct xlx_timer *timers;
-+    0x00, 0x25, 0x00, 0x40,                 /* 0x40002500 = UART ENABLE */
+ };
-+    0x08, 0x20, 0x00, 0x40,                 /* 0x40002008 = UART STARTTX */
-+    0x1c, 0x25, 0x00, 0x40                  /* 0x4000251c = UART TXD */
+-static inline unsigned int num_timers(struct timerblock *t)
-+};
++static inline unsigned int num_timers(XpsTimerState *t)
-+
+ {
- typedef struct testdef {
+     return 2 - t->one_timer_only;
-     const char *arch;       /* Target architecture */
+ }
-     const char *machine;    /* Name of the machine */
+@@ -XXX,XX +XXX,XX @@ static inline unsigned int timer_from_addr(hwaddr addr)
-@@ -XXX,XX +XXX,XX @@ static testdef_t tests[] = {
+     return addr >> 2;
-     { "hppa", "hppa", "", "SeaBIOS wants SYSTEM HALT" },
+ }
-     { "aarch64", "virt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64),
-       kernel_aarch64 },
+-static void timer_update_irq(struct timerblock *t)
-+    { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
++static void timer_update_irq(XpsTimerState *t)
+ {
-     { NULL }
+     unsigned int i, irq = 0;
      uint32_t csr;
@@ -XXX,XX +XXX,XX @@ static void timer_update_irq(struct timerblock *t)
  static uint64_t
  timer_read(void *opaque, hwaddr addr, unsigned int size)
  {
 -    struct timerblock *t = opaque;
 +    XpsTimerState *t = opaque;
      struct xlx_timer *xt;
      uint32_t r = 0;
      unsigned int timer;
@@ -XXX,XX +XXX,XX @@ static void
  timer_write(void *opaque, hwaddr addr,
              uint64_t val64, unsigned int size)
  {
 -    struct timerblock *t = opaque;
 +    XpsTimerState *t = opaque;
      struct xlx_timer *xt;
      unsigned int timer;
      uint32_t value = val64;
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps timer_ops = {
  static void timer_hit(void *opaque)
  {
      struct xlx_timer *xt = opaque;
 -    struct timerblock *t = xt->parent;
 +    XpsTimerState *t = xt->parent;
      D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
      xt->regs[R_TCSR] |= TCSR_TINT;
@@ -XXX,XX +XXX,XX @@ static void timer_hit(void *opaque)
  static void xilinx_timer_realize(DeviceState *dev, Error **errp)
  {
 -    struct timerblock *t = XILINX_TIMER(dev);
 +    XpsTimerState *t = XILINX_TIMER(dev);
      unsigned int i;
      /* Init all the ptimers.  */
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
  static void xilinx_timer_init(Object *obj)
  {
 -    struct timerblock *t = XILINX_TIMER(obj);
 +    XpsTimerState *t = XILINX_TIMER(obj);
      /* All timers share a single irq line.  */
      sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
  }
  static Property xilinx_timer_properties[] = {
 -    DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
 -                                                                62 * 1000000),
 -    DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
 +    DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000),
 +    DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0),
      DEFINE_PROP_END_OF_LIST(),
  };
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_class_init(ObjectClass *klass, void *data)
  static const TypeInfo xilinx_timer_info = {
      .name          = TYPE_XILINX_TIMER,
      .parent        = TYPE_SYS_BUS_DEVICE,
 -    .instance_size = sizeof(struct timerblock),
 +    .instance_size = sizeof(XpsTimerState),
      .instance_init = xilinx_timer_init,
      .class_init    = xilinx_timer_class_init,
  };
 --
-.19.1
+.34.1

-New patch
+[PULL 38/38] target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
+From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
+ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit
+to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu
+uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3
+write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is
+enabled and exposed to the guest. As a result EL3 writes of that bit are
+ignored.
+Cc: qemu-stable@nongnu.org
+Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
+Message-id: 20230105221251.17896-4-eiakovlev@linux.microsoft.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.c | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+         if (cpu_isar_feature(aa64_sme, cpu)) {
+             valid_mask |= SCR_ENTP2;
+         }
++        if (cpu_isar_feature(aa64_hcx, cpu)) {
++            valid_mask |= SCR_HXEN;
++        }
+     } else {
+         valid_mask &= ~(SCR_RW | SCR_ST);
+         if (cpu_isar_feature(aa32_ras, cpu)) {
+--
+.34.1

Last lot of patches for arm before softfreeze tomorrow...

thanks
-- PMM

The following changes since commit ef3a6af5e789ff078d1fef880f9dfb6adf18e8f1:

Merge remote-tracking branch 'remotes/kraxel/tags/vga-20181029-pull-request' into staging (2018-10-29 12:59:15 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181029

for you to fetch changes up to 20cf5663734310a282e27b7389bc9f53ffe227e6:

tests/boot-serial-test: Add microbit board testcase (2018-10-29 15:19:48 +0000)

----------------------------------------------------------------
target-arm queue:
 * microbit: Add the UART to our nRF51 SoC model
 * Add a virtual Xilinx Versal board "xlnx-versal-virt"
 * hw/arm/virt: Set VIRT_COMPAT_3_0 compat

----------------------------------------------------------------
Edgar E. Iglesias (2):
      hw/arm: versal: Add a model of Xilinx Versal SoC
      hw/arm: versal: Add a virtual Xilinx Versal board

Eric Auger (1):
      hw/arm/virt: Set VIRT_COMPAT_3_0 compat

Julia Suvorova (3):
      hw/char: Implement nRF51 SoC UART
      hw/arm/nrf51_soc: Connect UART to nRF51 SoC
      tests/boot-serial-test: Add microbit board testcase

hw/arm/Makefile.objs                |   1 +
 hw/char/Makefile.objs               |   1 +
 include/hw/arm/nrf51_soc.h          |   3 +
 include/hw/arm/xlnx-versal.h        | 122 +++++++++
 include/hw/char/nrf51_uart.h        |  78 ++++++
 hw/arm/microbit.c                   |   2 +
 hw/arm/nrf51_soc.c                  |  20 ++
 hw/arm/virt.c                       |   4 +
 hw/arm/xlnx-versal-virt.c           | 493 ++++++++++++++++++++++++++++++++++++
 hw/arm/xlnx-versal.c                | 323 +++++++++++++++++++++++
 hw/char/nrf51_uart.c                | 330 ++++++++++++++++++++++++
 tests/boot-serial-test.c            |  19 ++
 default-configs/aarch64-softmmu.mak |   1 +
 hw/char/trace-events                |   4 +
 14 files changed, 1401 insertions(+)
 create mode 100644 include/hw/arm/xlnx-versal.h
 create mode 100644 include/hw/char/nrf51_uart.h
 create mode 100644 hw/arm/xlnx-versal-virt.c
 create mode 100644 hw/arm/xlnx-versal.c
 create mode 100644 hw/char/nrf51_uart.c

From: Eric Auger <eric.auger@redhat.com>

We are missing the VIRT_COMPAT_3_0 definition and setting.
Let's add them.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20181024085602.16611-1-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_3_1_options(MachineClass *mc)
 }
 DEFINE_VIRT_MACHINE_AS_LATEST(3, 1)
 
+#define VIRT_COMPAT_3_0 \
+    HW_COMPAT_3_0
+
 static void virt_3_0_instance_init(Object *obj)
 {
     virt_3_1_instance_init(obj);
@@ -XXX,XX +XXX,XX @@ static void virt_3_0_instance_init(Object *obj)
 static void virt_machine_3_0_options(MachineClass *mc)
 {
     virt_machine_3_1_options(mc);
+    SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_0);
 }
 DEFINE_VIRT_MACHINE(3, 0)
 
-- 
2.19.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add a model of Xilinx Versal SoC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/Makefile.objs                |   1 +
 include/hw/arm/xlnx-versal.h        | 122 +++++++++++
 hw/arm/xlnx-versal.c                | 323 ++++++++++++++++++++++++++++
 default-configs/aarch64-softmmu.mak |   1 +
 4 files changed, 447 insertions(+)
 create mode 100644 include/hw/arm/xlnx-versal.h
 create mode 100644 hw/arm/xlnx-versal.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
 obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
 obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
 obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
+obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o
 obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
 obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
 obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Model of the Xilinx Versal
+ *
+ * Copyright (c) 2018 Xilinx Inc.
+ * Written by Edgar E. Iglesias
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#ifndef XLNX_VERSAL_H
+#define XLNX_VERSAL_H
+
+#include "hw/sysbus.h"
+#include "hw/arm/arm.h"
+#include "hw/intc/arm_gicv3.h"
+
+#define TYPE_XLNX_VERSAL "xlnx-versal"
+#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
+
+#define XLNX_VERSAL_NR_ACPUS   2
+#define XLNX_VERSAL_NR_UARTS   2
+#define XLNX_VERSAL_NR_GEMS    2
+#define XLNX_VERSAL_NR_IRQS    256
+
+typedef struct Versal {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    struct {
+        struct {
+            MemoryRegion mr;
+            ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
+            GICv3State gic;
+        } apu;
+    } fpd;
+
+    MemoryRegion mr_ps;
+
+    struct {
+        /* 4 ranges to access DDR.  */
+        MemoryRegion mr_ddr_ranges[4];
+    } noc;
+
+    struct {
+        MemoryRegion mr_ocm;
+
+        struct {
+            SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
+            SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
+        } iou;
+    } lpd;
+
+    struct {
+        MemoryRegion *mr_ddr;
+        uint32_t psci_conduit;
+    } cfg;
+} Versal;
+
+/* Memory-map and IRQ definitions. Copied a subset from
+ * auto-generated files.  */
+
+#define VERSAL_GIC_MAINT_IRQ        9
+#define VERSAL_TIMER_VIRT_IRQ       11
+#define VERSAL_TIMER_S_EL1_IRQ      13
+#define VERSAL_TIMER_NS_EL1_IRQ     14
+#define VERSAL_TIMER_NS_EL2_IRQ     10
+
+#define VERSAL_UART0_IRQ_0         18
+#define VERSAL_UART1_IRQ_0         19
+#define VERSAL_GEM0_IRQ_0          56
+#define VERSAL_GEM0_WAKE_IRQ_0     57
+#define VERSAL_GEM1_IRQ_0          58
+#define VERSAL_GEM1_WAKE_IRQ_0     59
+
+/* Architecturally eserved IRQs suitable for virtualization.  */
+#define VERSAL_RSVD_HIGH_IRQ_FIRST 160
+#define VERSAL_RSVD_HIGH_IRQ_LAST  255
+
+#define MM_TOP_RSVD                 0xa0000000U
+#define MM_TOP_RSVD_SIZE            0x4000000
+#define MM_GIC_APU_DIST_MAIN        0xf9000000U
+#define MM_GIC_APU_DIST_MAIN_SIZE   0x10000
+#define MM_GIC_APU_REDIST_0         0xf9080000U
+#define MM_GIC_APU_REDIST_0_SIZE    0x80000
+
+#define MM_UART0                    0xff000000U
+#define MM_UART0_SIZE               0x10000
+#define MM_UART1                    0xff010000U
+#define MM_UART1_SIZE               0x10000
+
+#define MM_GEM0                     0xff0c0000U
+#define MM_GEM0_SIZE                0x10000
+#define MM_GEM1                     0xff0d0000U
+#define MM_GEM1_SIZE                0x10000
+
+#define MM_OCM                      0xfffc0000U
+#define MM_OCM_SIZE                 0x40000
+
+#define MM_TOP_DDR                  0x0
+#define MM_TOP_DDR_SIZE             0x80000000U
+#define MM_TOP_DDR_2                0x800000000ULL
+#define MM_TOP_DDR_2_SIZE           0x800000000ULL
+#define MM_TOP_DDR_3                0xc000000000ULL
+#define MM_TOP_DDR_3_SIZE           0x4000000000ULL
+#define MM_TOP_DDR_4                0x10000000000ULL
+#define MM_TOP_DDR_4_SIZE           0xb780000000ULL
+
+#define MM_PSM_START                0xffc80000U
+#define MM_PSM_END                  0xffcf0000U
+
+#define MM_CRL                      0xff5e0000U
+#define MM_CRL_SIZE                 0x300000
+#define MM_IOU_SCNTR                0xff130000U
+#define MM_IOU_SCNTR_SIZE           0x10000
+#define MM_IOU_SCNTRS               0xff140000U
+#define MM_IOU_SCNTRS_SIZE          0x10000
+#define MM_FPD_CRF                  0xfd1a0000U
+#define MM_FPD_CRF_SIZE             0x140000
+#endif
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Xilinx Versal SoC model.
+ *
+ * Copyright (c) 2018 Xilinx Inc.
+ * Written by Edgar E. Iglesias
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "qemu/log.h"
+#include "hw/sysbus.h"
+#include "net/net.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
+#include "hw/arm/arm.h"
+#include "kvm_arm.h"
+#include "hw/misc/unimp.h"
+#include "hw/intc/arm_gicv3_common.h"
+#include "hw/arm/xlnx-versal.h"
+
+#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
+#define GEM_REVISION        0x40070106
+
+static void versal_create_apu_cpus(Versal *s)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
+        Object *obj;
+        char *name;
+
+        obj = object_new(XLNX_VERSAL_ACPU_TYPE);
+        if (!obj) {
+            /* Secondary CPUs start in PSCI powered-down state */
+            error_report("Unable to create apu.cpu[%d] of type %s",
+                         i, XLNX_VERSAL_ACPU_TYPE);
+            exit(EXIT_FAILURE);
+        }
+
+        name = g_strdup_printf("apu-cpu[%d]", i);
+        object_property_add_child(OBJECT(s), name, obj, &error_fatal);
+        g_free(name);
+
+        object_property_set_int(obj, s->cfg.psci_conduit,
+                                "psci-conduit", &error_abort);
+        if (i) {
+            object_property_set_bool(obj, true,
+                                     "start-powered-off", &error_abort);
+        }
+
+        object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu),
+                                "core-count", &error_abort);
+        object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
+                                 &error_abort);
+        object_property_set_bool(obj, true, "realized", &error_fatal);
+        s->fpd.apu.cpu[i] = ARM_CPU(obj);
+    }
+}
+
+static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
+{
+    static const uint64_t addrs[] = {
+        MM_GIC_APU_DIST_MAIN,
+        MM_GIC_APU_REDIST_0
+    };
+    SysBusDevice *gicbusdev;
+    DeviceState *gicdev;
+    int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
+    int i;
+
+    sysbus_init_child_obj(OBJECT(s), "apu-gic",
+                          &s->fpd.apu.gic, sizeof(s->fpd.apu.gic),
+                          gicv3_class_name());
+    gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
+    gicdev = DEVICE(&s->fpd.apu.gic);
+    qdev_prop_set_uint32(gicdev, "revision", 3);
+    qdev_prop_set_uint32(gicdev, "num-cpu", 2);
+    qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);
+    qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
+    qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2);
+    qdev_prop_set_bit(gicdev, "has-security-extensions", true);
+
+    object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized",
+                                    &error_fatal);
+
+    for (i = 0; i < ARRAY_SIZE(addrs); i++) {
+        MemoryRegion *mr;
+
+        mr = sysbus_mmio_get_region(gicbusdev, i);
+        memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);
+    }
+
+    for (i = 0; i < nr_apu_cpus; i++) {
+        DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);
+        int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
+        qemu_irq maint_irq;
+        int ti;
+        /* Mapping from the output timer irq lines from the CPU to the
+         * GIC PPI inputs.
+         */
+        const int timer_irq[] = {
+            [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
+            [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
+            [GTIMER_HYP]  = VERSAL_TIMER_NS_EL2_IRQ,
+            [GTIMER_SEC]  = VERSAL_TIMER_S_EL1_IRQ,
+        };
+
+        for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {
+            qdev_connect_gpio_out(cpudev, ti,
+                                  qdev_get_gpio_in(gicdev,
+                                                   ppibase + timer_irq[ti]));
+        }
+        maint_irq = qdev_get_gpio_in(gicdev,
+                                        ppibase + VERSAL_GIC_MAINT_IRQ);
+        qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
+                                    0, maint_irq);
+        sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
+        sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,
+                           qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
+        sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,
+                           qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
+        sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,
+                           qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
+    }
+
+    for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {
+        pic[i] = qdev_get_gpio_in(gicdev, i);
+    }
+}
+
+static void versal_create_uarts(Versal *s, qemu_irq *pic)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
+        static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};
+        static const uint64_t addrs[] = { MM_UART0, MM_UART1 };
+        char *name = g_strdup_printf("uart%d", i);
+        DeviceState *dev;
+        MemoryRegion *mr;
+
+        dev = qdev_create(NULL, "pl011");
+        s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);
+        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
+        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
+        qdev_init_nofail(dev);
+
+        mr = sysbus_mmio_get_region(s->lpd.iou.uart[i], 0);
+        memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
+
+        sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]);
+        g_free(name);
+    }
+}
+
+static void versal_create_gems(Versal *s, qemu_irq *pic)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
+        static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0};
+        static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 };
+        char *name = g_strdup_printf("gem%d", i);
+        NICInfo *nd = &nd_table[i];
+        DeviceState *dev;
+        MemoryRegion *mr;
+
+        dev = qdev_create(NULL, "cadence_gem");
+        s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);
+        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
+        if (nd->used) {
+            qemu_check_nic_model(nd, "cadence_gem");
+            qdev_set_nic_properties(dev, nd);
+        }
+        object_property_set_int(OBJECT(s->lpd.iou.gem[i]),
+                                2, "num-priority-queues",
+                                &error_abort);
+        object_property_set_link(OBJECT(s->lpd.iou.gem[i]),
+                                 OBJECT(&s->mr_ps), "dma",
+                                 &error_abort);
+        qdev_init_nofail(dev);
+
+        mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);
+        memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
+
+        sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);
+        g_free(name);
+    }
+}
+
+/* This takes the board allocated linear DDR memory and creates aliases
+ * for each split DDR range/aperture on the Versal address map.
+ */
+static void versal_map_ddr(Versal *s)
+{
+    uint64_t size = memory_region_size(s->cfg.mr_ddr);
+    /* Describes the various split DDR access regions.  */
+    static const struct {
+        uint64_t base;
+        uint64_t size;
+    } addr_ranges[] = {
+        { MM_TOP_DDR, MM_TOP_DDR_SIZE },
+        { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
+        { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
+        { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
+    };
+    uint64_t offset = 0;
+    int i;
+
+    assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges));
+    for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
+        char *name;
+        uint64_t mapsize;
+
+        mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
+        name = g_strdup_printf("noc-ddr-range%d", i);
+        /* Create the MR alias.  */
+        memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s),
+                                 name, s->cfg.mr_ddr,
+                                 offset, mapsize);
+
+        /* Map it onto the NoC MR.  */
+        memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base,
+                                    &s->noc.mr_ddr_ranges[i]);
+        offset += mapsize;
+        size -= mapsize;
+        g_free(name);
+    }
+}
+
+static void versal_unimp_area(Versal *s, const char *name,
+                                MemoryRegion *mr,
+                                hwaddr base, hwaddr size)
+{
+    DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
+    MemoryRegion *mr_dev;
+
+    qdev_prop_set_string(dev, "name", name);
+    qdev_prop_set_uint64(dev, "size", size);
+    object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
+    qdev_init_nofail(dev);
+
+    mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+    memory_region_add_subregion(mr, base, mr_dev);
+}
+
+static void versal_unimp(Versal *s)
+{
+    versal_unimp_area(s, "psm", &s->mr_ps,
+                        MM_PSM_START, MM_PSM_END - MM_PSM_START);
+    versal_unimp_area(s, "crl", &s->mr_ps,
+                        MM_CRL, MM_CRL_SIZE);
+    versal_unimp_area(s, "crf", &s->mr_ps,
+                        MM_FPD_CRF, MM_FPD_CRF_SIZE);
+    versal_unimp_area(s, "iou-scntr", &s->mr_ps,
+                        MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
+    versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
+                        MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);
+}
+
+static void versal_realize(DeviceState *dev, Error **errp)
+{
+    Versal *s = XLNX_VERSAL(dev);
+    qemu_irq pic[XLNX_VERSAL_NR_IRQS];
+
+    versal_create_apu_cpus(s);
+    versal_create_apu_gic(s, pic);
+    versal_create_uarts(s, pic);
+    versal_create_gems(s, pic);
+    versal_map_ddr(s);
+    versal_unimp(s);
+
+    /* Create the On Chip Memory (OCM).  */
+    memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
+                           MM_OCM_SIZE, &error_fatal);
+
+    memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
+    memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
+}
+
+static void versal_init(Object *obj)
+{
+    Versal *s = XLNX_VERSAL(obj);
+
+    memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
+    memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
+}
+
+static Property versal_properties[] = {
+    DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0),
+    DEFINE_PROP_END_OF_LIST()
+};
+
+static void versal_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = versal_realize;
+    dc->props = versal_properties;
+    /* No VMSD since we haven't got any top-level SoC state to save.  */
+}
+
+static const TypeInfo versal_info = {
+    .name = TYPE_XLNX_VERSAL,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(Versal),
+    .instance_init = versal_init,
+    .class_init = versal_class_init,
+};
+
+static void versal_register_types(void)
+{
+    type_register_static(&versal_info);
+}
+
+type_init(versal_register_types);
diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/aarch64-softmmu.mak
+++ b/default-configs/aarch64-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_DDC=y
 CONFIG_DPCD=y
 CONFIG_XLNX_ZYNQMP=y
 CONFIG_XLNX_ZYNQMP_ARM=y
+CONFIG_XLNX_VERSAL=y
 CONFIG_ARM_SMMUV3=y
-- 
2.19.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add a virtual Xilinx Versal board.

This board is based on the Xilinx Versal SoC. The exact
details of what peripherals are attached to this board
will remain in control of QEMU. QEMU will generate an
FDT on the fly for Linux and other software to auto-discover
peripherals.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
[PMM: removed stray blank line at EOF]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/Makefile.objs      |   2 +-
 hw/arm/xlnx-versal-virt.c | 493 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 494 insertions(+), 1 deletion(-)
 create mode 100644 hw/arm/xlnx-versal-virt.c

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
 obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
 obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
 obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
-obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o
+obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
 obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
 obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
 obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Xilinx Versal Virtual board.
+ *
+ * Copyright (c) 2018 Xilinx Inc.
+ * Written by Edgar E. Iglesias
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "sysemu/device_tree.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "hw/sysbus.h"
+#include "hw/arm/sysbus-fdt.h"
+#include "hw/arm/fdt.h"
+#include "cpu.h"
+#include "hw/arm/xlnx-versal.h"
+
+#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
+#define XLNX_VERSAL_VIRT_MACHINE(obj) \
+    OBJECT_CHECK(VersalVirt, (obj), TYPE_XLNX_VERSAL_VIRT_MACHINE)
+
+typedef struct VersalVirt {
+    MachineState parent_obj;
+
+    Versal soc;
+    MemoryRegion mr_ddr;
+
+    void *fdt;
+    int fdt_size;
+    struct {
+        uint32_t gic;
+        uint32_t ethernet_phy[2];
+        uint32_t clk_125Mhz;
+        uint32_t clk_25Mhz;
+    } phandle;
+    struct arm_boot_info binfo;
+
+    struct {
+        bool secure;
+    } cfg;
+} VersalVirt;
+
+static void fdt_create(VersalVirt *s)
+{
+    MachineClass *mc = MACHINE_GET_CLASS(s);
+    int i;
+
+    s->fdt = create_device_tree(&s->fdt_size);
+    if (!s->fdt) {
+        error_report("create_device_tree() failed");
+        exit(1);
+    }
+
+    /* Allocate all phandles.  */
+    s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt);
+    for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) {
+        s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt);
+    }
+    s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
+    s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
+
+    /* Create /chosen node for load_dtb.  */
+    qemu_fdt_add_subnode(s->fdt, "/chosen");
+
+    /* Header */
+    qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic);
+    qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2);
+    qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2);
+    qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc);
+    qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt");
+}
+
+static void fdt_add_clk_node(VersalVirt *s, const char *name,
+                             unsigned int freq_hz, uint32_t phandle)
+{
+    qemu_fdt_add_subnode(s->fdt, name);
+    qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
+    qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
+    qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
+    qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
+    qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
+}
+
+static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
+{
+    int i;
+
+    qemu_fdt_add_subnode(s->fdt, "/cpus");
+    qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0);
+    qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1);
+
+    for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
+        char *name = g_strdup_printf("/cpus/cpu@%d", i);
+        ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
+
+        qemu_fdt_add_subnode(s->fdt, name);
+        qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
+        if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
+            qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
+        }
+        qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu");
+        qemu_fdt_setprop_string(s->fdt, name, "compatible",
+                                armcpu->dtb_compatible);
+        g_free(name);
+    }
+}
+
+static void fdt_add_gic_nodes(VersalVirt *s)
+{
+    char *nodename;
+
+    nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN);
+    qemu_fdt_add_subnode(s->fdt, nodename);
+    qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic);
+    qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts",
+                           GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ,
+                           GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+    qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0);
+    qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
+                                 2, MM_GIC_APU_DIST_MAIN,
+                                 2, MM_GIC_APU_DIST_MAIN_SIZE,
+                                 2, MM_GIC_APU_REDIST_0,
+                                 2, MM_GIC_APU_REDIST_0_SIZE);
+    qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3);
+    qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3");
+}
+
+static void fdt_add_timer_nodes(VersalVirt *s)
+{
+    const char compat[] = "arm,armv8-timer";
+    uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
+
+    qemu_fdt_add_subnode(s->fdt, "/timer");
+    qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts",
+            GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags,
+            GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags,
+            GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags,
+            GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags);
+    qemu_fdt_setprop(s->fdt, "/timer", "compatible",
+                     compat, sizeof(compat));
+}
+
+static void fdt_add_uart_nodes(VersalVirt *s)
+{
+    uint64_t addrs[] = { MM_UART1, MM_UART0 };
+    unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 };
+    const char compat[] = "arm,pl011\0arm,sbsa-uart";
+    const char clocknames[] = "uartclk\0apb_pclk";
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(addrs); i++) {
+        char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]);
+        qemu_fdt_add_subnode(s->fdt, name);
+        qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200);
+        qemu_fdt_setprop_cells(s->fdt, name, "clocks",
+                               s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
+        qemu_fdt_setprop(s->fdt, name, "clock-names",
+                         clocknames, sizeof(clocknames));
+
+        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+                               GIC_FDT_IRQ_TYPE_SPI, irqs[i],
+                               GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                     2, addrs[i], 2, 0x1000);
+        qemu_fdt_setprop(s->fdt, name, "compatible",
+                         compat, sizeof(compat));
+        qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
+
+        if (addrs[i] == MM_UART0) {
+            /* Select UART0.  */
+            qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name);
+        }
+        g_free(name);
+    }
+}
+
+static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname,
+                                     uint32_t phandle)
+{
+    char *name = g_strdup_printf("%s/fixed-link", gemname);
+
+    qemu_fdt_add_subnode(s->fdt, name);
+    qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
+    qemu_fdt_setprop_cells(s->fdt, name, "full-duplex");
+    qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000);
+    g_free(name);
+}
+
+static void fdt_add_gem_nodes(VersalVirt *s)
+{
+    uint64_t addrs[] = { MM_GEM1, MM_GEM0 };
+    unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 };
+    const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk";
+    const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem";
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(addrs); i++) {
+        char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]);
+        qemu_fdt_add_subnode(s->fdt, name);
+
+        fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]);
+        qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id");
+        qemu_fdt_setprop_cell(s->fdt, name, "phy-handle",
+                              s->phandle.ethernet_phy[i]);
+        qemu_fdt_setprop_cells(s->fdt, name, "clocks",
+                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
+                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
+        qemu_fdt_setprop(s->fdt, name, "clock-names",
+                         clocknames, sizeof(clocknames));
+        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+                               GIC_FDT_IRQ_TYPE_SPI, irqs[i],
+                               GIC_FDT_IRQ_FLAGS_LEVEL_HI,
+                               GIC_FDT_IRQ_TYPE_SPI, irqs[i],
+                               GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                     2, addrs[i], 2, 0x1000);
+        qemu_fdt_setprop(s->fdt, name, "compatible",
+                         compat_gem, sizeof(compat_gem));
+        qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1);
+        qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0);
+        g_free(name);
+    }
+}
+
+static void fdt_nop_memory_nodes(void *fdt, Error **errp)
+{
+    Error *err = NULL;
+    char **node_path;
+    int n = 0;
+
+    node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    while (node_path[n]) {
+        if (g_str_has_prefix(node_path[n], "/memory")) {
+            qemu_fdt_nop_node(fdt, node_path[n]);
+        }
+        n++;
+    }
+    g_strfreev(node_path);
+}
+
+static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size)
+{
+    /* Describes the various split DDR access regions.  */
+    static const struct {
+        uint64_t base;
+        uint64_t size;
+    } addr_ranges[] = {
+        { MM_TOP_DDR, MM_TOP_DDR_SIZE },
+        { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
+        { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
+        { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
+    };
+    uint64_t mem_reg_prop[8] = {0};
+    uint64_t size = ram_size;
+    Error *err = NULL;
+    char *name;
+    int i;
+
+    fdt_nop_memory_nodes(fdt, &err);
+    if (err) {
+        error_report_err(err);
+        return;
+    }
+
+    name = g_strdup_printf("/memory@%x", MM_TOP_DDR);
+    for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
+        uint64_t mapsize;
+
+        mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
+
+        mem_reg_prop[i * 2] = addr_ranges[i].base;
+        mem_reg_prop[i * 2 + 1] = mapsize;
+        size -= mapsize;
+    }
+    qemu_fdt_add_subnode(fdt, name);
+    qemu_fdt_setprop_string(fdt, name, "device_type", "memory");
+
+    switch (i) {
+    case 1:
+        qemu_fdt_setprop_sized_cells(fdt, name, "reg",
+                                     2, mem_reg_prop[0],
+                                     2, mem_reg_prop[1]);
+        break;
+    case 2:
+        qemu_fdt_setprop_sized_cells(fdt, name, "reg",
+                                     2, mem_reg_prop[0],
+                                     2, mem_reg_prop[1],
+                                     2, mem_reg_prop[2],
+                                     2, mem_reg_prop[3]);
+        break;
+    case 3:
+        qemu_fdt_setprop_sized_cells(fdt, name, "reg",
+                                     2, mem_reg_prop[0],
+                                     2, mem_reg_prop[1],
+                                     2, mem_reg_prop[2],
+                                     2, mem_reg_prop[3],
+                                     2, mem_reg_prop[4],
+                                     2, mem_reg_prop[5]);
+        break;
+    case 4:
+        qemu_fdt_setprop_sized_cells(fdt, name, "reg",
+                                     2, mem_reg_prop[0],
+                                     2, mem_reg_prop[1],
+                                     2, mem_reg_prop[2],
+                                     2, mem_reg_prop[3],
+                                     2, mem_reg_prop[4],
+                                     2, mem_reg_prop[5],
+                                     2, mem_reg_prop[6],
+                                     2, mem_reg_prop[7]);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    g_free(name);
+}
+
+static void versal_virt_modify_dtb(const struct arm_boot_info *binfo,
+                                    void *fdt)
+{
+    VersalVirt *s = container_of(binfo, VersalVirt, binfo);
+
+    fdt_add_memory_nodes(s, fdt, binfo->ram_size);
+}
+
+static void *versal_virt_get_dtb(const struct arm_boot_info *binfo,
+                                  int *fdt_size)
+{
+    const VersalVirt *board = container_of(binfo, VersalVirt, binfo);
+
+    *fdt_size = board->fdt_size;
+    return board->fdt;
+}
+
+#define NUM_VIRTIO_TRANSPORT 32
+static void create_virtio_regions(VersalVirt *s)
+{
+    int virtio_mmio_size = 0x200;
+    int i;
+
+    for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
+        char *name = g_strdup_printf("virtio%d", i);;
+        hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
+        int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i;
+        MemoryRegion *mr;
+        DeviceState *dev;
+        qemu_irq pic_irq;
+
+        pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
+        dev = qdev_create(NULL, "virtio-mmio");
+        object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev),
+                                  &error_fatal);
+        qdev_init_nofail(dev);
+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
+        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+        memory_region_add_subregion(&s->soc.mr_ps, base, mr);
+        sysbus_create_simple("virtio-mmio", base, pic_irq);
+    }
+
+    for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
+        hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
+        int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i;
+        char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
+
+        qemu_fdt_add_subnode(s->fdt, name);
+        qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0);
+        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+                               GIC_FDT_IRQ_TYPE_SPI, irq,
+                               GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
+        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                     2, base, 2, virtio_mmio_size);
+        qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio");
+        g_free(name);
+    }
+}
+
+static void versal_virt_init(MachineState *machine)
+{
+    VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
+    int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
+
+    /*
+     * If the user provides an Operating System to be loaded, we expect them
+     * to use the -kernel command line option.
+     *
+     * Users can load firmware or boot-loaders with the -device loader options.
+     *
+     * When loading an OS, we generate a dtb and let arm_load_kernel() select
+     * where it gets loaded. This dtb will be passed to the kernel in x0.
+     *
+     * If there's no -kernel option, we generate a DTB and place it at 0x1000
+     * for the bootloaders or firmware to pick up.
+     *
+     * If users want to provide their own DTB, they can use the -dtb option.
+     * These dtb's will have their memory nodes modified to match QEMU's
+     * selected ram_size option before they get passed to the kernel or fw.
+     *
+     * When loading an OS, we turn on QEMU's PSCI implementation with SMC
+     * as the PSCI conduit. When there's no -kernel, we assume the user
+     * provides EL3 firmware to handle PSCI.
+     */
+    if (machine->kernel_filename) {
+        psci_conduit = QEMU_PSCI_CONDUIT_SMC;
+    }
+
+    memory_region_allocate_system_memory(&s->mr_ddr, NULL, "ddr",
+                                         machine->ram_size);
+
+    sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
+                          sizeof(s->soc), TYPE_XLNX_VERSAL);
+    object_property_set_link(OBJECT(&s->soc), OBJECT(&s->mr_ddr),
+                             "ddr", &error_abort);
+    object_property_set_int(OBJECT(&s->soc), psci_conduit,
+                            "psci-conduit", &error_abort);
+    object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
+
+    fdt_create(s);
+    create_virtio_regions(s);
+    fdt_add_gem_nodes(s);
+    fdt_add_uart_nodes(s);
+    fdt_add_gic_nodes(s);
+    fdt_add_timer_nodes(s);
+    fdt_add_cpu_nodes(s, psci_conduit);
+    fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
+    fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
+
+    /* Make the APU cpu address space visible to virtio and other
+     * modules unaware of muliple address-spaces.  */
+    memory_region_add_subregion_overlap(get_system_memory(),
+                                        0, &s->soc.fpd.apu.mr, 0);
+
+    s->binfo.ram_size = machine->ram_size;
+    s->binfo.kernel_filename = machine->kernel_filename;
+    s->binfo.kernel_cmdline = machine->kernel_cmdline;
+    s->binfo.initrd_filename = machine->initrd_filename;
+    s->binfo.loader_start = 0x0;
+    s->binfo.get_dtb = versal_virt_get_dtb;
+    s->binfo.modify_dtb = versal_virt_modify_dtb;
+    if (machine->kernel_filename) {
+        arm_load_kernel(s->soc.fpd.apu.cpu[0], &s->binfo);
+    } else {
+        AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
+                                                  &s->binfo);
+        /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
+         * Offset things by 4K.  */
+        s->binfo.loader_start = 0x1000;
+        s->binfo.dtb_limit = 0x1000000;
+        if (arm_load_dtb(s->binfo.loader_start,
+                         &s->binfo, s->binfo.dtb_limit, as) < 0) {
+            exit(EXIT_FAILURE);
+        }
+    }
+}
+
+static void versal_virt_machine_instance_init(Object *obj)
+{
+}
+
+static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->desc = "Xilinx Versal Virtual development board";
+    mc->init = versal_virt_init;
+    mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
+    mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
+    mc->no_cdrom = true;
+}
+
+static const TypeInfo versal_virt_machine_init_typeinfo = {
+    .name       = TYPE_XLNX_VERSAL_VIRT_MACHINE,
+    .parent     = TYPE_MACHINE,
+    .class_init = versal_virt_machine_class_init,
+    .instance_init = versal_virt_machine_instance_init,
+    .instance_size = sizeof(VersalVirt),
+};
+
+static void versal_virt_machine_init_register_types(void)
+{
+    type_register_static(&versal_virt_machine_init_typeinfo);
+}
+
+type_init(versal_virt_machine_init_register_types)
-- 
2.19.1

From: Julia Suvorova via Qemu-devel <qemu-devel@nongnu.org>

Not implemented: CTS/NCTS, PSEL*.

Signed-off-by: Julia Suvorova <jusual@mail.ru>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/Makefile.objs        |   1 +
 include/hw/char/nrf51_uart.h |  78 +++++++++
 hw/char/nrf51_uart.c         | 330 +++++++++++++++++++++++++++++++++++
 hw/char/trace-events         |   4 +
 4 files changed, 413 insertions(+)
 create mode 100644 include/hw/char/nrf51_uart.h
 create mode 100644 hw/char/nrf51_uart.c

diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -XXX,XX +XXX,XX @@
 common-obj-$(CONFIG_IPACK) += ipoctal232.o
 common-obj-$(CONFIG_ESCC) += escc.o
+common-obj-$(CONFIG_NRF51_SOC) += nrf51_uart.o
 common-obj-$(CONFIG_PARALLEL) += parallel.o
 common-obj-$(CONFIG_PARALLEL) += parallel-isa.o
 common-obj-$(CONFIG_PL011) += pl011.o
diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/char/nrf51_uart.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * nRF51 SoC UART emulation
+ *
+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#ifndef NRF51_UART_H
+#define NRF51_UART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+#include "hw/registerfields.h"
+
+#define UART_FIFO_LENGTH 6
+#define UART_BASE 0x40002000
+#define UART_SIZE 0x1000
+
+#define TYPE_NRF51_UART "nrf51_soc.uart"
+#define NRF51_UART(obj) OBJECT_CHECK(NRF51UARTState, (obj), TYPE_NRF51_UART)
+
+REG32(UART_STARTRX, 0x000)
+REG32(UART_STOPRX, 0x004)
+REG32(UART_STARTTX, 0x008)
+REG32(UART_STOPTX, 0x00C)
+REG32(UART_SUSPEND, 0x01C)
+
+REG32(UART_CTS, 0x100)
+REG32(UART_NCTS, 0x104)
+REG32(UART_RXDRDY, 0x108)
+REG32(UART_TXDRDY, 0x11C)
+REG32(UART_ERROR, 0x124)
+REG32(UART_RXTO, 0x144)
+
+REG32(UART_INTEN, 0x300)
+    FIELD(UART_INTEN, CTS, 0, 1)
+    FIELD(UART_INTEN, NCTS, 1, 1)
+    FIELD(UART_INTEN, RXDRDY, 2, 1)
+    FIELD(UART_INTEN, TXDRDY, 7, 1)
+    FIELD(UART_INTEN, ERROR, 9, 1)
+    FIELD(UART_INTEN, RXTO, 17, 1)
+REG32(UART_INTENSET, 0x304)
+REG32(UART_INTENCLR, 0x308)
+REG32(UART_ERRORSRC, 0x480)
+REG32(UART_ENABLE, 0x500)
+REG32(UART_PSELRTS, 0x508)
+REG32(UART_PSELTXD, 0x50C)
+REG32(UART_PSELCTS, 0x510)
+REG32(UART_PSELRXD, 0x514)
+REG32(UART_RXD, 0x518)
+REG32(UART_TXD, 0x51C)
+REG32(UART_BAUDRATE, 0x524)
+REG32(UART_CONFIG, 0x56C)
+
+typedef struct NRF51UARTState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+    CharBackend chr;
+    qemu_irq irq;
+    guint watch_tag;
+
+    uint8_t rx_fifo[UART_FIFO_LENGTH];
+    unsigned int rx_fifo_pos;
+    unsigned int rx_fifo_len;
+
+    uint32_t reg[0x56C];
+
+    bool rx_started;
+    bool tx_started;
+    bool pending_tx_byte;
+    bool enabled;
+} NRF51UARTState;
+
+#endif
diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/char/nrf51_uart.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * nRF51 SoC UART emulation
+ *
+ * See nRF51 Series Reference Manual, "29 Universal Asynchronous
+ * Receiver/Transmitter" for hardware specifications:
+ * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
+ *
+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/char/nrf51_uart.h"
+#include "trace.h"
+
+static void nrf51_uart_update_irq(NRF51UARTState *s)
+{
+    bool irq = false;
+
+    irq |= (s->reg[R_UART_RXDRDY] &&
+            (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK));
+    irq |= (s->reg[R_UART_TXDRDY] &&
+            (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK));
+    irq |= (s->reg[R_UART_ERROR]  &&
+            (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK));
+    irq |= (s->reg[R_UART_RXTO]   &&
+            (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK));
+
+    qemu_set_irq(s->irq, irq);
+}
+
+static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    NRF51UARTState *s = NRF51_UART(opaque);
+    uint64_t r;
+
+    if (!s->enabled) {
+        return 0;
+    }
+
+    switch (addr) {
+    case A_UART_RXD:
+        r = s->rx_fifo[s->rx_fifo_pos];
+        if (s->rx_started && s->rx_fifo_len) {
+            s->rx_fifo_pos = (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH;
+            s->rx_fifo_len--;
+            if (s->rx_fifo_len) {
+                s->reg[R_UART_RXDRDY] = 1;
+                nrf51_uart_update_irq(s);
+            }
+            qemu_chr_fe_accept_input(&s->chr);
+        }
+        break;
+    case A_UART_INTENSET:
+    case A_UART_INTENCLR:
+    case A_UART_INTEN:
+        r = s->reg[R_UART_INTEN];
+        break;
+    default:
+        r = s->reg[addr / 4];
+        break;
+    }
+
+    trace_nrf51_uart_read(addr, r, size);
+
+    return r;
+}
+
+static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque)
+{
+    NRF51UARTState *s = NRF51_UART(opaque);
+    int r;
+    uint8_t c = s->reg[R_UART_TXD];
+
+    s->watch_tag = 0;
+
+    r = qemu_chr_fe_write(&s->chr, &c, 1);
+    if (r <= 0) {
+        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+                                             uart_transmit, s);
+        if (!s->watch_tag) {
+            /* The hardware has no transmit error reporting,
+             * so silently drop the byte
+             */
+            goto buffer_drained;
+        }
+        return FALSE;
+    }
+
+buffer_drained:
+    s->reg[R_UART_TXDRDY] = 1;
+    s->pending_tx_byte = false;
+    return FALSE;
+}
+
+static void uart_cancel_transmit(NRF51UARTState *s)
+{
+    if (s->watch_tag) {
+        g_source_remove(s->watch_tag);
+        s->watch_tag = 0;
+    }
+}
+
+static void uart_write(void *opaque, hwaddr addr,
+                       uint64_t value, unsigned int size)
+{
+    NRF51UARTState *s = NRF51_UART(opaque);
+
+    trace_nrf51_uart_write(addr, value, size);
+
+    if (!s->enabled && (addr != A_UART_ENABLE)) {
+        return;
+    }
+
+    switch (addr) {
+    case A_UART_TXD:
+        if (!s->pending_tx_byte && s->tx_started) {
+            s->reg[R_UART_TXD] = value;
+            s->pending_tx_byte = true;
+            uart_transmit(NULL, G_IO_OUT, s);
+        }
+        break;
+    case A_UART_INTEN:
+        s->reg[R_UART_INTEN] = value;
+        break;
+    case A_UART_INTENSET:
+        s->reg[R_UART_INTEN] |= value;
+        break;
+    case A_UART_INTENCLR:
+        s->reg[R_UART_INTEN] &= ~value;
+        break;
+    case A_UART_TXDRDY ... A_UART_RXTO:
+        s->reg[addr / 4] = value;
+        break;
+    case A_UART_ERRORSRC:
+        s->reg[addr / 4] &= ~value;
+        break;
+    case A_UART_RXD:
+        break;
+    case A_UART_RXDRDY:
+        if (value == 0) {
+            s->reg[R_UART_RXDRDY] = 0;
+        }
+        break;
+    case A_UART_STARTTX:
+        if (value == 1) {
+            s->tx_started = true;
+        }
+        break;
+    case A_UART_STARTRX:
+        if (value == 1) {
+            s->rx_started = true;
+        }
+        break;
+    case A_UART_ENABLE:
+        if (value) {
+            if (value == 4) {
+                s->enabled = true;
+            }
+            break;
+        }
+        s->enabled = false;
+        value = 1;
+        /* fall through */
+    case A_UART_SUSPEND:
+    case A_UART_STOPTX:
+        if (value == 1) {
+            s->tx_started = false;
+        }
+        /* fall through */
+    case A_UART_STOPRX:
+        if (addr != A_UART_STOPTX && value == 1) {
+            s->rx_started = false;
+            s->reg[R_UART_RXTO] = 1;
+        }
+        break;
+    default:
+        s->reg[addr / 4] = value;
+        break;
+    }
+    nrf51_uart_update_irq(s);
+}
+
+static const MemoryRegionOps uart_ops = {
+    .read =  uart_read,
+    .write = uart_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void nrf51_uart_reset(DeviceState *dev)
+{
+    NRF51UARTState *s = NRF51_UART(dev);
+
+    s->pending_tx_byte = 0;
+
+    uart_cancel_transmit(s);
+
+    memset(s->reg, 0, sizeof(s->reg));
+
+    s->reg[R_UART_PSELRTS] = 0xFFFFFFFF;
+    s->reg[R_UART_PSELTXD] = 0xFFFFFFFF;
+    s->reg[R_UART_PSELCTS] = 0xFFFFFFFF;
+    s->reg[R_UART_PSELRXD] = 0xFFFFFFFF;
+    s->reg[R_UART_BAUDRATE] = 0x4000000;
+
+    s->rx_fifo_len = 0;
+    s->rx_fifo_pos = 0;
+    s->rx_started = false;
+    s->tx_started = false;
+    s->enabled = false;
+}
+
+static void uart_receive(void *opaque, const uint8_t *buf, int size)
+{
+
+    NRF51UARTState *s = NRF51_UART(opaque);
+    int i;
+
+    if (size == 0 || s->rx_fifo_len >= UART_FIFO_LENGTH) {
+        return;
+    }
+
+    for (i = 0; i < size; i++) {
+        uint32_t pos = (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LENGTH;
+        s->rx_fifo[pos] = buf[i];
+        s->rx_fifo_len++;
+    }
+
+    s->reg[R_UART_RXDRDY] = 1;
+    nrf51_uart_update_irq(s);
+}
+
+static int uart_can_receive(void *opaque)
+{
+    NRF51UARTState *s = NRF51_UART(opaque);
+
+    return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0;
+}
+
+static void uart_event(void *opaque, int event)
+{
+    NRF51UARTState *s = NRF51_UART(opaque);
+
+    if (event == CHR_EVENT_BREAK) {
+        s->reg[R_UART_ERRORSRC] |= 3;
+        s->reg[R_UART_ERROR] = 1;
+        nrf51_uart_update_irq(s);
+    }
+}
+
+static void nrf51_uart_realize(DeviceState *dev, Error **errp)
+{
+    NRF51UARTState *s = NRF51_UART(dev);
+
+    qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
+                             uart_event, NULL, s, NULL, true);
+}
+
+static void nrf51_uart_init(Object *obj)
+{
+    NRF51UARTState *s = NRF51_UART(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+    memory_region_init_io(&s->iomem, obj, &uart_ops, s,
+                          "nrf51_soc.uart", UART_SIZE);
+    sysbus_init_mmio(sbd, &s->iomem);
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static int nrf51_uart_post_load(void *opaque, int version_id)
+{
+    NRF51UARTState *s = NRF51_UART(opaque);
+
+    if (s->pending_tx_byte) {
+        s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
+                                             uart_transmit, s);
+    }
+
+    return 0;
+}
+
+static const VMStateDescription nrf51_uart_vmstate = {
+    .name = "nrf51_soc.uart",
+    .post_load = nrf51_uart_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C),
+        VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH),
+        VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState),
+        VMSTATE_UINT32(rx_fifo_len, NRF51UARTState),
+        VMSTATE_BOOL(rx_started, NRF51UARTState),
+        VMSTATE_BOOL(tx_started, NRF51UARTState),
+        VMSTATE_BOOL(pending_tx_byte, NRF51UARTState),
+        VMSTATE_BOOL(enabled, NRF51UARTState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static Property nrf51_uart_properties[] = {
+    DEFINE_PROP_CHR("chardev", NRF51UARTState, chr),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void nrf51_uart_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = nrf51_uart_reset;
+    dc->realize = nrf51_uart_realize;
+    dc->props = nrf51_uart_properties;
+    dc->vmsd = &nrf51_uart_vmstate;
+}
+
+static const TypeInfo nrf51_uart_info = {
+    .name = TYPE_NRF51_UART,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(NRF51UARTState),
+    .instance_init = nrf51_uart_init,
+    .class_init = nrf51_uart_class_init
+};
+
+static void nrf51_uart_register_types(void)
+{
+    type_register_static(&nrf51_uart_info);
+}
+
+type_init(nrf51_uart_register_types)
diff --git a/hw/char/trace-events b/hw/char/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_uart_receive(uint8_t c) "CMSDK APB UART: got character 0x%x from backe
 cmsdk_apb_uart_tx_pending(void) "CMSDK APB UART: character send to backend pending"
 cmsdk_apb_uart_tx(uint8_t c) "CMSDK APB UART: character 0x%x sent to backend"
 cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
+
+# hw/char/nrf51_uart.c
+nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
+nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
-- 
2.19.1

From: Julia Suvorova via Qemu-devel <qemu-devel@nongnu.org>

Wire up nRF51 UART in the corresponding SoC.

Signed-off-by: Julia Suvorova <jusual@mail.ru>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/nrf51_soc.h |  3 +++
 hw/arm/microbit.c          |  2 ++
 hw/arm/nrf51_soc.c         | 20 ++++++++++++++++++++
 3 files changed, 25 insertions(+)

diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/nrf51_soc.h
+++ b/include/hw/arm/nrf51_soc.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/sysbus.h"
 #include "hw/arm/armv7m.h"
+#include "hw/char/nrf51_uart.h"
 
 #define TYPE_NRF51_SOC "nrf51-soc"
 #define NRF51_SOC(obj) \
@@ -XXX,XX +XXX,XX @@ typedef struct NRF51State {
     /*< public >*/
     ARMv7MState cpu;
 
+    NRF51UARTState uart;
+
     MemoryRegion iomem;
     MemoryRegion sram;
     MemoryRegion flash;
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/boards.h"
 #include "hw/arm/arm.h"
+#include "sysemu/sysemu.h"
 #include "exec/address-spaces.h"
 
 #include "hw/arm/nrf51_soc.h"
@@ -XXX,XX +XXX,XX @@ static void microbit_init(MachineState *machine)
 
     sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51),
                           TYPE_NRF51_SOC);
+    qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0));
     object_property_set_link(soc, OBJECT(system_memory), "memory",
                              &error_fatal);
     object_property_set_bool(soc, true, "realized", &error_fatal);
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -XXX,XX +XXX,XX @@
 #define NRF51822_FLASH_SIZE     (256 * 1024)
 #define NRF51822_SRAM_SIZE      (16 * 1024)
 
+#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
+
 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
 {
     NRF51State *s = NRF51_SOC(dev_soc);
+    MemoryRegion *mr;
     Error *err = NULL;
 
     if (!s->board_memory) {
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
     }
     memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
 
+    /* UART */
+    object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
+    memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
+                       qdev_get_gpio_in(DEVICE(&s->cpu),
+                       BASE_TO_IRQ(UART_BASE)));
+
     create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
     create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
     create_unimplemented_device("nrf51_soc.private",
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_init(Object *obj)
     qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
                          ARM_CPU_TYPE_NAME("cortex-m0"));
     qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
+
+    sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
+                           TYPE_NRF51_UART);
+    object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",
+                              &error_abort);
 }
 
 static Property nrf51_soc_properties[] = {
-- 
2.19.1

From: Julia Suvorova via Qemu-devel <qemu-devel@nongnu.org>

New mini-kernel test for nRF51 SoC UART.

Signed-off-by: Julia Suvorova <jusual@mail.ru>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/boot-serial-test.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/boot-serial-test.c
+++ b/tests/boot-serial-test.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_aarch64[] = {
     0xfd, 0xff, 0xff, 0x17,                 /* b       -12 (loop) */
 };
 
+static const uint8_t kernel_nrf51[] = {
+    0x00, 0x00, 0x00, 0x00,                 /* Stack top address */
+    0x09, 0x00, 0x00, 0x00,                 /* Reset handler address */
+    0x04, 0x4a,                             /* ldr  r2, [pc, #16] Get ENABLE */
+    0x04, 0x21,                             /* movs r1, #4 */
+    0x11, 0x60,                             /* str  r1, [r2] */
+    0x04, 0x4a,                             /* ldr  r2, [pc, #16] Get STARTTX */
+    0x01, 0x21,                             /* movs r1, #1 */
+    0x11, 0x60,                             /* str  r1, [r2] */
+    0x03, 0x4a,                             /* ldr  r2, [pc, #12] Get TXD */
+    0x54, 0x21,                             /* movs r1, 'T' */
+    0x11, 0x60,                             /* str  r1, [r2] */
+    0xfe, 0xe7,                             /* b    . */
+    0x00, 0x25, 0x00, 0x40,                 /* 0x40002500 = UART ENABLE */
+    0x08, 0x20, 0x00, 0x40,                 /* 0x40002008 = UART STARTTX */
+    0x1c, 0x25, 0x00, 0x40                  /* 0x4000251c = UART TXD */
+};
+
 typedef struct testdef {
     const char *arch;       /* Target architecture */
     const char *machine;    /* Name of the machine */
@@ -XXX,XX +XXX,XX @@ static testdef_t tests[] = {
     { "hppa", "hppa", "", "SeaBIOS wants SYSTEM HALT" },
     { "aarch64", "virt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64),
       kernel_aarch64 },
+    { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
 
     { NULL }
 };
-- 
2.19.1

The following changes since commit 3db29dcac23da85486704ef9e7a8e7217f7829cd:

Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-01-12 13:51:36 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230113

for you to fetch changes up to 08899b5c68a55a3780d707e2464073c8f2670d31:

target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled (2023-01-13 13:19:36 +0000)

----------------------------------------------------------------
target-arm queue:
 hw/arm/stm32f405: correctly describe the memory layout
 hw/arm: Add Olimex H405 board
 cubieboard: Support booting from an SD card image with u-boot on it
 target/arm: Fix sve_probe_page
 target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
 various code cleanups

----------------------------------------------------------------
Evgeny Iakovlev (1):
      target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled

Felipe Balbi (2):
      hw/arm/stm32f405: correctly describe the memory layout
      hw/arm: Add Olimex H405

Philippe Mathieu-Daudé (27):
      hw/arm/pxa2xx: Simplify pxa255_init()
      hw/arm/pxa2xx: Simplify pxa270_init()
      hw/arm/collie: Use the IEC binary prefix definitions
      hw/arm/collie: Simplify flash creation using for() loop
      hw/arm/gumstix: Improve documentation
      hw/arm/gumstix: Use the IEC binary prefix definitions
      hw/arm/mainstone: Use the IEC binary prefix definitions
      hw/arm/musicpal: Use the IEC binary prefix definitions
      hw/arm/omap_sx1: Remove unused 'total_ram' definitions
      hw/arm/omap_sx1: Use the IEC binary prefix definitions
      hw/arm/z2: Use the IEC binary prefix definitions
      hw/arm/vexpress: Remove dead code in vexpress_common_init()
      hw/arm: Remove unreachable code calling pflash_cfi01_register()
      hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState
      hw/gpio/omap_gpio: Add local variable to avoid embedded cast
      hw/arm/omap: Drop useless casts from void * to pointer
      hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name
      hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name
      hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name
      hw/arm/stellaris: Drop useless casts from void * to pointer
      hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name
      hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE()
      hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
      hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC
      hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
      hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic'
      hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock'

Richard Henderson (1):
      target/arm: Fix sve_probe_page

Strahinja Jankovic (7):
      hw/misc: Allwinner-A10 Clock Controller Module Emulation
      hw/misc: Allwinner A10 DRAM Controller Emulation
      {hw/i2c,docs/system/arm}: Allwinner TWI/I2C Emulation
      hw/misc: AXP209 PMU Emulation
      hw/arm: Add AXP209 to Cubieboard
      hw/arm: Allwinner A10 enable SPL load from MMC
      tests/avocado: Add SD boot test to Cubieboard

From: Felipe Balbi <balbi@kernel.org>

STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled
Memory) at a different base address. Correctly describe the memory
layout to give existing FW images a chance to run unmodified.

Reviewed-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Message-id: 20221230145733.200496-2-balbi@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/stm32f405_soc.h | 5 ++++-
 hw/arm/stm32f405_soc.c         | 8 ++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/stm32f405_soc.h
+++ b/include/hw/arm/stm32f405_soc.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
 #define FLASH_BASE_ADDRESS 0x08000000
 #define FLASH_SIZE (1024 * 1024)
 #define SRAM_BASE_ADDRESS 0x20000000
-#define SRAM_SIZE (192 * 1024)
+#define SRAM_SIZE (128 * 1024)
+#define CCM_BASE_ADDRESS 0x10000000
+#define CCM_SIZE (64 * 1024)
 
 struct STM32F405State {
     /*< private >*/
@@ -XXX,XX +XXX,XX @@ struct STM32F405State {
     STM32F2XXADCState adc[STM_NUM_ADCS];
     STM32F2XXSPIState spi[STM_NUM_SPIS];
 
+    MemoryRegion ccm;
     MemoryRegion sram;
     MemoryRegion flash;
     MemoryRegion flash_alias;
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -XXX,XX +XXX,XX @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
     }
     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
 
+    memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE,
+                           &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm);
+
     armv7m = DEVICE(&s->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 96);
     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
-- 
2.34.1

From: Felipe Balbi <balbi@kernel.org>

Olimex makes a series of low-cost STM32 boards. This commit introduces
the minimum setup to support SMT32-H405. See [1] for details

[1] https://www.olimex.com/Products/ARM/ST/STM32-H405/

Signed-off-by: Felipe Balbi <balbi@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20221230145733.200496-3-balbi@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/stm32.rst               |  1 +
 configs/devices/arm-softmmu/default.mak |  1 +
 hw/arm/olimex-stm32-h405.c              | 69 +++++++++++++++++++++++++
 MAINTAINERS                             |  6 +++
 hw/arm/Kconfig                          |  4 ++
 hw/arm/meson.build                      |  1 +
 6 files changed, 82 insertions(+)
 create mode 100644 hw/arm/olimex-stm32-h405.c

diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/stm32.rst
+++ b/docs/system/arm/stm32.rst
@@ -XXX,XX +XXX,XX @@ The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
 compatible with STM32F2 series. The following machines are based on this chip :
 
 - ``netduinoplus2``     Netduino Plus 2 board with STM32F405RGT6 microcontroller
+- ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microcontroller
 
 There are many other STM32 series that are currently not supported by QEMU.
 
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/devices/arm-softmmu/default.mak
+++ b/configs/devices/arm-softmmu/default.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_COLLIE=y
 CONFIG_ASPEED_SOC=y
 CONFIG_NETDUINO2=y
 CONFIG_NETDUINOPLUS2=y
+CONFIG_OLIMEX_STM32_H405=y
 CONFIG_MPS2=y
 CONFIG_RASPI=y
 CONFIG_DIGIC=y
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/olimex-stm32-h405.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ST STM32VLDISCOVERY machine
+ * Olimex STM32-H405 machine
+ *
+ * Copyright (c) 2022 Felipe Balbi <balbi@kernel.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
+#include "qemu/error-report.h"
+#include "hw/arm/stm32f405_soc.h"
+#include "hw/arm/boot.h"
+
+/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
+
+/* Main SYSCLK frequency in Hz (168MHz) */
+#define SYSCLK_FRQ 168000000ULL
+
+static void olimex_stm32_h405_init(MachineState *machine)
+{
+    DeviceState *dev;
+    Clock *sysclk;
+
+    /* This clock doesn't need migration because it is fixed-frequency */
+    sysclk = clock_new(OBJECT(machine), "SYSCLK");
+    clock_set_hz(sysclk, SYSCLK_FRQ);
+
+    dev = qdev_new(TYPE_STM32F405_SOC);
+    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
+    qdev_connect_clock_in(dev, "sysclk", sysclk);
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+    armv7m_load_kernel(ARM_CPU(first_cpu),
+                       machine->kernel_filename,
+                       0, FLASH_SIZE);
+}
+
+static void olimex_stm32_h405_machine_init(MachineClass *mc)
+{
+    mc->desc = "Olimex STM32-H405 (Cortex-M4)";
+    mc->init = olimex_stm32_h405_init;
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
+
+    /* SRAM pre-allocated as part of the SoC instantiation */
+    mc->default_ram_size = 0;
+}
+
+DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/netduinoplus2.c
 
+Olimex STM32 H405
+M: Felipe Balbi <balbi@kernel.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/olimex-stm32-h405.c
+
 SmartFusion2
 M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
 M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config NETDUINOPLUS2
     bool
     select STM32F405_SOC
 
+config OLIMEX_STM32_H405
+    bool
+    select STM32F405_SOC
+
 config NSERIES
     bool
     select OMAP
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
 arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
 arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
 arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
+arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
 arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
 arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
 arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
-- 
2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

During SPL boot several Clock Controller Module (CCM) registers are
read, most important are PLL and Tuning, as well as divisor registers.

This patch adds these registers and initializes reset values from user's
guide.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>

Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20221226220303.14420-2-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/allwinner-a10.h      |   2 +
 include/hw/misc/allwinner-a10-ccm.h |  67 +++++++++
 hw/arm/allwinner-a10.c              |   7 +
 hw/misc/allwinner-a10-ccm.c         | 224 ++++++++++++++++++++++++++++
 hw/arm/Kconfig                      |   1 +
 hw/misc/Kconfig                     |   3 +
 hw/misc/meson.build                 |   1 +
 7 files changed, 305 insertions(+)
 create mode 100644 include/hw/misc/allwinner-a10-ccm.h
 create mode 100644 hw/misc/allwinner-a10-ccm.c

diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/usb/hcd-ohci.h"
 #include "hw/usb/hcd-ehci.h"
 #include "hw/rtc/allwinner-rtc.h"
+#include "hw/misc/allwinner-a10-ccm.h"
 
 #include "target/arm/cpu.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
     /*< public >*/
 
     ARMCPU cpu;
+    AwA10ClockCtlState ccm;
     AwA10PITState timer;
     AwA10PICState intc;
     AwEmacState emac;
diff --git a/include/hw/misc/allwinner-a10-ccm.h b/include/hw/misc/allwinner-a10-ccm.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/allwinner-a10-ccm.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Allwinner A10 Clock Control Module emulation
+ *
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ *  This file is derived from Allwinner H3 CCU,
+ *  by Niek Linnenbank.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_A10_CCM_H
+#define HW_MISC_ALLWINNER_A10_CCM_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * @name Constants
+ * @{
+ */
+
+/** Size of register I/O address space used by CCM device */
+#define AW_A10_CCM_IOSIZE        (0x400)
+
+/** Total number of known registers */
+#define AW_A10_CCM_REGS_NUM      (AW_A10_CCM_IOSIZE / sizeof(uint32_t))
+
+/** @} */
+
+/**
+ * @name Object model
+ * @{
+ */
+
+#define TYPE_AW_A10_CCM    "allwinner-a10-ccm"
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10ClockCtlState, AW_A10_CCM)
+
+/** @} */
+
+/**
+ * Allwinner A10 CCM object instance state.
+ */
+struct AwA10ClockCtlState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
+
+    /** Maps I/O registers in physical memory */
+    MemoryRegion iomem;
+
+    /** Array of hardware registers */
+    uint32_t regs[AW_A10_CCM_REGS_NUM];
+};
+
+#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/usb/hcd-ohci.h"
 
 #define AW_A10_MMC0_BASE        0x01c0f000
+#define AW_A10_CCM_BASE         0x01c20000
 #define AW_A10_PIC_REG_BASE     0x01c20400
 #define AW_A10_PIT_REG_BASE     0x01c20c00
 #define AW_A10_UART0_REG_BASE   0x01c28000
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
 
     object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
 
+    object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
+
     object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
 
     object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
     create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
 
+    /* Clock Control Module */
+    sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
+
     /* FIXME use qdev NIC properties instead of nd_table[] */
     if (nd_table[0].used) {
         qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
diff --git a/hw/misc/allwinner-a10-ccm.c b/hw/misc/allwinner-a10-ccm.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/allwinner-a10-ccm.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Allwinner A10 Clock Control Module emulation
+ *
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ *  This file is derived from Allwinner H3 CCU,
+ *  by Niek Linnenbank.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/allwinner-a10-ccm.h"
+
+/* CCM register offsets */
+enum {
+    REG_PLL1_CFG             = 0x0000, /* PLL1 Control */
+    REG_PLL1_TUN             = 0x0004, /* PLL1 Tuning */
+    REG_PLL2_CFG             = 0x0008, /* PLL2 Control */
+    REG_PLL2_TUN             = 0x000C, /* PLL2 Tuning */
+    REG_PLL3_CFG             = 0x0010, /* PLL3 Control */
+    REG_PLL4_CFG             = 0x0018, /* PLL4 Control */
+    REG_PLL5_CFG             = 0x0020, /* PLL5 Control */
+    REG_PLL5_TUN             = 0x0024, /* PLL5 Tuning */
+    REG_PLL6_CFG             = 0x0028, /* PLL6 Control */
+    REG_PLL6_TUN             = 0x002C, /* PLL6 Tuning */
+    REG_PLL7_CFG             = 0x0030, /* PLL7 Control */
+    REG_PLL1_TUN2            = 0x0038, /* PLL1 Tuning2 */
+    REG_PLL5_TUN2            = 0x003C, /* PLL5 Tuning2 */
+    REG_PLL8_CFG             = 0x0040, /* PLL8 Control */
+    REG_OSC24M_CFG           = 0x0050, /* OSC24M Control */
+    REG_CPU_AHB_APB0_CFG     = 0x0054, /* CPU, AHB and APB0 Divide Ratio */
+};
+
+#define REG_INDEX(offset)    (offset / sizeof(uint32_t))
+
+/* CCM register reset values */
+enum {
+    REG_PLL1_CFG_RST         = 0x21005000,
+    REG_PLL1_TUN_RST         = 0x0A101000,
+    REG_PLL2_CFG_RST         = 0x08100010,
+    REG_PLL2_TUN_RST         = 0x00000000,
+    REG_PLL3_CFG_RST         = 0x0010D063,
+    REG_PLL4_CFG_RST         = 0x21009911,
+    REG_PLL5_CFG_RST         = 0x11049280,
+    REG_PLL5_TUN_RST         = 0x14888000,
+    REG_PLL6_CFG_RST         = 0x21009911,
+    REG_PLL6_TUN_RST         = 0x00000000,
+    REG_PLL7_CFG_RST         = 0x0010D063,
+    REG_PLL1_TUN2_RST        = 0x00000000,
+    REG_PLL5_TUN2_RST        = 0x00000000,
+    REG_PLL8_CFG_RST         = 0x21009911,
+    REG_OSC24M_CFG_RST       = 0x00138013,
+    REG_CPU_AHB_APB0_CFG_RST = 0x00010010,
+};
+
+static uint64_t allwinner_a10_ccm_read(void *opaque, hwaddr offset,
+                                       unsigned size)
+{
+    const AwA10ClockCtlState *s = AW_A10_CCM(opaque);
+    const uint32_t idx = REG_INDEX(offset);
+
+    switch (offset) {
+    case REG_PLL1_CFG:
+    case REG_PLL1_TUN:
+    case REG_PLL2_CFG:
+    case REG_PLL2_TUN:
+    case REG_PLL3_CFG:
+    case REG_PLL4_CFG:
+    case REG_PLL5_CFG:
+    case REG_PLL5_TUN:
+    case REG_PLL6_CFG:
+    case REG_PLL6_TUN:
+    case REG_PLL7_CFG:
+    case REG_PLL1_TUN2:
+    case REG_PLL5_TUN2:
+    case REG_PLL8_CFG:
+    case REG_OSC24M_CFG:
+    case REG_CPU_AHB_APB0_CFG:
+        break;
+    case 0x158 ... AW_A10_CCM_IOSIZE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+                      __func__, (uint32_t)offset);
+        return 0;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
+                      __func__, (uint32_t)offset);
+        return 0;
+    }
+
+    return s->regs[idx];
+}
+
+static void allwinner_a10_ccm_write(void *opaque, hwaddr offset,
+                                   uint64_t val, unsigned size)
+{
+    AwA10ClockCtlState *s = AW_A10_CCM(opaque);
+    const uint32_t idx = REG_INDEX(offset);
+
+    switch (offset) {
+    case REG_PLL1_CFG:
+    case REG_PLL1_TUN:
+    case REG_PLL2_CFG:
+    case REG_PLL2_TUN:
+    case REG_PLL3_CFG:
+    case REG_PLL4_CFG:
+    case REG_PLL5_CFG:
+    case REG_PLL5_TUN:
+    case REG_PLL6_CFG:
+    case REG_PLL6_TUN:
+    case REG_PLL7_CFG:
+    case REG_PLL1_TUN2:
+    case REG_PLL5_TUN2:
+    case REG_PLL8_CFG:
+    case REG_OSC24M_CFG:
+    case REG_CPU_AHB_APB0_CFG:
+        break;
+    case 0x158 ... AW_A10_CCM_IOSIZE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+                      __func__, (uint32_t)offset);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
+                      __func__, (uint32_t)offset);
+        break;
+    }
+
+    s->regs[idx] = (uint32_t) val;
+}
+
+static const MemoryRegionOps allwinner_a10_ccm_ops = {
+    .read = allwinner_a10_ccm_read,
+    .write = allwinner_a10_ccm_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+    .impl.min_access_size = 4,
+};
+
+static void allwinner_a10_ccm_reset_enter(Object *obj, ResetType type)
+{
+    AwA10ClockCtlState *s = AW_A10_CCM(obj);
+
+    /* Set default values for registers */
+    s->regs[REG_INDEX(REG_PLL1_CFG)] = REG_PLL1_CFG_RST;
+    s->regs[REG_INDEX(REG_PLL1_TUN)] = REG_PLL1_TUN_RST;
+    s->regs[REG_INDEX(REG_PLL2_CFG)] = REG_PLL2_CFG_RST;
+    s->regs[REG_INDEX(REG_PLL2_TUN)] = REG_PLL2_TUN_RST;
+    s->regs[REG_INDEX(REG_PLL3_CFG)] = REG_PLL3_CFG_RST;
+    s->regs[REG_INDEX(REG_PLL4_CFG)] = REG_PLL4_CFG_RST;
+    s->regs[REG_INDEX(REG_PLL5_CFG)] = REG_PLL5_CFG_RST;
+    s->regs[REG_INDEX(REG_PLL5_TUN)] = REG_PLL5_TUN_RST;
+    s->regs[REG_INDEX(REG_PLL6_CFG)] = REG_PLL6_CFG_RST;
+    s->regs[REG_INDEX(REG_PLL6_TUN)] = REG_PLL6_TUN_RST;
+    s->regs[REG_INDEX(REG_PLL7_CFG)] = REG_PLL7_CFG_RST;
+    s->regs[REG_INDEX(REG_PLL1_TUN2)] = REG_PLL1_TUN2_RST;
+    s->regs[REG_INDEX(REG_PLL5_TUN2)] = REG_PLL5_TUN2_RST;
+    s->regs[REG_INDEX(REG_PLL8_CFG)] = REG_PLL8_CFG_RST;
+    s->regs[REG_INDEX(REG_OSC24M_CFG)] = REG_OSC24M_CFG_RST;
+    s->regs[REG_INDEX(REG_CPU_AHB_APB0_CFG)] = REG_CPU_AHB_APB0_CFG_RST;
+}
+
+static void allwinner_a10_ccm_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    AwA10ClockCtlState *s = AW_A10_CCM(obj);
+
+    /* Memory mapping */
+    memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_ccm_ops, s,
+                          TYPE_AW_A10_CCM, AW_A10_CCM_IOSIZE);
+    sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_a10_ccm_vmstate = {
+    .name = "allwinner-a10-ccm",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, AwA10ClockCtlState, AW_A10_CCM_REGS_NUM),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void allwinner_a10_ccm_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    rc->phases.enter = allwinner_a10_ccm_reset_enter;
+    dc->vmsd = &allwinner_a10_ccm_vmstate;
+}
+
+static const TypeInfo allwinner_a10_ccm_info = {
+    .name          = TYPE_AW_A10_CCM,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_init = allwinner_a10_ccm_init,
+    .instance_size = sizeof(AwA10ClockCtlState),
+    .class_init    = allwinner_a10_ccm_class_init,
+};
+
+static void allwinner_a10_ccm_register(void)
+{
+    type_register_static(&allwinner_a10_ccm_info);
+}
+
+type_init(allwinner_a10_ccm_register)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
     select AHCI
     select ALLWINNER_A10_PIT
     select ALLWINNER_A10_PIC
+    select ALLWINNER_A10_CCM
     select ALLWINNER_EMAC
     select SERIAL
     select UNIMP
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config VIRT_CTRL
 config LASI
     bool
 
+config ALLWINNER_A10_CCM
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ subdir('macio')
 
 softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c'))
 
+softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c'))
 softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c'))
 specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'))
 softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
-- 
2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

During SPL boot several DRAM Controller registers are used. Most
important registers are those related to DRAM initialization and
calibration, where SPL initiates process and waits until certain bit is
set/cleared.

This patch adds these registers, initializes reset values from user's
guide and updates state of registers as SPL expects it.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>

Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20221226220303.14420-3-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/allwinner-a10.h        |   2 +
 include/hw/misc/allwinner-a10-dramc.h |  68 ++++++++++
 hw/arm/allwinner-a10.c                |   7 +
 hw/misc/allwinner-a10-dramc.c         | 179 ++++++++++++++++++++++++++
 hw/arm/Kconfig                        |   1 +
 hw/misc/Kconfig                       |   3 +
 hw/misc/meson.build                   |   1 +
 7 files changed, 261 insertions(+)
 create mode 100644 include/hw/misc/allwinner-a10-dramc.h
 create mode 100644 hw/misc/allwinner-a10-dramc.c

diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/usb/hcd-ehci.h"
 #include "hw/rtc/allwinner-rtc.h"
 #include "hw/misc/allwinner-a10-ccm.h"
+#include "hw/misc/allwinner-a10-dramc.h"
 
 #include "target/arm/cpu.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
 
     ARMCPU cpu;
     AwA10ClockCtlState ccm;
+    AwA10DramControllerState dramc;
     AwA10PITState timer;
     AwA10PICState intc;
     AwEmacState emac;
diff --git a/include/hw/misc/allwinner-a10-dramc.h b/include/hw/misc/allwinner-a10-dramc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/allwinner-a10-dramc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Allwinner A10 DRAM Controller emulation
+ *
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ *  This file is derived from Allwinner H3 DRAMC,
+ *  by Niek Linnenbank.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_A10_DRAMC_H
+#define HW_MISC_ALLWINNER_A10_DRAMC_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+
+/**
+ * @name Constants
+ * @{
+ */
+
+/** Size of register I/O address space used by DRAMC device */
+#define AW_A10_DRAMC_IOSIZE        (0x1000)
+
+/** Total number of known registers */
+#define AW_A10_DRAMC_REGS_NUM      (AW_A10_DRAMC_IOSIZE / sizeof(uint32_t))
+
+/** @} */
+
+/**
+ * @name Object model
+ * @{
+ */
+
+#define TYPE_AW_A10_DRAMC    "allwinner-a10-dramc"
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10DramControllerState, AW_A10_DRAMC)
+
+/** @} */
+
+/**
+ * Allwinner A10 DRAMC object instance state.
+ */
+struct AwA10DramControllerState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
+
+    /** Maps I/O registers in physical memory */
+    MemoryRegion iomem;
+
+    /** Array of hardware registers */
+    uint32_t regs[AW_A10_DRAMC_REGS_NUM];
+};
+
+#endif /* HW_MISC_ALLWINNER_A10_DRAMC_H */
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "hw/usb/hcd-ohci.h"
 
+#define AW_A10_DRAMC_BASE       0x01c01000
 #define AW_A10_MMC0_BASE        0x01c0f000
 #define AW_A10_CCM_BASE         0x01c20000
 #define AW_A10_PIC_REG_BASE     0x01c20400
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
 
     object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
 
+    object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
+
     object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
 
     object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
 
+    /* DRAM Control Module */
+    sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
+
     /* FIXME use qdev NIC properties instead of nd_table[] */
     if (nd_table[0].used) {
         qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
diff --git a/hw/misc/allwinner-a10-dramc.c b/hw/misc/allwinner-a10-dramc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/allwinner-a10-dramc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Allwinner A10 DRAM Controller emulation
+ *
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ *  This file is derived from Allwinner H3 DRAMC,
+ *  by Niek Linnenbank.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/allwinner-a10-dramc.h"
+
+/* DRAMC register offsets */
+enum {
+    REG_SDR_CCR = 0x0000,
+    REG_SDR_ZQCR0 = 0x00a8,
+    REG_SDR_ZQSR = 0x00b0
+};
+
+#define REG_INDEX(offset)    (offset / sizeof(uint32_t))
+
+/* DRAMC register flags */
+enum {
+    REG_SDR_CCR_DATA_TRAINING = (1 << 30),
+    REG_SDR_CCR_DRAM_INIT     = (1 << 31),
+};
+enum {
+    REG_SDR_ZQSR_ZCAL         = (1 << 31),
+};
+
+/* DRAMC register reset values */
+enum {
+    REG_SDR_CCR_RESET   = 0x80020000,
+    REG_SDR_ZQCR0_RESET = 0x07b00000,
+    REG_SDR_ZQSR_RESET  = 0x80000000
+};
+
+static uint64_t allwinner_a10_dramc_read(void *opaque, hwaddr offset,
+                                       unsigned size)
+{
+    const AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
+    const uint32_t idx = REG_INDEX(offset);
+
+    switch (offset) {
+    case REG_SDR_CCR:
+    case REG_SDR_ZQCR0:
+    case REG_SDR_ZQSR:
+        break;
+    case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+                      __func__, (uint32_t)offset);
+        return 0;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
+                      __func__, (uint32_t)offset);
+        return 0;
+    }
+
+    return s->regs[idx];
+}
+
+static void allwinner_a10_dramc_write(void *opaque, hwaddr offset,
+                                   uint64_t val, unsigned size)
+{
+    AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
+    const uint32_t idx = REG_INDEX(offset);
+
+    switch (offset) {
+    case REG_SDR_CCR:
+        if (val & REG_SDR_CCR_DRAM_INIT) {
+            /* Clear DRAM_INIT to indicate process is done. */
+            val &= ~REG_SDR_CCR_DRAM_INIT;
+        }
+        if (val & REG_SDR_CCR_DATA_TRAINING) {
+            /* Clear DATA_TRAINING to indicate process is done. */
+            val &= ~REG_SDR_CCR_DATA_TRAINING;
+        }
+        break;
+    case REG_SDR_ZQCR0:
+        /* Set ZCAL in ZQSR to indicate calibration is done. */
+        s->regs[REG_INDEX(REG_SDR_ZQSR)] |= REG_SDR_ZQSR_ZCAL;
+        break;
+    case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+                      __func__, (uint32_t)offset);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
+                      __func__, (uint32_t)offset);
+        break;
+    }
+
+    s->regs[idx] = (uint32_t) val;
+}
+
+static const MemoryRegionOps allwinner_a10_dramc_ops = {
+    .read = allwinner_a10_dramc_read,
+    .write = allwinner_a10_dramc_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+    .impl.min_access_size = 4,
+};
+
+static void allwinner_a10_dramc_reset_enter(Object *obj, ResetType type)
+{
+    AwA10DramControllerState *s = AW_A10_DRAMC(obj);
+
+    /* Set default values for registers */
+    s->regs[REG_INDEX(REG_SDR_CCR)] = REG_SDR_CCR_RESET;
+    s->regs[REG_INDEX(REG_SDR_ZQCR0)] = REG_SDR_ZQCR0_RESET;
+    s->regs[REG_INDEX(REG_SDR_ZQSR)] = REG_SDR_ZQSR_RESET;
+}
+
+static void allwinner_a10_dramc_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    AwA10DramControllerState *s = AW_A10_DRAMC(obj);
+
+    /* Memory mapping */
+    memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_dramc_ops, s,
+                          TYPE_AW_A10_DRAMC, AW_A10_DRAMC_IOSIZE);
+    sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_a10_dramc_vmstate = {
+    .name = "allwinner-a10-dramc",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, AwA10DramControllerState,
+                             AW_A10_DRAMC_REGS_NUM),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void allwinner_a10_dramc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    rc->phases.enter = allwinner_a10_dramc_reset_enter;
+    dc->vmsd = &allwinner_a10_dramc_vmstate;
+}
+
+static const TypeInfo allwinner_a10_dramc_info = {
+    .name          = TYPE_AW_A10_DRAMC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_init = allwinner_a10_dramc_init,
+    .instance_size = sizeof(AwA10DramControllerState),
+    .class_init    = allwinner_a10_dramc_class_init,
+};
+
+static void allwinner_a10_dramc_register(void)
+{
+    type_register_static(&allwinner_a10_dramc_info);
+}
+
+type_init(allwinner_a10_dramc_register)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
     select ALLWINNER_A10_PIT
     select ALLWINNER_A10_PIC
     select ALLWINNER_A10_CCM
+    select ALLWINNER_A10_DRAMC
     select ALLWINNER_EMAC
     select SERIAL
     select UNIMP
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config LASI
 config ALLWINNER_A10_CCM
     bool
 
+config ALLWINNER_A10_DRAMC
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ subdir('macio')
 softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c'))
 
 softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c'))
+softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_DRAMC', if_true: files('allwinner-a10-dramc.c'))
 softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c'))
 specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'))
 softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
-- 
2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

This patch implements Allwinner TWI/I2C controller emulation. Only
master-mode functionality is implemented.

The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this is
first part enabling the TWI/I2C bus operation.

Since both Allwinner A10 and H3 use the same module, it is added for
both boards.

Docs are also updated for Cubieboard and Orangepi-PC board to indicate
I2C availability.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20221226220303.14420-4-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/cubieboard.rst |   1 +
 docs/system/arm/orangepi.rst   |   1 +
 include/hw/arm/allwinner-a10.h |   2 +
 include/hw/arm/allwinner-h3.h  |   3 +
 include/hw/i2c/allwinner-i2c.h |  55 ++++
 hw/arm/allwinner-a10.c         |   8 +
 hw/arm/allwinner-h3.c          |  11 +-
 hw/i2c/allwinner-i2c.c         | 459 +++++++++++++++++++++++++++++++++
 hw/arm/Kconfig                 |   2 +
 hw/i2c/Kconfig                 |   4 +
 hw/i2c/meson.build             |   1 +
 hw/i2c/trace-events            |   5 +
 12 files changed, 551 insertions(+), 1 deletion(-)
 create mode 100644 include/hw/i2c/allwinner-i2c.h
 create mode 100644 hw/i2c/allwinner-i2c.c

diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/cubieboard.rst
+++ b/docs/system/arm/cubieboard.rst
@@ -XXX,XX +XXX,XX @@ Emulated devices:
 - SDHCI
 - USB controller
 - SATA controller
+- TWI (I2C) controller
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/orangepi.rst
+++ b/docs/system/arm/orangepi.rst
@@ -XXX,XX +XXX,XX @@ The Orange Pi PC machine supports the following devices:
  * Clock Control Unit
  * System Control module
  * Security Identifier device
+ * TWI (I2C)
 
 Limitations
 """""""""""
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/rtc/allwinner-rtc.h"
 #include "hw/misc/allwinner-a10-ccm.h"
 #include "hw/misc/allwinner-a10-dramc.h"
+#include "hw/i2c/allwinner-i2c.h"
 
 #include "target/arm/cpu.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
     AwEmacState emac;
     AllwinnerAHCIState sata;
     AwSdHostState mmc0;
+    AWI2CState i2c0;
     AwRtcState rtc;
     MemoryRegion sram_a;
     EHCISysBusState ehci[AW_A10_NUM_USB];
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/sd/allwinner-sdhost.h"
 #include "hw/net/allwinner-sun8i-emac.h"
 #include "hw/rtc/allwinner-rtc.h"
+#include "hw/i2c/allwinner-i2c.h"
 #include "target/arm/cpu.h"
 #include "sysemu/block-backend.h"
 
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_DEV_UART2,
     AW_H3_DEV_UART3,
     AW_H3_DEV_EMAC,
+    AW_H3_DEV_TWI0,
     AW_H3_DEV_DRAMCOM,
     AW_H3_DEV_DRAMCTL,
     AW_H3_DEV_DRAMPHY,
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
     AwH3SysCtrlState sysctrl;
     AwSidState sid;
     AwSdHostState mmc0;
+    AWI2CState i2c0;
     AwSun8iEmacState emac;
     AwRtcState rtc;
     GICState gic;
diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/i2c/allwinner-i2c.h
@@ -XXX,XX +XXX,XX @@
+/*
+ *  Allwinner I2C Bus Serial Interface registers definition
+ *
+ *  Copyright (C) 2022 Strahinja Jankovic. <strahinja.p.jankovic@gmail.com>
+ *
+ *  This file is derived from IMX I2C controller,
+ *  by Jean-Christophe DUBOIS .
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef ALLWINNER_I2C_H
+#define ALLWINNER_I2C_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_AW_I2C "allwinner.i2c"
+OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
+
+#define AW_I2C_MEM_SIZE         0x24
+
+struct AWI2CState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    MemoryRegion iomem;
+    I2CBus *bus;
+    qemu_irq irq;
+
+    uint8_t addr;
+    uint8_t xaddr;
+    uint8_t data;
+    uint8_t cntr;
+    uint8_t stat;
+    uint8_t ccr;
+    uint8_t srst;
+    uint8_t efr;
+    uint8_t lcr;
+};
+
+#endif /* ALLWINNER_I2C_H */
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@
 #define AW_A10_OHCI_BASE        0x01c14400
 #define AW_A10_SATA_BASE        0x01c18000
 #define AW_A10_RTC_BASE         0x01c20d00
+#define AW_A10_I2C0_BASE        0x01c2ac00
 
 static void aw_a10_init(Object *obj)
 {
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
 
     object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
 
+    object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
+
     if (machine_usb(current_machine)) {
         int i;
 
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     /* RTC */
     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
+
+    /* I2C */
+    sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
 }
 
 static void aw_a10_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
     [AW_H3_DEV_UART1]      = 0x01c28400,
     [AW_H3_DEV_UART2]      = 0x01c28800,
     [AW_H3_DEV_UART3]      = 0x01c28c00,
+    [AW_H3_DEV_TWI0]       = 0x01c2ac00,
     [AW_H3_DEV_EMAC]       = 0x01c30000,
     [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
     [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
     { "uart1",     0x01c28400, 1 * KiB },
     { "uart2",     0x01c28800, 1 * KiB },
     { "uart3",     0x01c28c00, 1 * KiB },
-    { "twi0",      0x01c2ac00, 1 * KiB },
     { "twi1",      0x01c2b000, 1 * KiB },
     { "twi2",      0x01c2b400, 1 * KiB },
     { "scr",       0x01c2c400, 1 * KiB },
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_GIC_SPI_UART1     =  1,
     AW_H3_GIC_SPI_UART2     =  2,
     AW_H3_GIC_SPI_UART3     =  3,
+    AW_H3_GIC_SPI_TWI0      =  6,
     AW_H3_GIC_SPI_TIMER0    = 18,
     AW_H3_GIC_SPI_TIMER1    = 19,
     AW_H3_GIC_SPI_MMC0      = 60,
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
                               "ram-size");
 
     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
+
+    object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
 }
 
 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
 
+    /* I2C */
+    sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_H3_DEV_TWI0]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
+                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
+
     /* Unimplemented devices */
     for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
         create_unimplemented_device(unimplemented[i].device_name,
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/i2c/allwinner-i2c.c
@@ -XXX,XX +XXX,XX @@
+/*
+ *  Allwinner I2C Bus Serial Interface Emulation
+ *
+ *  Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ *  This file is derived from IMX I2C controller,
+ *  by Jean-Christophe DUBOIS .
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "qemu/osdep.h"
+#include "hw/i2c/allwinner-i2c.h"
+#include "hw/irq.h"
+#include "migration/vmstate.h"
+#include "hw/i2c/i2c.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "qemu/module.h"
+
+/* Allwinner I2C memory map */
+#define TWI_ADDR_REG            0x00  /* slave address register */
+#define TWI_XADDR_REG           0x04  /* extended slave address register */
+#define TWI_DATA_REG            0x08  /* data register */
+#define TWI_CNTR_REG            0x0c  /* control register */
+#define TWI_STAT_REG            0x10  /* status register */
+#define TWI_CCR_REG             0x14  /* clock control register */
+#define TWI_SRST_REG            0x18  /* software reset register */
+#define TWI_EFR_REG             0x1c  /* enhance feature register */
+#define TWI_LCR_REG             0x20  /* line control register */
+
+/* Used only in slave mode, do not set */
+#define TWI_ADDR_RESET          0
+#define TWI_XADDR_RESET         0
+
+/* Data register */
+#define TWI_DATA_MASK           0xFF
+#define TWI_DATA_RESET          0
+
+/* Control register */
+#define TWI_CNTR_INT_EN         (1 << 7)
+#define TWI_CNTR_BUS_EN         (1 << 6)
+#define TWI_CNTR_M_STA          (1 << 5)
+#define TWI_CNTR_M_STP          (1 << 4)
+#define TWI_CNTR_INT_FLAG       (1 << 3)
+#define TWI_CNTR_A_ACK          (1 << 2)
+#define TWI_CNTR_MASK           0xFC
+#define TWI_CNTR_RESET          0
+
+/* Status register */
+#define TWI_STAT_MASK           0xF8
+#define TWI_STAT_RESET          0xF8
+
+/* Clock register */
+#define TWI_CCR_CLK_M_MASK      0x78
+#define TWI_CCR_CLK_N_MASK      0x07
+#define TWI_CCR_MASK            0x7F
+#define TWI_CCR_RESET           0
+
+/* Soft reset */
+#define TWI_SRST_MASK           0x01
+#define TWI_SRST_RESET          0
+
+/* Enhance feature */
+#define TWI_EFR_MASK            0x03
+#define TWI_EFR_RESET           0
+
+/* Line control */
+#define TWI_LCR_SCL_STATE       (1 << 5)
+#define TWI_LCR_SDA_STATE       (1 << 4)
+#define TWI_LCR_SCL_CTL         (1 << 3)
+#define TWI_LCR_SCL_CTL_EN      (1 << 2)
+#define TWI_LCR_SDA_CTL         (1 << 1)
+#define TWI_LCR_SDA_CTL_EN      (1 << 0)
+#define TWI_LCR_MASK            0x3F
+#define TWI_LCR_RESET           0x3A
+
+/* Status value in STAT register is shifted by 3 bits */
+#define TWI_STAT_SHIFT      3
+#define STAT_FROM_STA(x)    ((x) << TWI_STAT_SHIFT)
+#define STAT_TO_STA(x)      ((x) >> TWI_STAT_SHIFT)
+
+enum {
+    STAT_BUS_ERROR = 0,
+    /* Master mode */
+    STAT_M_STA_TX,
+    STAT_M_RSTA_TX,
+    STAT_M_ADDR_WR_ACK,
+    STAT_M_ADDR_WR_NACK,
+    STAT_M_DATA_TX_ACK,
+    STAT_M_DATA_TX_NACK,
+    STAT_M_ARB_LOST,
+    STAT_M_ADDR_RD_ACK,
+    STAT_M_ADDR_RD_NACK,
+    STAT_M_DATA_RX_ACK,
+    STAT_M_DATA_RX_NACK,
+    /* Slave mode */
+    STAT_S_ADDR_WR_ACK,
+    STAT_S_ARB_LOST_AW_ACK,
+    STAT_S_GCA_ACK,
+    STAT_S_ARB_LOST_GCA_ACK,
+    STAT_S_DATA_RX_SA_ACK,
+    STAT_S_DATA_RX_SA_NACK,
+    STAT_S_DATA_RX_GCA_ACK,
+    STAT_S_DATA_RX_GCA_NACK,
+    STAT_S_STP_RSTA,
+    STAT_S_ADDR_RD_ACK,
+    STAT_S_ARB_LOST_AR_ACK,
+    STAT_S_DATA_TX_ACK,
+    STAT_S_DATA_TX_NACK,
+    STAT_S_LB_TX_ACK,
+    /* Master mode, 10-bit */
+    STAT_M_2ND_ADDR_WR_ACK,
+    STAT_M_2ND_ADDR_WR_NACK,
+    /* Idle */
+    STAT_IDLE = 0x1f
+} TWI_STAT_STA;
+
+static const char *allwinner_i2c_get_regname(unsigned offset)
+{
+    switch (offset) {
+    case TWI_ADDR_REG:
+        return "ADDR";
+    case TWI_XADDR_REG:
+        return "XADDR";
+    case TWI_DATA_REG:
+        return "DATA";
+    case TWI_CNTR_REG:
+        return "CNTR";
+    case TWI_STAT_REG:
+        return "STAT";
+    case TWI_CCR_REG:
+        return "CCR";
+    case TWI_SRST_REG:
+        return "SRST";
+    case TWI_EFR_REG:
+        return "EFR";
+    case TWI_LCR_REG:
+        return "LCR";
+    default:
+        return "[?]";
+    }
+}
+
+static inline bool allwinner_i2c_is_reset(AWI2CState *s)
+{
+    return s->srst & TWI_SRST_MASK;
+}
+
+static inline bool allwinner_i2c_bus_is_enabled(AWI2CState *s)
+{
+    return s->cntr & TWI_CNTR_BUS_EN;
+}
+
+static inline bool allwinner_i2c_interrupt_is_enabled(AWI2CState *s)
+{
+    return s->cntr & TWI_CNTR_INT_EN;
+}
+
+static void allwinner_i2c_reset_hold(Object *obj)
+{
+    AWI2CState *s = AW_I2C(obj);
+
+    if (STAT_TO_STA(s->stat) != STAT_IDLE) {
+        i2c_end_transfer(s->bus);
+    }
+
+    s->addr  = TWI_ADDR_RESET;
+    s->xaddr = TWI_XADDR_RESET;
+    s->data  = TWI_DATA_RESET;
+    s->cntr  = TWI_CNTR_RESET;
+    s->stat  = TWI_STAT_RESET;
+    s->ccr   = TWI_CCR_RESET;
+    s->srst  = TWI_SRST_RESET;
+    s->efr   = TWI_EFR_RESET;
+    s->lcr   = TWI_LCR_RESET;
+}
+
+static inline void allwinner_i2c_raise_interrupt(AWI2CState *s)
+{
+    /*
+     * Raise an interrupt if the device is not reset and it is configured
+     * to generate some interrupts.
+     */
+    if (!allwinner_i2c_is_reset(s) && allwinner_i2c_bus_is_enabled(s)) {
+        if (STAT_TO_STA(s->stat) != STAT_IDLE) {
+            s->cntr |= TWI_CNTR_INT_FLAG;
+            if (allwinner_i2c_interrupt_is_enabled(s)) {
+                qemu_irq_raise(s->irq);
+            }
+        }
+    }
+}
+
+static uint64_t allwinner_i2c_read(void *opaque, hwaddr offset,
+                                   unsigned size)
+{
+    uint16_t value;
+    AWI2CState *s = AW_I2C(opaque);
+
+    switch (offset) {
+    case TWI_ADDR_REG:
+        value = s->addr;
+        break;
+    case TWI_XADDR_REG:
+        value = s->xaddr;
+        break;
+    case TWI_DATA_REG:
+        if ((STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) ||
+            (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) ||
+            (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK)) {
+            /* Get the next byte */
+            s->data = i2c_recv(s->bus);
+
+            if (s->cntr & TWI_CNTR_A_ACK) {
+                s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
+            } else {
+                s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
+            }
+            allwinner_i2c_raise_interrupt(s);
+        }
+        value = s->data;
+        break;
+    case TWI_CNTR_REG:
+        value = s->cntr;
+        break;
+    case TWI_STAT_REG:
+        value = s->stat;
+        /*
+         * If polling when reading then change state to indicate data
+         * is available
+         */
+        if (STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) {
+            if (s->cntr & TWI_CNTR_A_ACK) {
+                s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
+            } else {
+                s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
+            }
+            allwinner_i2c_raise_interrupt(s);
+        }
+        break;
+    case TWI_CCR_REG:
+        value = s->ccr;
+        break;
+    case TWI_SRST_REG:
+        value = s->srst;
+        break;
+    case TWI_EFR_REG:
+        value = s->efr;
+        break;
+    case TWI_LCR_REG:
+        value = s->lcr;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
+                      HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset);
+        value = 0;
+        break;
+    }
+
+    trace_allwinner_i2c_read(allwinner_i2c_get_regname(offset), offset, value);
+
+    return (uint64_t)value;
+}
+
+static void allwinner_i2c_write(void *opaque, hwaddr offset,
+                                uint64_t value, unsigned size)
+{
+    AWI2CState *s = AW_I2C(opaque);
+
+    value &= 0xff;
+
+    trace_allwinner_i2c_write(allwinner_i2c_get_regname(offset), offset, value);
+
+    switch (offset) {
+    case TWI_ADDR_REG:
+        s->addr = (uint8_t)value;
+        break;
+    case TWI_XADDR_REG:
+        s->xaddr = (uint8_t)value;
+        break;
+    case TWI_DATA_REG:
+        /* If the device is in reset or not enabled, nothing to do */
+        if (allwinner_i2c_is_reset(s) || (!allwinner_i2c_bus_is_enabled(s))) {
+            break;
+        }
+
+        s->data = value & TWI_DATA_MASK;
+
+        switch (STAT_TO_STA(s->stat)) {
+        case STAT_M_STA_TX:
+        case STAT_M_RSTA_TX:
+            /* Send address */
+            if (i2c_start_transfer(s->bus, extract32(s->data, 1, 7),
+                                extract32(s->data, 0, 1))) {
+                /* If non zero is returned, the address is not valid */
+                s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_NACK);
+            } else {
+                /* Determine if read of write */
+                if (extract32(s->data, 0, 1)) {
+                    s->stat = STAT_FROM_STA(STAT_M_ADDR_RD_ACK);
+                } else {
+                    s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_ACK);
+                }
+                allwinner_i2c_raise_interrupt(s);
+            }
+            break;
+        case STAT_M_ADDR_WR_ACK:
+        case STAT_M_DATA_TX_ACK:
+            if (i2c_send(s->bus, s->data)) {
+                /* If the target return non zero then end the transfer */
+                s->stat = STAT_FROM_STA(STAT_M_DATA_TX_NACK);
+                i2c_end_transfer(s->bus);
+            } else {
+                s->stat = STAT_FROM_STA(STAT_M_DATA_TX_ACK);
+                allwinner_i2c_raise_interrupt(s);
+            }
+            break;
+        default:
+            break;
+        }
+        break;
+    case TWI_CNTR_REG:
+        if (!allwinner_i2c_is_reset(s)) {
+            /* Do something only if not in software reset */
+            s->cntr = value & TWI_CNTR_MASK;
+
+            /* Check if start condition should be sent */
+            if (s->cntr & TWI_CNTR_M_STA) {
+                /* Update status */
+                if (STAT_TO_STA(s->stat) == STAT_IDLE) {
+                    /* Send start condition */
+                    s->stat = STAT_FROM_STA(STAT_M_STA_TX);
+                } else {
+                    /* Send repeated start condition */
+                    s->stat = STAT_FROM_STA(STAT_M_RSTA_TX);
+                }
+                /* Clear start condition */
+                s->cntr &= ~TWI_CNTR_M_STA;
+            }
+            if (s->cntr & TWI_CNTR_M_STP) {
+                /* Update status */
+                i2c_end_transfer(s->bus);
+                s->stat = STAT_FROM_STA(STAT_IDLE);
+                s->cntr &= ~TWI_CNTR_M_STP;
+            }
+            if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
+                /* Interrupt flag cleared */
+                qemu_irq_lower(s->irq);
+            }
+            if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
+                if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
+                    s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
+                }
+            } else {
+                if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK) {
+                    s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
+                }
+            }
+            allwinner_i2c_raise_interrupt(s);
+
+        }
+        break;
+    case TWI_CCR_REG:
+        s->ccr = value & TWI_CCR_MASK;
+        break;
+    case TWI_SRST_REG:
+        if (((value & TWI_SRST_MASK) == 0) && (s->srst & TWI_SRST_MASK)) {
+            /* Perform reset */
+            allwinner_i2c_reset_hold(OBJECT(s));
+        }
+        s->srst = value & TWI_SRST_MASK;
+        break;
+    case TWI_EFR_REG:
+        s->efr = value & TWI_EFR_MASK;
+        break;
+    case TWI_LCR_REG:
+        s->lcr = value & TWI_LCR_MASK;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
+                      HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset);
+        break;
+    }
+}
+
+static const MemoryRegionOps allwinner_i2c_ops = {
+    .read = allwinner_i2c_read,
+    .write = allwinner_i2c_write,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 4,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription allwinner_i2c_vmstate = {
+    .name = TYPE_AW_I2C,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8(addr, AWI2CState),
+        VMSTATE_UINT8(xaddr, AWI2CState),
+        VMSTATE_UINT8(data, AWI2CState),
+        VMSTATE_UINT8(cntr, AWI2CState),
+        VMSTATE_UINT8(ccr, AWI2CState),
+        VMSTATE_UINT8(srst, AWI2CState),
+        VMSTATE_UINT8(efr, AWI2CState),
+        VMSTATE_UINT8(lcr, AWI2CState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void allwinner_i2c_realize(DeviceState *dev, Error **errp)
+{
+    AWI2CState *s = AW_I2C(dev);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_i2c_ops, s,
+                          TYPE_AW_I2C, AW_I2C_MEM_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
+    sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
+    s->bus = i2c_init_bus(dev, "i2c");
+}
+
+static void allwinner_i2c_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    rc->phases.hold = allwinner_i2c_reset_hold;
+    dc->vmsd = &allwinner_i2c_vmstate;
+    dc->realize = allwinner_i2c_realize;
+    dc->desc = "Allwinner I2C Controller";
+}
+
+static const TypeInfo allwinner_i2c_type_info = {
+    .name = TYPE_AW_I2C,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(AWI2CState),
+    .class_init = allwinner_i2c_class_init,
+};
+
+static void allwinner_i2c_register_types(void)
+{
+    type_register_static(&allwinner_i2c_type_info);
+}
+
+type_init(allwinner_i2c_register_types)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
     select ALLWINNER_A10_CCM
     select ALLWINNER_A10_DRAMC
     select ALLWINNER_EMAC
+    select ALLWINNER_I2C
     select SERIAL
     select UNIMP
 
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
     bool
     select ALLWINNER_A10_PIT
     select ALLWINNER_SUN8I_EMAC
+    select ALLWINNER_I2C
     select SERIAL
     select ARM_TIMER
     select ARM_GIC
diff --git a/hw/i2c/Kconfig b/hw/i2c/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/Kconfig
+++ b/hw/i2c/Kconfig
@@ -XXX,XX +XXX,XX @@ config MPC_I2C
     bool
     select I2C
 
+config ALLWINNER_I2C
+    bool
+    select I2C
+
 config PCA954X
     bool
     select I2C
diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/meson.build
+++ b/hw/i2c/meson.build
@@ -XXX,XX +XXX,XX @@ i2c_ss.add(when: 'CONFIG_BITBANG_I2C', if_true: files('bitbang_i2c.c'))
 i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c'))
 i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c'))
 i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c'))
+i2c_ss.add(when: 'CONFIG_ALLWINNER_I2C', if_true: files('allwinner-i2c.c'))
 i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c'))
 i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c'))
 i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c'))
diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/trace-events
+++ b/hw/i2c/trace-events
@@ -XXX,XX +XXX,XX @@ i2c_send_async(uint8_t address, uint8_t data) "send_async(addr:0x%02x) data:0x%0
 i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x"
 i2c_ack(void) ""
 
+# allwinner_i2c.c
+
+allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value) "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64
+allwinner_i2c_write(const char* reg_name, uint64_t offset, uint64_t value) "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64
+
 # aspeed_i2c.c
 
 aspeed_i2c_bus_cmd(uint32_t cmd, const char *cmd_flags, uint32_t count, uint32_t intr_status) "handling cmd=0x%x %s count=%d intr=0x%x"
-- 
2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

This patch adds minimal support for AXP-209 PMU.
Most important is chip ID since U-Boot SPL expects version 0x1. Besides
the chip ID register, reset values for two more registers used by A10
U-Boot SPL are covered.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Message-id: 20221226220303.14420-5-strahinja.p.jankovic@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/axp209.c     | 238 +++++++++++++++++++++++++++++++++++++++++++
 MAINTAINERS          |   2 +
 hw/misc/Kconfig      |   4 +
 hw/misc/meson.build  |   1 +
 hw/misc/trace-events |   5 +
 5 files changed, 250 insertions(+)
 create mode 100644 hw/misc/axp209.c

diff --git a/hw/misc/axp209.c b/hw/misc/axp209.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/axp209.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * AXP-209 PMU Emulation
+ *
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "hw/i2c/i2c.h"
+#include "migration/vmstate.h"
+
+#define TYPE_AXP209_PMU "axp209_pmu"
+
+#define AXP209(obj) \
+    OBJECT_CHECK(AXP209I2CState, (obj), TYPE_AXP209_PMU)
+
+/* registers */
+enum {
+    REG_POWER_STATUS = 0x0u,
+    REG_OPERATING_MODE,
+    REG_OTG_VBUS_STATUS,
+    REG_CHIP_VERSION,
+    REG_DATA_CACHE_0,
+    REG_DATA_CACHE_1,
+    REG_DATA_CACHE_2,
+    REG_DATA_CACHE_3,
+    REG_DATA_CACHE_4,
+    REG_DATA_CACHE_5,
+    REG_DATA_CACHE_6,
+    REG_DATA_CACHE_7,
+    REG_DATA_CACHE_8,
+    REG_DATA_CACHE_9,
+    REG_DATA_CACHE_A,
+    REG_DATA_CACHE_B,
+    REG_POWER_OUTPUT_CTRL = 0x12u,
+    REG_DC_DC2_OUT_V_CTRL = 0x23u,
+    REG_DC_DC2_DVS_CTRL = 0x25u,
+    REG_DC_DC3_OUT_V_CTRL = 0x27u,
+    REG_LDO2_4_OUT_V_CTRL,
+    REG_LDO3_OUT_V_CTRL,
+    REG_VBUS_CH_MGMT = 0x30u,
+    REG_SHUTDOWN_V_CTRL,
+    REG_SHUTDOWN_CTRL,
+    REG_CHARGE_CTRL_1,
+    REG_CHARGE_CTRL_2,
+    REG_SPARE_CHARGE_CTRL,
+    REG_PEK_KEY_CTRL,
+    REG_DC_DC_FREQ_SET,
+    REG_CHR_TEMP_TH_SET,
+    REG_CHR_HIGH_TEMP_TH_CTRL,
+    REG_IPSOUT_WARN_L1,
+    REG_IPSOUT_WARN_L2,
+    REG_DISCHR_TEMP_TH_SET,
+    REG_DISCHR_HIGH_TEMP_TH_CTRL,
+    REG_IRQ_BANK_1_CTRL = 0x40u,
+    REG_IRQ_BANK_2_CTRL,
+    REG_IRQ_BANK_3_CTRL,
+    REG_IRQ_BANK_4_CTRL,
+    REG_IRQ_BANK_5_CTRL,
+    REG_IRQ_BANK_1_STAT = 0x48u,
+    REG_IRQ_BANK_2_STAT,
+    REG_IRQ_BANK_3_STAT,
+    REG_IRQ_BANK_4_STAT,
+    REG_IRQ_BANK_5_STAT,
+    REG_ADC_ACIN_V_H = 0x56u,
+    REG_ADC_ACIN_V_L,
+    REG_ADC_ACIN_CURR_H,
+    REG_ADC_ACIN_CURR_L,
+    REG_ADC_VBUS_V_H,
+    REG_ADC_VBUS_V_L,
+    REG_ADC_VBUS_CURR_H,
+    REG_ADC_VBUS_CURR_L,
+    REG_ADC_INT_TEMP_H,
+    REG_ADC_INT_TEMP_L,
+    REG_ADC_TEMP_SENS_V_H = 0x62u,
+    REG_ADC_TEMP_SENS_V_L,
+    REG_ADC_BAT_V_H = 0x78u,
+    REG_ADC_BAT_V_L,
+    REG_ADC_BAT_DISCHR_CURR_H,
+    REG_ADC_BAT_DISCHR_CURR_L,
+    REG_ADC_BAT_CHR_CURR_H,
+    REG_ADC_BAT_CHR_CURR_L,
+    REG_ADC_IPSOUT_V_H,
+    REG_ADC_IPSOUT_V_L,
+    REG_DC_DC_MOD_SEL = 0x80u,
+    REG_ADC_EN_1,
+    REG_ADC_EN_2,
+    REG_ADC_SR_CTRL,
+    REG_ADC_IN_RANGE,
+    REG_GPIO1_ADC_IRQ_RISING_TH,
+    REG_GPIO1_ADC_IRQ_FALLING_TH,
+    REG_TIMER_CTRL = 0x8au,
+    REG_VBUS_CTRL_MON_SRP,
+    REG_OVER_TEMP_SHUTDOWN = 0x8fu,
+    REG_GPIO0_FEAT_SET,
+    REG_GPIO_OUT_HIGH_SET,
+    REG_GPIO1_FEAT_SET,
+    REG_GPIO2_FEAT_SET,
+    REG_GPIO_SIG_STATE_SET_MON,
+    REG_GPIO3_SET,
+    REG_COULOMB_CNTR_CTRL = 0xb8u,
+    REG_POWER_MEAS_RES,
+    NR_REGS
+};
+
+#define AXP209_CHIP_VERSION_ID             (0x01)
+#define AXP209_DC_DC2_OUT_V_CTRL_RESET     (0x16)
+#define AXP209_IRQ_BANK_1_CTRL_RESET       (0xd8)
+
+/* A simple I2C slave which returns values of ID or CNT register. */
+typedef struct AXP209I2CState {
+    /*< private >*/
+    I2CSlave i2c;
+    /*< public >*/
+    uint8_t regs[NR_REGS];  /* peripheral registers */
+    uint8_t ptr;            /* current register index */
+    uint8_t count;          /* counter used for tx/rx */
+} AXP209I2CState;
+
+/* Reset all counters and load ID register */
+static void axp209_reset_enter(Object *obj, ResetType type)
+{
+    AXP209I2CState *s = AXP209(obj);
+
+    memset(s->regs, 0, NR_REGS);
+    s->ptr = 0;
+    s->count = 0;
+    s->regs[REG_CHIP_VERSION] = AXP209_CHIP_VERSION_ID;
+    s->regs[REG_DC_DC2_OUT_V_CTRL] = AXP209_DC_DC2_OUT_V_CTRL_RESET;
+    s->regs[REG_IRQ_BANK_1_CTRL] = AXP209_IRQ_BANK_1_CTRL_RESET;
+}
+
+/* Handle events from master. */
+static int axp209_event(I2CSlave *i2c, enum i2c_event event)
+{
+    AXP209I2CState *s = AXP209(i2c);
+
+    s->count = 0;
+
+    return 0;
+}
+
+/* Called when master requests read */
+static uint8_t axp209_rx(I2CSlave *i2c)
+{
+    AXP209I2CState *s = AXP209(i2c);
+    uint8_t ret = 0xff;
+
+    if (s->ptr < NR_REGS) {
+        ret = s->regs[s->ptr++];
+    }
+
+    trace_axp209_rx(s->ptr - 1, ret);
+
+    return ret;
+}
+
+/*
+ * Called when master sends write.
+ * Update ptr with byte 0, then perform write with second byte.
+ */
+static int axp209_tx(I2CSlave *i2c, uint8_t data)
+{
+    AXP209I2CState *s = AXP209(i2c);
+
+    if (s->count == 0) {
+        /* Store register address */
+        s->ptr = data;
+        s->count++;
+        trace_axp209_select(data);
+    } else {
+        trace_axp209_tx(s->ptr, data);
+        if (s->ptr == REG_DC_DC2_OUT_V_CTRL) {
+            s->regs[s->ptr++] = data;
+        }
+    }
+
+    return 0;
+}
+
+static const VMStateDescription vmstate_axp209 = {
+    .name = TYPE_AXP209_PMU,
+    .version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8_ARRAY(regs, AXP209I2CState, NR_REGS),
+        VMSTATE_UINT8(count, AXP209I2CState),
+        VMSTATE_UINT8(ptr, AXP209I2CState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void axp209_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    I2CSlaveClass *isc = I2C_SLAVE_CLASS(oc);
+    ResettableClass *rc = RESETTABLE_CLASS(oc);
+
+    rc->phases.enter = axp209_reset_enter;
+    dc->vmsd = &vmstate_axp209;
+    isc->event = axp209_event;
+    isc->recv = axp209_rx;
+    isc->send = axp209_tx;
+}
+
+static const TypeInfo axp209_info = {
+    .name = TYPE_AXP209_PMU,
+    .parent = TYPE_I2C_SLAVE,
+    .instance_size = sizeof(AXP209I2CState),
+    .class_init = axp209_class_init
+};
+
+static void axp209_register_devices(void)
+{
+    type_register_static(&axp209_info);
+}
+
+type_init(axp209_register_devices);
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ ARM Machines
 Allwinner-a10
 M: Beniamino Galvani <b.galvani@gmail.com>
 M: Peter Maydell <peter.maydell@linaro.org>
+R: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
 L: qemu-arm@nongnu.org
 S: Odd Fixes
 F: hw/*/allwinner*
 F: include/hw/*/allwinner*
 F: hw/arm/cubieboard.c
 F: docs/system/arm/cubieboard.rst
+F: hw/misc/axp209.c
 
 Allwinner-h3
 M: Niek Linnenbank <nieklinnenbank@gmail.com>
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10_CCM
 config ALLWINNER_A10_DRAMC
     bool
 
+config AXP209_PMU
+    bool
+    depends on I2C
+
 source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'
 softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
 softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-sysctrl.c'))
 softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sid.c'))
+softmmu_ss.add(when: 'CONFIG_AXP209_PMU', if_true: files('axp209.c'))
 softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
 softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c'))
 softmmu_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c'))
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%"
 avr_power_read(uint8_t value) "power_reduc read value:%u"
 avr_power_write(uint8_t value) "power_reduc write value:%u"
 
+# axp209.c
+axp209_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
+axp209_select(uint8_t reg) "Accessing reg 0x%" PRIx8
+axp209_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
+
 # eccmemctl.c
 ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
 ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
-- 
2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

SPL Boot for Cubieboard expects AXP209 connected to I2C0 bus.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221226220303.14420-6-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/cubieboard.c | 6 ++++++
 hw/arm/Kconfig      | 1 +
 2 files changed, 7 insertions(+)

diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "hw/qdev-properties.h"
 #include "hw/arm/allwinner-a10.h"
+#include "hw/i2c/i2c.h"
 
 static struct arm_boot_info cubieboard_binfo = {
     .loader_start = AW_A10_SDRAM_BASE,
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
     BlockBackend *blk;
     BusState *bus;
     DeviceState *carddev;
+    I2CBus *i2c;
 
     /* BIOS is not supported by this board */
     if (machine->firmware) {
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
         exit(1);
     }
 
+    /* Connect AXP 209 */
+    i2c = I2C_BUS(qdev_get_child_bus(DEVICE(&a10->i2c0), "i2c"));
+    i2c_slave_create_simple(i2c, "axp209_pmu", 0x34);
+
     /* Retrieve SD bus */
     di = drive_get(IF_SD, 0, 0);
     blk = di ? blk_by_legacy_dinfo(di) : NULL;
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
     select ALLWINNER_A10_DRAMC
     select ALLWINNER_EMAC
     select ALLWINNER_I2C
+    select AXP209_PMU
     select SERIAL
     select UNIMP
 
-- 
2.34.1

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

This patch enables copying of SPL from MMC if `-kernel` parameter is not
passed when starting QEMU. SPL is copied to SRAM_A.

The approach is reused from Allwinner H3 implementation.

Tested with Armbian and custom Yocto image.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>

Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20221226220303.14420-7-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/allwinner-a10.h | 21 +++++++++++++++++++++
 hw/arm/allwinner-a10.c         | 18 ++++++++++++++++++
 hw/arm/cubieboard.c            |  5 +++++
 3 files changed, 44 insertions(+)

From: Strahinja Jankovic <strahinjapjankovic@gmail.com>

Cubieboard now can boot directly from SD card, without the need to pass
`-kernel` parameter. Update Avocado tests to cover this functionality.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20221226220303.14420-8-strahinja.p.jankovic@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/boot_linux_console.py | 47 +++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
                                                 'sda')
         # cubieboard's reboot is not functioning; omit reboot test.
 
+    @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
+    def test_arm_cubieboard_openwrt_22_03_2(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:cubieboard
+        :avocado: tags=device:sd
+        """
+
+        # This test download a 7.5 MiB compressed image and expand it
+        # to 126 MiB.
+        image_url = ('https://downloads.openwrt.org/releases/22.03.2/targets/'
+                     'sunxi/cortexa8/openwrt-22.03.2-sunxi-cortexa8-'
+                     'cubietech_a10-cubieboard-ext4-sdcard.img.gz')
+        image_hash = ('94b5ecbfbc0b3b56276e5146b899eafa'
+                      '2ac5dc2d08733d6705af9f144f39f554')
+        image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash,
+                                         algorithm='sha256')
+        image_path = archive.extract(image_path_gz, self.workdir)
+        image_pow2ceil_expand(image_path)
+
+        self.vm.set_console()
+        self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
+                         '-nic', 'user',
+                         '-no-reboot')
+        self.vm.launch()
+
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'usbcore.nousb '
+                               'noreboot')
+
+        self.wait_for_console_pattern('U-Boot SPL')
+
+        interrupt_interactive_console_until_pattern(
+                self, 'Hit any key to stop autoboot:', '=>')
+        exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
+                                                kernel_command_line + "'", '=>')
+        exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
+
+        self.wait_for_console_pattern(
+            'Please press Enter to activate this console.')
+
+        exec_command_and_wait_for_pattern(self, ' ', 'root@')
+
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                                'Allwinner sun4i/sun5i')
+        # cubieboard's reboot is not functioning; omit reboot test.
+
     @skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout')
     def test_arm_quanta_gsj(self):
         """
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Don't dereference CPUTLBEntryFull until we verify that
the page is valid.  Move the other user-only info field
updates after the valid check to match.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1412
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230104190056.305143-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sve_helper.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
 #ifdef CONFIG_USER_ONLY
     flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
                                &info->host, retaddr);
-    memset(&info->attrs, 0, sizeof(info->attrs));
-    /* Require both ANON and MTE; see allocation_tag_mem(). */
-    info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
 #else
     CPUTLBEntryFull *full;
     flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
                               &info->host, &full, retaddr);
-    info->attrs = full->attrs;
-    info->tagged = full->pte_attrs == 0xf0;
 #endif
     info->flags = flags;
 
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
         return false;
     }
 
+#ifdef CONFIG_USER_ONLY
+    memset(&info->attrs, 0, sizeof(info->attrs));
+    /* Require both ANON and MTE; see allocation_tag_mem(). */
+    info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
+#else
+    info->attrs = full->attrs;
+    info->tagged = full->pte_attrs == 0xf0;
+#endif
+
     /* Ensure that info->host[] is relative to addr, not addr + mem_off. */
     info->host -= mem_off;
     return true;
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Since pxa255_init() must map the device in the system memory,
there is no point in passing get_system_memory() by argument.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/pxa.h | 2 +-
 hw/arm/gumstix.c     | 3 +--
 hw/arm/pxa2xx.c      | 4 +++-
 hw/arm/tosa.c        | 2 +-
 4 files changed, 6 insertions(+), 5 deletions(-)

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Since pxa270_init() must map the device in the system memory,
there is no point in passing get_system_memory() by argument.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/pxa.h |  3 +--
 hw/arm/gumstix.c     |  3 +--
 hw/arm/mainstone.c   | 10 ++++------
 hw/arm/pxa2xx.c      |  4 ++--
 hw/arm/spitz.c       |  6 ++----
 hw/arm/z2.c          |  3 +--
 6 files changed, 11 insertions(+), 18 deletions(-)

diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/pxa.h
+++ b/include/hw/arm/pxa.h
@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
 
 # define PA_FMT			"0x%08lx"
 
-PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
-                         const char *revision);
+PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
 PXA2xxState *pxa255_init(unsigned int sdram_size);
 
 #endif /* PXA_H */
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/gumstix.c
+++ b/hw/arm/gumstix.c
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
 {
     PXA2xxState *cpu;
     DriveInfo *dinfo;
-    MemoryRegion *address_space_mem = get_system_memory();
 
     uint32_t verdex_rom = 0x02000000;
     uint32_t verdex_ram = 0x10000000;
 
-    cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);
+    cpu = pxa270_init(verdex_ram, machine->cpu_type);
 
     dinfo = drive_get(IF_PFLASH, 0, 0);
     if (!dinfo && !qtest_enabled()) {
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info mainstone_binfo = {
     .ram_size = 0x04000000,
 };
 
-static void mainstone_common_init(MemoryRegion *address_space_mem,
-                                  MachineState *machine,
+static void mainstone_common_init(MachineState *machine,
                                   enum mainstone_model_e model, int arm_id)
 {
     uint32_t sector_len = 256 * 1024;
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
     MemoryRegion *rom = g_new(MemoryRegion, 1);
 
     /* Setup CPU & memory */
-    mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
-                      machine->cpu_type);
+    mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
     memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
                            &error_fatal);
-    memory_region_add_subregion(address_space_mem, 0, rom);
+    memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
 
     /* There are two 32MiB flash devices on the board */
     for (i = 0; i < 2; i ++) {
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
 
 static void mainstone_init(MachineState *machine)
 {
-    mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
+    mainstone_common_init(machine, mainstone, 0x196);
 }
 
 static void mainstone2_machine_init(MachineClass *mc)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_reset(void *opaque, int line, int level)
 }
 
 /* Initialise a PXA270 integrated chip (ARM based core).  */
-PXA2xxState *pxa270_init(MemoryRegion *address_space,
-                         unsigned int sdram_size, const char *cpu_type)
+PXA2xxState *pxa270_init(unsigned int sdram_size, const char *cpu_type)
 {
+    MemoryRegion *address_space = get_system_memory();
     PXA2xxState *s;
     int i;
     DriveInfo *dinfo;
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
     SpitzMachineState *sms = SPITZ_MACHINE(machine);
     enum spitz_model_e model = smc->model;
     PXA2xxState *mpu;
-    MemoryRegion *address_space_mem = get_system_memory();
     MemoryRegion *rom = g_new(MemoryRegion, 1);
 
     /* Setup CPU & memory */
-    mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
-                      machine->cpu_type);
+    mpu = pxa270_init(spitz_binfo.ram_size, machine->cpu_type);
     sms->mpu = mpu;
 
     sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
 
     memory_region_init_rom(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal);
-    memory_region_add_subregion(address_space_mem, 0, rom);
+    memory_region_add_subregion(get_system_memory(), 0, rom);
 
     /* Setup peripherals */
     spitz_keyboard_register(mpu);
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aer915_info = {
 
 static void z2_init(MachineState *machine)
 {
-    MemoryRegion *address_space_mem = get_system_memory();
     uint32_t sector_len = 0x10000;
     PXA2xxState *mpu;
     DriveInfo *dinfo;
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
     DeviceState *wm;
 
     /* Setup CPU & memory */
-    mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);
+    mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type);
 
     dinfo = drive_get(IF_PFLASH, 0, 0);
     if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

IEC binary prefixes ease code review: the unit is explicit.

Add definitions for RAM / Flash / Flash blocksize.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/collie.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "qom/object.h"
 
+#define RAM_SIZE            (512 * MiB)
+#define FLASH_SIZE          (32 * MiB)
+#define FLASH_SECTOR_SIZE   (64 * KiB)
+
 struct CollieMachineState {
     MachineState parent;
 
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(CollieMachineState, COLLIE_MACHINE)
 
 static struct arm_boot_info collie_binfo = {
     .loader_start = SA_SDCS0,
-    .ram_size = 0x20000000,
+    .ram_size = RAM_SIZE,
 };
 
 static void collie_init(MachineState *machine)
@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
     memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
 
     dinfo = drive_get(IF_PFLASH, 0, 0);
-    pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000,
+    pflash_cfi01_register(SA_CS0, "collie.fl1", FLASH_SIZE,
                     dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                    64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
+                    FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
 
     dinfo = drive_get(IF_PFLASH, 0, 1);
-    pflash_cfi01_register(SA_CS1, "collie.fl2", 0x02000000,
+    pflash_cfi01_register(SA_CS1, "collie.fl2", FLASH_SIZE,
                     dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                    64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
+                    FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
 
     sysbus_create_simple("scoop", 0x40800000, NULL);
 
@@ -XXX,XX +XXX,XX @@ static void collie_machine_class_init(ObjectClass *oc, void *data)
     mc->init = collie_init;
     mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110");
-    mc->default_ram_size = 0x20000000;
+    mc->default_ram_size = RAM_SIZE;
     mc->default_ram_id = "strongarm.sdram";
 }
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/collie.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info collie_binfo = {
 
 static void collie_init(MachineState *machine)
 {
-    DriveInfo *dinfo;
     MachineClass *mc = MACHINE_GET_CLASS(machine);
     CollieMachineState *cms = COLLIE_MACHINE(machine);
 
@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
 
     memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
 
-    dinfo = drive_get(IF_PFLASH, 0, 0);
-    pflash_cfi01_register(SA_CS0, "collie.fl1", FLASH_SIZE,
-                    dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                    FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
-
-    dinfo = drive_get(IF_PFLASH, 0, 1);
-    pflash_cfi01_register(SA_CS1, "collie.fl2", FLASH_SIZE,
-                    dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                    FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
+    for (unsigned i = 0; i < 2; i++) {
+        DriveInfo *dinfo = drive_get(IF_PFLASH, 0, i);
+        pflash_cfi01_register(i ? SA_CS1 : SA_CS0,
+                              i ? "collie.fl2" : "collie.fl1", FLASH_SIZE,
+                              dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+                              FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
+    }
 
     sysbus_create_simple("scoop", 0x40800000, NULL);
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a comment describing the Connex uses a Numonyx RC28F128J3F75
flash, and the Verdex uses a Micron RC28F256P30TFA.

Correct the Verdex machine description (we model the 'Pro' board).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-6-philmd@linaro.org
Message-Id: <20200223231044.8003-3-philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/gumstix.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/gumstix.c
+++ b/hw/arm/gumstix.c
@@ -XXX,XX +XXX,XX @@
  * Contributions after 2012-01-13 are licensed under the terms of the
  * GNU GPL, version 2 or (at your option) any later version.
  */
- 
+
 /* 
  * Example usage:
  * 
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
         exit(1);
     }
 
+    /* Numonyx RC28F128J3F75 */
     if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom,
                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                                sector_len, 2, 0, 0, 0, 0, 0)) {
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
         exit(1);
     }
 
+    /* Micron RC28F256P30TFA */
     if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom,
                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                                sector_len, 2, 0, 0, 0, 0, 0)) {
@@ -XXX,XX +XXX,XX @@ static void verdex_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
 
-    mc->desc = "Gumstix Verdex (PXA270)";
+    mc->desc = "Gumstix Verdex Pro XL6P COMs (PXA270)";
     mc->init = verdex_init;
     mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
-- 
2.34.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

IEC binary prefixes ease code review: the unit is explicit.

Add definitions for RAM / Flash / Flash blocksize.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-7-philmd@linaro.org
Message-Id: <20200223231044.8003-3-philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/gumstix.c | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/gumstix.c
+++ b/hw/arm/gumstix.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "qemu/error-report.h"
 #include "hw/arm/pxa.h"
 #include "net/net.h"
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/qtest.h"
 #include "cpu.h"
 
-static const int sector_len = 128 * 1024;
+#define CONNEX_FLASH_SIZE   (16 * MiB)
+#define CONNEX_RAM_SIZE     (64 * MiB)
+
+#define VERDEX_FLASH_SIZE   (32 * MiB)
+#define VERDEX_RAM_SIZE     (256 * MiB)
+
+#define FLASH_SECTOR_SIZE   (128 * KiB)
 
 static void connex_init(MachineState *machine)
 {
     PXA2xxState *cpu;
     DriveInfo *dinfo;
 
-    uint32_t connex_rom = 0x01000000;
-    uint32_t connex_ram = 0x04000000;
-
-    cpu = pxa255_init(connex_ram);
+    cpu = pxa255_init(CONNEX_RAM_SIZE);
 
     dinfo = drive_get(IF_PFLASH, 0, 0);
     if (!dinfo && !qtest_enabled()) {
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
     }
 
     /* Numonyx RC28F128J3F75 */
-    if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom,
+    if (!pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                               sector_len, 2, 0, 0, 0, 0, 0)) {
+                               FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
         error_report("Error registering flash memory");
         exit(1);
     }
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
     PXA2xxState *cpu;
     DriveInfo *dinfo;
 
-    uint32_t verdex_rom = 0x02000000;
-    uint32_t verdex_ram = 0x10000000;
-
-    cpu = pxa270_init(verdex_ram, machine->cpu_type);
+    cpu = pxa270_init(VERDEX_RAM_SIZE, machine->cpu_type);
 
     dinfo = drive_get(IF_PFLASH, 0, 0);
     if (!dinfo && !qtest_enabled()) {
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
     }
 
     /* Micron RC28F256P30TFA */
-    if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom,
+    if (!pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                               sector_len, 2, 0, 0, 0, 0, 0)) {
+                               FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
         error_report("Error registering flash memory");
         exit(1);
     }
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

IEC binary prefixes ease code review: the unit is explicit.

Add the FLASH_SECTOR_SIZE definition.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mainstone.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -XXX,XX +XXX,XX @@
  * GNU GPL, version 2 or (at your option) any later version.
  */
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
 #include "hw/arm/pxa.h"
@@ -XXX,XX +XXX,XX @@ static const struct keymap map[0xE0] = {
 
 enum mainstone_model_e { mainstone };
 
-#define MAINSTONE_RAM	0x04000000
-#define MAINSTONE_ROM	0x00800000
-#define MAINSTONE_FLASH	0x02000000
+#define MAINSTONE_RAM_SIZE      (64 * MiB)
+#define MAINSTONE_ROM_SIZE      (8 * MiB)
+#define MAINSTONE_FLASH_SIZE    (32 * MiB)
 
 static struct arm_boot_info mainstone_binfo = {
     .loader_start = PXA2XX_SDRAM_BASE,
-    .ram_size = 0x04000000,
+    .ram_size = MAINSTONE_RAM_SIZE,
 };
 
+#define FLASH_SECTOR_SIZE   (256 * KiB)
+
 static void mainstone_common_init(MachineState *machine,
                                   enum mainstone_model_e model, int arm_id)
 {
-    uint32_t sector_len = 256 * 1024;
     hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
     PXA2xxState *mpu;
     DeviceState *mst_irq;
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
 
     /* Setup CPU & memory */
     mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
-    memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
+    memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM_SIZE,
                            &error_fatal);
     memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
 
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
         dinfo = drive_get(IF_PFLASH, 0, i);
         if (!pflash_cfi01_register(mainstone_flash_base[i],
                                    i ? "mainstone.flash1" : "mainstone.flash0",
-                                   MAINSTONE_FLASH,
+                                   MAINSTONE_FLASH_SIZE,
                                    dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                                   sector_len, 4, 0, 0, 0, 0, 0)) {
+                                   FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
             error_report("Error registering flash memory");
             exit(1);
         }
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

IEC binary prefixes ease code review: the unit is explicit.

Add the FLASH_SECTOR_SIZE definition.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/musicpal.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "qapi/error.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
@@ -XXX,XX +XXX,XX @@ static const TypeInfo musicpal_key_info = {
     .class_init    = musicpal_key_class_init,
 };
 
+#define FLASH_SECTOR_SIZE   (64 * KiB)
+
 static struct arm_boot_info musicpal_binfo = {
     .loader_start = 0x0,
     .board_id = 0x20e,
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
 
         flash_size = blk_getlength(blk);
-        if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
-            flash_size != 32*1024*1024) {
+        if (flash_size != 8 * MiB && flash_size != 16 * MiB &&
+            flash_size != 32 * MiB) {
             error_report("Invalid flash image size");
             exit(1);
         }
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
          */
         pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX,
                               "musicpal.flash", flash_size,
-                              blk, 0x10000,
+                              blk, FLASH_SECTOR_SIZE,
                               MP_FLASH_SIZE_MAX / flash_size,
                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
                               0x5555, 0x2AAA, 0);
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

IEC binary prefixes ease code review: the unit is explicit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/omap_sx1.c | 33 +++++++++++++++++----------------
 1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -XXX,XX +XXX,XX @@
  * with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "qapi/error.h"
 #include "ui/console.h"
 #include "hw/arm/omap.h"
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps static_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-#define sdram_size	0x02000000
-#define sector_size	(128 * 1024)
-#define flash0_size	(16 * 1024 * 1024)
-#define flash1_size	( 8 * 1024 * 1024)
-#define flash2_size	(32 * 1024 * 1024)
+#define SDRAM_SIZE      (32 * MiB)
+#define SECTOR_SIZE     (128 * KiB)
+#define FLASH0_SIZE     (16 * MiB)
+#define FLASH1_SIZE     (8 * MiB)
+#define FLASH2_SIZE     (32 * MiB)
 
 static struct arm_boot_info sx1_binfo = {
     .loader_start = OMAP_EMIFF_BASE,
-    .ram_size = sdram_size,
+    .ram_size = SDRAM_SIZE,
     .board_id = 0x265,
 };
 
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
     static uint32_t cs3val = 0x00001139;
     DriveInfo *dinfo;
     int fl_idx;
-    uint32_t flash_size = flash0_size;
+    uint32_t flash_size = FLASH0_SIZE;
 
     if (machine->ram_size != mc->default_ram_size) {
         char *sz = size_to_str(mc->default_ram_size);
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
     }
 
     if (version == 2) {
-        flash_size = flash2_size;
+        flash_size = FLASH2_SIZE;
     }
 
     memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram);
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
         if (!pflash_cfi01_register(OMAP_CS0_BASE,
                                    "omap_sx1.flash0-1", flash_size,
                                    blk_by_legacy_dinfo(dinfo),
-                                   sector_size, 4, 0, 0, 0, 0, 0)) {
+                                   SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
             fprintf(stderr, "qemu: Error registering flash memory %d.\n",
                            fl_idx);
         }
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
             (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
         MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
         memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0",
-                               flash1_size, &error_fatal);
+                               FLASH1_SIZE, &error_fatal);
         memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
 
         memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
-                              "sx1.cs1", OMAP_CS1_SIZE - flash1_size);
+                              "sx1.cs1", OMAP_CS1_SIZE - FLASH1_SIZE);
         memory_region_add_subregion(address_space,
-                                OMAP_CS1_BASE + flash1_size, &cs[1]);
+                                OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
 
         if (!pflash_cfi01_register(OMAP_CS1_BASE,
-                                   "omap_sx1.flash1-1", flash1_size,
+                                   "omap_sx1.flash1-1", FLASH1_SIZE,
                                    blk_by_legacy_dinfo(dinfo),
-                                   sector_size, 4, 0, 0, 0, 0, 0)) {
+                                   SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
             fprintf(stderr, "qemu: Error registering flash memory %d.\n",
                            fl_idx);
         }
@@ -XXX,XX +XXX,XX @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
     mc->init = sx1_init_v2;
     mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
-    mc->default_ram_size = sdram_size;
+    mc->default_ram_size = SDRAM_SIZE;
     mc->default_ram_id = "omap1.dram";
 }
 
@@ -XXX,XX +XXX,XX @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
     mc->init = sx1_init_v1;
     mc->ignore_memory_transaction_failures = true;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
-    mc->default_ram_size = sdram_size;
+    mc->default_ram_size = SDRAM_SIZE;
     mc->default_ram_id = "omap1.dram";
 }
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

IEC binary prefixes ease code review: the unit is explicit.

Add the FLASH_SECTOR_SIZE definition.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-12-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/z2.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "hw/arm/pxa.h"
 #include "hw/arm/boot.h"
 #include "hw/i2c/i2c.h"
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aer915_info = {
     .class_init    = aer915_class_init,
 };
 
+#define FLASH_SECTOR_SIZE   (64 * KiB)
+
 static void z2_init(MachineState *machine)
 {
-    uint32_t sector_len = 0x10000;
     PXA2xxState *mpu;
     DriveInfo *dinfo;
     void *z2_lcd;
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
     dinfo = drive_get(IF_PFLASH, 0, 0);
     if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
                                dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                               sector_len, 4, 0, 0, 0, 0, 0)) {
+                               FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
         error_report("Error registering flash memory");
         exit(1);
     }
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Upon introduction in commit b8433303fb ("Set proper device-width
for vexpress flash"), ve_pflash_cfi01_register() was calling
qdev_init_nofail() which can not fail. This call was later
converted with a script to use &error_fatal, still unable to
fail. Remove the unreachable code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-13-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/vexpress.c | 10 +---------
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
     dinfo = drive_get(IF_PFLASH, 0, 0);
     pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
                                        dinfo);
-    if (!pflash0) {
-        error_report("vexpress: error registering flash 0");
-        exit(1);
-    }
 
     if (map[VE_NORFLASHALIAS] != -1) {
         /* Map flash 0 as an alias into low memory */
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
     }
 
     dinfo = drive_get(IF_PFLASH, 0, 1);
-    if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
-                                  dinfo)) {
-        error_report("vexpress: error registering flash 1");
-        exit(1);
-    }
+    ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo);
 
     sram_size = 0x2000000;
     memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Since its QOM'ification in commit 368a354f02 ("pflash_cfi0x:
QOMified") the pflash_cfi01_register() function does not fail.

This call was later converted with a script to use &error_fatal,
still unable to fail. Remove the unreachable code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109115316.2235-14-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/gumstix.c     | 18 ++++++------------
 hw/arm/mainstone.c   | 13 +++++--------
 hw/arm/omap_sx1.c    | 22 ++++++++--------------
 hw/arm/versatilepb.c |  6 ++----
 hw/arm/z2.c          |  9 +++------
 5 files changed, 24 insertions(+), 44 deletions(-)

diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/gumstix.c
+++ b/hw/arm/gumstix.c
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
     }
 
     /* Numonyx RC28F128J3F75 */
-    if (!pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
-                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                               FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
-        error_report("Error registering flash memory");
-        exit(1);
-    }
+    pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
+                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+                          FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
 
     /* Interrupt line of NIC is connected to GPIO line 36 */
     smc91c111_init(&nd_table[0], 0x04000300,
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
     }
 
     /* Micron RC28F256P30TFA */
-    if (!pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
-                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                               FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
-        error_report("Error registering flash memory");
-        exit(1);
-    }
+    pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
+                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+                          FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
 
     /* Interrupt line of NIC is connected to GPIO line 99 */
     smc91c111_init(&nd_table[0], 0x04000300,
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
     /* There are two 32MiB flash devices on the board */
     for (i = 0; i < 2; i ++) {
         dinfo = drive_get(IF_PFLASH, 0, i);
-        if (!pflash_cfi01_register(mainstone_flash_base[i],
-                                   i ? "mainstone.flash1" : "mainstone.flash0",
-                                   MAINSTONE_FLASH_SIZE,
-                                   dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                                   FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
-            error_report("Error registering flash memory");
-            exit(1);
-        }
+        pflash_cfi01_register(mainstone_flash_base[i],
+                              i ? "mainstone.flash1" : "mainstone.flash0",
+                              MAINSTONE_FLASH_SIZE,
+                              dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+                              FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
     }
 
     mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
 
     fl_idx = 0;
     if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
-        if (!pflash_cfi01_register(OMAP_CS0_BASE,
-                                   "omap_sx1.flash0-1", flash_size,
-                                   blk_by_legacy_dinfo(dinfo),
-                                   SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
-            fprintf(stderr, "qemu: Error registering flash memory %d.\n",
-                           fl_idx);
-        }
+        pflash_cfi01_register(OMAP_CS0_BASE,
+                              "omap_sx1.flash0-1", flash_size,
+                              blk_by_legacy_dinfo(dinfo),
+                              SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
         fl_idx++;
     }
 
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
         memory_region_add_subregion(address_space,
                                 OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
 
-        if (!pflash_cfi01_register(OMAP_CS1_BASE,
-                                   "omap_sx1.flash1-1", FLASH1_SIZE,
-                                   blk_by_legacy_dinfo(dinfo),
-                                   SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
-            fprintf(stderr, "qemu: Error registering flash memory %d.\n",
-                           fl_idx);
-        }
+        pflash_cfi01_register(OMAP_CS1_BASE,
+                              "omap_sx1.flash1-1", FLASH1_SIZE,
+                              blk_by_legacy_dinfo(dinfo),
+                              SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
         fl_idx++;
     } else {
         memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id)
     /* 0x34000000 NOR Flash */
 
     dinfo = drive_get(IF_PFLASH, 0, 0);
-    if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
+    pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
                           VERSATILE_FLASH_SIZE,
                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                           VERSATILE_FLASH_SECT_SIZE,
-                          4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
-        fprintf(stderr, "qemu: Error registering flash memory.\n");
-    }
+                          4, 0x0089, 0x0018, 0x0000, 0x0, 0);
 
     versatile_binfo.ram_size = machine->ram_size;
     versatile_binfo.board_id = board_id;
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
     mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type);
 
     dinfo = drive_get(IF_PFLASH, 0, 0);
-    if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
-                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
-                               FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
-        error_report("Error registering flash memory");
-        exit(1);
-    }
+    pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
+                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
+                          FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
 
     /* setup keypad */
     pxa27x_register_keypad(mpu->kp, map, 0x100);
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

To avoid forward-declaring PXA2xxI2CState, declare
PXA2XX_I2C before its use in pxa2xx_i2c_init() prototype.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/pxa.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/pxa.h
+++ b/include/hw/arm/pxa.h
@@ -XXX,XX +XXX,XX @@ void pxa27x_register_keypad(PXA2xxKeyPadState *kp,
                             const struct keymap *map, int size);
 
 /* pxa2xx.c */
-typedef struct PXA2xxI2CState PXA2xxI2CState;
+#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
+
 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
                 qemu_irq irq, uint32_t page_size);
 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
 
-#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
 typedef struct PXA2xxI2SState PXA2xxI2SState;
-OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
 
 #define TYPE_PXA2XX_FIR "pxa2xx-fir"
 OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState, PXA2XX_FIR)
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/omap1.c            | 115 ++++++++++++++++++--------------------
 hw/arm/omap2.c            |  40 ++++++-------
 hw/arm/omap_sx1.c         |   2 +-
 hw/arm/palm.c             |   2 +-
 hw/char/omap_uart.c       |   7 +--
 hw/display/omap_dss.c     |  15 +++--
 hw/display/omap_lcdc.c    |   9 ++-
 hw/dma/omap_dma.c         |  15 +++--
 hw/gpio/omap_gpio.c       |  15 +++--
 hw/intc/omap_intc.c       |  12 ++--
 hw/misc/omap_gpmc.c       |  12 ++--
 hw/misc/omap_l4.c         |   7 +--
 hw/misc/omap_sdrc.c       |   7 +--
 hw/misc/omap_tap.c        |   5 +-
 hw/sd/omap_mmc.c          |   9 ++-
 hw/ssi/omap_spi.c         |   7 +--
 hw/timer/omap_gptimer.c   |  22 ++++----
 hw/timer/omap_synctimer.c |   4 +-
 18 files changed, 142 insertions(+), 163 deletions(-)

diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -XXX,XX +XXX,XX @@ static void omap_timer_fire(void *opaque)
 
 static void omap_timer_tick(void *opaque)
 {
-    struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
+    struct omap_mpu_timer_s *timer = opaque;
 
     omap_timer_sync(timer);
     omap_timer_fire(timer);
@@ -XXX,XX +XXX,XX @@ static void omap_timer_tick(void *opaque)
 
 static void omap_timer_clk_update(void *opaque, int line, int on)
 {
-    struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
+    struct omap_mpu_timer_s *timer = opaque;
 
     omap_timer_sync(timer);
     timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
@@ -XXX,XX +XXX,XX @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
 static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
                                     unsigned size)
 {
-    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
+    struct omap_mpu_timer_s *s = opaque;
 
     if (size != 4) {
         return omap_badwidth_read32(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
 static void omap_mpu_timer_write(void *opaque, hwaddr addr,
                                  uint64_t value, unsigned size)
 {
-    struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
+    struct omap_mpu_timer_s *s = opaque;
 
     if (size != 4) {
         omap_badwidth_write32(opaque, addr, value);
@@ -XXX,XX +XXX,XX @@ struct omap_watchdog_timer_s {
 static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
                                    unsigned size)
 {
-    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
+    struct omap_watchdog_timer_s *s = opaque;
 
     if (size != 2) {
         return omap_badwidth_read16(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
 static void omap_wd_timer_write(void *opaque, hwaddr addr,
                                 uint64_t value, unsigned size)
 {
-    struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
+    struct omap_watchdog_timer_s *s = opaque;
 
     if (size != 2) {
         omap_badwidth_write16(opaque, addr, value);
@@ -XXX,XX +XXX,XX @@ struct omap_32khz_timer_s {
 static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
                                    unsigned size)
 {
-    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
+    struct omap_32khz_timer_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 4) {
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
 static void omap_os_timer_write(void *opaque, hwaddr addr,
                                 uint64_t value, unsigned size)
 {
-    struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
+    struct omap_32khz_timer_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 4) {
@@ -XXX,XX +XXX,XX @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
 static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
                                   unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
     uint16_t ret;
 
     if (size != 2) {
@@ -XXX,XX +XXX,XX @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
 static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
                                uint64_t value, unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
     int64_t now, ticks;
     int div, mult;
     static const int bypass_div[4] = { 1, 2, 4, 4 };
@@ -XXX,XX +XXX,XX @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory,
 static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
                                   unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
 
     if (size != 4) {
         return omap_badwidth_read32(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
 static void omap_pin_cfg_write(void *opaque, hwaddr addr,
                                uint64_t value, unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
     uint32_t diff;
 
     if (size != 4) {
@@ -XXX,XX +XXX,XX @@ static void omap_pin_cfg_init(MemoryRegion *system_memory,
 static uint64_t omap_id_read(void *opaque, hwaddr addr,
                              unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
 
     if (size != 4) {
         return omap_badwidth_read32(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
 static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
 
     if (size != 4) {
         return omap_badwidth_read32(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
 static void omap_mpui_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
 
     if (size != 4) {
         omap_badwidth_write32(opaque, addr, value);
@@ -XXX,XX +XXX,XX @@ struct omap_tipb_bridge_s {
 static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
                                       unsigned size)
 {
-    struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
+    struct omap_tipb_bridge_s *s = opaque;
 
     if (size < 2) {
         return omap_badwidth_read16(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
 static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
                                    uint64_t value, unsigned size)
 {
-    struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
+    struct omap_tipb_bridge_s *s = opaque;
 
     if (size < 2) {
         omap_badwidth_write16(opaque, addr, value);
@@ -XXX,XX +XXX,XX @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
 static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
     uint32_t ret;
 
     if (size != 4) {
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
 static void omap_tcmi_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
 
     if (size != 4) {
         omap_badwidth_write32(opaque, addr, value);
@@ -XXX,XX +XXX,XX @@ struct dpll_ctl_s {
 static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
+    struct dpll_ctl_s *s = opaque;
 
     if (size != 2) {
         return omap_badwidth_read16(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
 static void omap_dpll_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
+    struct dpll_ctl_s *s = opaque;
     uint16_t diff;
     static const int bypass_div[4] = { 1, 2, 4, 4 };
     int div, mult;
@@ -XXX,XX +XXX,XX @@ static struct dpll_ctl_s  *omap_dpll_init(MemoryRegion *memory,
 static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
 
     if (size != 2) {
         return omap_badwidth_read16(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
 static void omap_clkm_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
     uint16_t diff;
     omap_clk clk;
     static const char *clkschemename[8] = {
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_clkm_ops = {
 static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
                                  unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
     CPUState *cpu = CPU(s->cpu);
 
     if (size != 2) {
@@ -XXX,XX +XXX,XX @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
 static void omap_clkdsp_write(void *opaque, hwaddr addr,
                               uint64_t value, unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
     uint16_t diff;
 
     if (size != 2) {
@@ -XXX,XX +XXX,XX @@ struct omap_mpuio_s {
 
 static void omap_mpuio_set(void *opaque, int line, int level)
 {
-    struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
+    struct omap_mpuio_s *s = opaque;
     uint16_t prev = s->inputs;
 
     if (level)
@@ -XXX,XX +XXX,XX @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
 static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
                                 unsigned size)
 {
-    struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
+    struct omap_mpuio_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
     uint16_t ret;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
 static void omap_mpuio_write(void *opaque, hwaddr addr,
                              uint64_t value, unsigned size)
 {
-    struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
+    struct omap_mpuio_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
     uint16_t diff;
     int ln;
@@ -XXX,XX +XXX,XX @@ static void omap_mpuio_reset(struct omap_mpuio_s *s)
 
 static void omap_mpuio_onoff(void *opaque, int line, int on)
 {
-    struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
+    struct omap_mpuio_s *s = opaque;
 
     s->clk = on;
     if (on)
@@ -XXX,XX +XXX,XX @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
     }
 }
 
-static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
-                                unsigned size)
+static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
+    struct omap_uwire_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 2) {
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
 static void omap_uwire_write(void *opaque, hwaddr addr,
                              uint64_t value, unsigned size)
 {
-    struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
+    struct omap_uwire_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 2) {
@@ -XXX,XX +XXX,XX @@ static void omap_pwl_update(struct omap_pwl_s *s)
     }
 }
 
-static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
-                              unsigned size)
+static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
+    struct omap_pwl_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 1) {
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
 static void omap_pwl_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
 {
-    struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
+    struct omap_pwl_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 1) {
@@ -XXX,XX +XXX,XX @@ static void omap_pwl_reset(struct omap_pwl_s *s)
 
 static void omap_pwl_clk_update(void *opaque, int line, int on)
 {
-    struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
+    struct omap_pwl_s *s = opaque;
 
     s->clk = on;
     omap_pwl_update(s);
@@ -XXX,XX +XXX,XX @@ struct omap_pwt_s {
     omap_clk clk;
 };
 
-static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
-                              unsigned size)
+static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
+    struct omap_pwt_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 1) {
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
 static void omap_pwt_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
 {
-    struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
+    struct omap_pwt_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 1) {
@@ -XXX,XX +XXX,XX @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s)
         printf("%s: conversion failed\n", __func__);
 }
 
-static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
-                              unsigned size)
+static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
+    struct omap_rtc_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
     uint8_t i;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
 static void omap_rtc_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
 {
-    struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
+    struct omap_rtc_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
     struct tm new_tm;
     time_t ti[2];
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
 
 static void omap_mcbsp_source_tick(void *opaque)
 {
-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+    struct omap_mcbsp_s *s = opaque;
     static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
 
     if (!s->rx_rate)
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
 
 static void omap_mcbsp_sink_tick(void *opaque)
 {
-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+    struct omap_mcbsp_s *s = opaque;
     static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
 
     if (!s->tx_rate)
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
 static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
                                 unsigned size)
 {
-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+    struct omap_mcbsp_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
     uint16_t ret;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
 static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
                 uint32_t value)
 {
-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+    struct omap_mcbsp_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     switch (offset) {
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
 static void omap_mcbsp_writew(void *opaque, hwaddr addr,
                 uint32_t value)
 {
-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+    struct omap_mcbsp_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (offset == 0x04) {				/* DXR */
@@ -XXX,XX +XXX,XX @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
 
 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
 {
-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+    struct omap_mcbsp_s *s = opaque;
 
     if (s->rx_rate) {
         s->rx_req = s->codec->in.len;
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
 
 static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
 {
-    struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
+    struct omap_mcbsp_s *s = opaque;
 
     if (s->tx_rate) {
         s->tx_req = s->codec->out.size;
@@ -XXX,XX +XXX,XX @@ static void omap_lpg_reset(struct omap_lpg_s *s)
     omap_lpg_update(s);
 }
 
-static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
-                              unsigned size)
+static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
+    struct omap_lpg_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 1) {
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
 static void omap_lpg_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
 {
-    struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
+    struct omap_lpg_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 1) {
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_lpg_ops = {
 
 static void omap_lpg_clk_update(void *opaque, int line, int on)
 {
-    struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
+    struct omap_lpg_s *s = opaque;
 
     s->clk = on;
     omap_lpg_update(s);
@@ -XXX,XX +XXX,XX @@ static void omap_setup_mpui_io(MemoryRegion *system_memory,
 /* General chip reset */
 static void omap1_mpu_reset(void *opaque)
 {
-    struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *mpu = opaque;
 
     omap_dma_reset(mpu->dma);
     omap_mpu_timer_reset(mpu->timer[0]);
@@ -XXX,XX +XXX,XX @@ static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
 
 void omap_mpu_wakeup(void *opaque, int irq, int req)
 {
-    struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *mpu = opaque;
     CPUState *cpu = CPU(mpu->cpu);
 
     if (cpu->halted) {
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -XXX,XX +XXX,XX @@ static inline void omap_eac_out_empty(struct omap_eac_s *s)
 
 static void omap_eac_in_cb(void *opaque, int avail_b)
 {
-    struct omap_eac_s *s = (struct omap_eac_s *) opaque;
+    struct omap_eac_s *s = opaque;
 
     s->codec.rxavail = avail_b >> 2;
     omap_eac_in_refill(s);
@@ -XXX,XX +XXX,XX @@ static void omap_eac_in_cb(void *opaque, int avail_b)
 
 static void omap_eac_out_cb(void *opaque, int free_b)
 {
-    struct omap_eac_s *s = (struct omap_eac_s *) opaque;
+    struct omap_eac_s *s = opaque;
 
     s->codec.txavail = free_b >> 2;
     if (s->codec.txlen)
@@ -XXX,XX +XXX,XX @@ static void omap_eac_reset(struct omap_eac_s *s)
     omap_eac_interrupt_update(s);
 }
 
-static uint64_t omap_eac_read(void *opaque, hwaddr addr,
-                              unsigned size)
+static uint64_t omap_eac_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_eac_s *s = (struct omap_eac_s *) opaque;
+    struct omap_eac_s *s = opaque;
     uint32_t ret;
 
     if (size != 2) {
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_eac_read(void *opaque, hwaddr addr,
 static void omap_eac_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
 {
-    struct omap_eac_s *s = (struct omap_eac_s *) opaque;
+    struct omap_eac_s *s = opaque;
 
     if (size != 2) {
         omap_badwidth_write16(opaque, addr, value);
@@ -XXX,XX +XXX,XX @@ static void omap_sti_reset(struct omap_sti_s *s)
 static uint64_t omap_sti_read(void *opaque, hwaddr addr,
                               unsigned size)
 {
-    struct omap_sti_s *s = (struct omap_sti_s *) opaque;
+    struct omap_sti_s *s = opaque;
 
     if (size != 4) {
         return omap_badwidth_read32(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sti_read(void *opaque, hwaddr addr,
 static void omap_sti_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
 {
-    struct omap_sti_s *s = (struct omap_sti_s *) opaque;
+    struct omap_sti_s *s = opaque;
 
     if (size != 4) {
         omap_badwidth_write32(opaque, addr, value);
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_sti_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
-                                   unsigned size)
+static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, unsigned size)
 {
     OMAP_BAD_REG(addr);
     return 0;
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
 static void omap_sti_fifo_write(void *opaque, hwaddr addr,
                                 uint64_t value, unsigned size)
 {
-    struct omap_sti_s *s = (struct omap_sti_s *) opaque;
+    struct omap_sti_s *s = opaque;
     int ch = addr >> 6;
     uint8_t byte = value;
 
@@ -XXX,XX +XXX,XX @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
 static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
+    struct omap_prcm_s *s = opaque;
     uint32_t ret;
 
     if (size != 4) {
@@ -XXX,XX +XXX,XX @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
 static void omap_prcm_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
+    struct omap_prcm_s *s = opaque;
 
     if (size != 4) {
         omap_badwidth_write32(opaque, addr, value);
@@ -XXX,XX +XXX,XX @@ struct omap_sysctl_s {
 static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
 {
 
-    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
+    struct omap_sysctl_s *s = opaque;
     int pad_offset, byte_offset;
     int value;
 
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
 
 static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
 {
-    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
+    struct omap_sysctl_s *s = opaque;
 
     switch (addr) {
     case 0x000:	/* CONTROL_REVISION */
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
     return 0;
 }
 
-static void omap_sysctl_write8(void *opaque, hwaddr addr,
-                uint32_t value)
+static void omap_sysctl_write8(void *opaque, hwaddr addr, uint32_t value)
 {
-    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
+    struct omap_sysctl_s *s = opaque;
     int pad_offset, byte_offset;
     int prev_value;
 
@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write8(void *opaque, hwaddr addr,
     }
 }
 
-static void omap_sysctl_write(void *opaque, hwaddr addr,
-                uint32_t value)
+static void omap_sysctl_write(void *opaque, hwaddr addr, uint32_t value)
 {
-    struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
+    struct omap_sysctl_s *s = opaque;
 
     switch (addr) {
     case 0x000:	/* CONTROL_REVISION */
@@ -XXX,XX +XXX,XX @@ static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
 /* General chip reset */
 static void omap2_mpu_reset(void *opaque)
 {
-    struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *mpu = opaque;
 
     omap_dma_reset(mpu->dma);
     omap_prcm_reset(mpu->prcm);
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -XXX,XX +XXX,XX @@
 static uint64_t static_read(void *opaque, hwaddr offset,
                             unsigned size)
 {
-    uint32_t *val = (uint32_t *) opaque;
+    uint32_t *val = opaque;
     uint32_t mask = (4 / size) - 1;
 
     return *val >> ((offset & mask) << 3);
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -XXX,XX +XXX,XX @@ static struct {
 
 static void palmte_button_event(void *opaque, int keycode)
 {
-    struct omap_mpu_state_s *cpu = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *cpu = opaque;
 
     if (palmte_keymap[keycode & 0x7f].row != -1)
         omap_mpuio_key(cpu->mpuio,
diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/omap_uart.c
+++ b/hw/char/omap_uart.c
@@ -XXX,XX +XXX,XX @@ struct omap_uart_s *omap_uart_init(hwaddr base,
     return s;
 }
 
-static uint64_t omap_uart_read(void *opaque, hwaddr addr,
-                               unsigned size)
+static uint64_t omap_uart_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_uart_s *s = (struct omap_uart_s *) opaque;
+    struct omap_uart_s *s = opaque;
 
     if (size == 4) {
         return omap_badwidth_read8(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_uart_read(void *opaque, hwaddr addr,
 static void omap_uart_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_uart_s *s = (struct omap_uart_s *) opaque;
+    struct omap_uart_s *s = opaque;
 
     if (size == 4) {
         omap_badwidth_write8(opaque, addr, value);
diff --git a/hw/display/omap_dss.c b/hw/display/omap_dss.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/omap_dss.c
+++ b/hw/display/omap_dss.c
@@ -XXX,XX +XXX,XX @@ void omap_dss_reset(struct omap_dss_s *s)
 static uint64_t omap_diss_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
+    struct omap_dss_s *s = opaque;
 
     if (size != 4) {
         return omap_badwidth_read32(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_diss_read(void *opaque, hwaddr addr,
 static void omap_diss_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
+    struct omap_dss_s *s = opaque;
 
     if (size != 4) {
         omap_badwidth_write32(opaque, addr, value);
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_diss_ops = {
 static uint64_t omap_disc_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
+    struct omap_dss_s *s = opaque;
 
     if (size != 4) {
         return omap_badwidth_read32(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_disc_read(void *opaque, hwaddr addr,
 static void omap_disc_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
+    struct omap_dss_s *s = opaque;
 
     if (size != 4) {
         omap_badwidth_write32(opaque, addr, value);
@@ -XXX,XX +XXX,XX @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
     omap_dispc_interrupt_update(s);
 }
 
-static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
-                               unsigned size)
+static uint64_t omap_rfbi_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
+    struct omap_dss_s *s = opaque;
 
     if (size != 4) {
         return omap_badwidth_read32(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
 static void omap_rfbi_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_dss_s *s = (struct omap_dss_s *) opaque;
+    struct omap_dss_s *s = opaque;
 
     if (size != 4) {
         omap_badwidth_write32(opaque, addr, value);
diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/omap_lcdc.c
+++ b/hw/display/omap_lcdc.c
@@ -XXX,XX +XXX,XX @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s,
 
 static void omap_update_display(void *opaque)
 {
-    struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
+    struct omap_lcd_panel_s *omap_lcd = opaque;
     DisplaySurface *surface;
     drawfn draw_line;
     int size, height, first, last;
@@ -XXX,XX +XXX,XX @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
     }
 }
 
-static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
-                               unsigned size)
+static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
+    struct omap_lcd_panel_s *s = opaque;
 
     switch (addr) {
     case 0x00:	/* LCD_CONTROL */
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
 static void omap_lcdc_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
+    struct omap_lcd_panel_s *s = opaque;
 
     switch (addr) {
     case 0x00:	/* LCD_CONTROL */
diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/omap_dma.c
+++ b/hw/dma/omap_dma.c
@@ -XXX,XX +XXX,XX @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
     return 0;
 }
 
-static uint64_t omap_dma_read(void *opaque, hwaddr addr,
-                              unsigned size)
+static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
+    struct omap_dma_s *s = opaque;
     int reg, ch;
     uint16_t ret;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr,
 static void omap_dma_write(void *opaque, hwaddr addr,
                            uint64_t value, unsigned size)
 {
-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
+    struct omap_dma_s *s = opaque;
     int reg, ch;
 
     if (size != 2) {
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_dma_ops = {
 
 static void omap_dma_request(void *opaque, int drq, int req)
 {
-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
+    struct omap_dma_s *s = opaque;
     /* The request pins are level triggered in QEMU.  */
     if (req) {
         if (~s->dma->drqbmp & (1ULL << drq)) {
@@ -XXX,XX +XXX,XX @@ static void omap_dma_request(void *opaque, int drq, int req)
 /* XXX: this won't be needed once soc_dma knows about clocks.  */
 static void omap_dma_clk_update(void *opaque, int line, int on)
 {
-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
+    struct omap_dma_s *s = opaque;
     int i;
 
     s->dma->freq = omap_clk_getrate(s->clk);
@@ -XXX,XX +XXX,XX @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
 static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
+    struct omap_dma_s *s = opaque;
     int irqn = 0, chnum;
     struct omap_dma_channel_s *ch;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
 static void omap_dma4_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_dma_s *s = (struct omap_dma_s *) opaque;
+    struct omap_dma_s *s = opaque;
     int chnum, irqn = 0;
     struct omap_dma_channel_s *ch;
 
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/omap_gpio.c
+++ b/hw/gpio/omap_gpio.c
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_set(void *opaque, int line, int level)
 static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
+    struct omap_gpio_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
 
     if (size != 2) {
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
 static void omap_gpio_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
+    struct omap_gpio_s *s = opaque;
     int offset = addr & OMAP_MPUI_REG_MASK;
     uint16_t diff;
     int ln;
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
 
 static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
 {
-    struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
+    struct omap2_gpio_s *s = opaque;
 
     switch (addr) {
     case 0x00:	/* GPIO_REVISION */
@@ -XXX,XX +XXX,XX @@ static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
 static void omap2_gpio_module_write(void *opaque, hwaddr addr,
                 uint32_t value)
 {
-    struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
+    struct omap2_gpio_s *s = opaque;
     uint32_t diff;
     int ln;
 
@@ -XXX,XX +XXX,XX @@ static void omap2_gpif_reset(DeviceState *dev)
     s->gpo = 0;
 }
 
-static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
-                                    unsigned size)
+static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
+    struct omap2_gpif_s *s = opaque;
 
     switch (addr) {
     case 0x00:	/* IPGENERICOCPSPL_REVISION */
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
 static void omap2_gpif_top_write(void *opaque, hwaddr addr,
                                  uint64_t value, unsigned size)
 {
-    struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
+    struct omap2_gpif_s *s = opaque;
 
     switch (addr) {
     case 0x00:	/* IPGENERICOCPSPL_REVISION */
diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/omap_intc.c
+++ b/hw/intc/omap_intc.c
@@ -XXX,XX +XXX,XX @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
 
 static void omap_set_intr(void *opaque, int irq, int req)
 {
-    struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
+    struct omap_intr_handler_s *ih = opaque;
     uint32_t rise;
 
     struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr(void *opaque, int irq, int req)
 /* Simplified version with no edge detection */
 static void omap_set_intr_noedge(void *opaque, int irq, int req)
 {
-    struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
+    struct omap_intr_handler_s *ih = opaque;
     uint32_t rise;
 
     struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
 static uint64_t omap_inth_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
+    struct omap_intr_handler_s *s = opaque;
     int i, offset = addr;
     int bank_no = offset >> 8;
     int line_no;
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
 static void omap_inth_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
+    struct omap_intr_handler_s *s = opaque;
     int i, offset = addr;
     int bank_no = offset >> 8;
     struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_intc_info = {
 static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
                                 unsigned size)
 {
-    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
+    struct omap_intr_handler_s *s = opaque;
     int offset = addr;
     int bank_no, line_no;
     struct omap_intr_handler_bank_s *bank = NULL;
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
 static void omap2_inth_write(void *opaque, hwaddr addr,
                              uint64_t value, unsigned size)
 {
-    struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
+    struct omap_intr_handler_s *s = opaque;
     int offset = addr;
     int bank_no, line_no;
     struct omap_intr_handler_bank_s *bank = NULL;
diff --git a/hw/misc/omap_gpmc.c b/hw/misc/omap_gpmc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/omap_gpmc.c
+++ b/hw/misc/omap_gpmc.c
@@ -XXX,XX +XXX,XX @@ static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int value)
 static uint64_t omap_nand_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
+    struct omap_gpmc_cs_file_s *f = opaque;
     uint64_t v;
     nand_setpins(f->dev, 0, 0, 0, 1, 0);
     switch (omap_gpmc_devsize(f)) {
@@ -XXX,XX +XXX,XX @@ static void omap_nand_setio(DeviceState *dev, uint64_t value,
 static void omap_nand_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
+    struct omap_gpmc_cs_file_s *f = opaque;
     nand_setpins(f->dev, 0, 0, 0, 1, 0);
     omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
 }
@@ -XXX,XX +XXX,XX @@ static void fill_prefetch_fifo(struct omap_gpmc_s *s)
 static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
                                         unsigned size)
 {
-    struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
+    struct omap_gpmc_s *s = opaque;
     uint32_t data;
     if (s->prefetch.config1 & 1) {
         /* The TRM doesn't define the behaviour if you read from the
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
 static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr,
                                      uint64_t value, unsigned size)
 {
-    struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
+    struct omap_gpmc_s *s = opaque;
     int cs = prefetch_cs(s->prefetch.config1);
     if ((s->prefetch.config1 & 1) == 0) {
         /* The TRM doesn't define the behaviour of writing to the
@@ -XXX,XX +XXX,XX @@ static int gpmc_wordaccess_only(hwaddr addr)
 static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
+    struct omap_gpmc_s *s = opaque;
     int cs;
     struct omap_gpmc_cs_file_s *f;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
 static void omap_gpmc_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
+    struct omap_gpmc_s *s = opaque;
     int cs;
     struct omap_gpmc_cs_file_s *f;
 
diff --git a/hw/misc/omap_l4.c b/hw/misc/omap_l4.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/omap_l4.c
+++ b/hw/misc/omap_l4.c
@@ -XXX,XX +XXX,XX @@ hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
     return ta->start[region].size;
 }
 
-static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
-                               unsigned size)
+static uint64_t omap_l4ta_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
+    struct omap_target_agent_s *s = opaque;
 
     if (size != 2) {
         return omap_badwidth_read16(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
 static void omap_l4ta_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
+    struct omap_target_agent_s *s = opaque;
 
     if (size != 4) {
         omap_badwidth_write32(opaque, addr, value);
diff --git a/hw/misc/omap_sdrc.c b/hw/misc/omap_sdrc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/omap_sdrc.c
+++ b/hw/misc/omap_sdrc.c
@@ -XXX,XX +XXX,XX @@ void omap_sdrc_reset(struct omap_sdrc_s *s)
     s->config = 0x10;
 }
 
-static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
-                               unsigned size)
+static uint64_t omap_sdrc_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
+    struct omap_sdrc_s *s = opaque;
 
     if (size != 4) {
         return omap_badwidth_read32(opaque, addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
 static void omap_sdrc_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
+    struct omap_sdrc_s *s = opaque;
 
     if (size != 4) {
         omap_badwidth_write32(opaque, addr, value);
diff --git a/hw/misc/omap_tap.c b/hw/misc/omap_tap.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/omap_tap.c
+++ b/hw/misc/omap_tap.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/omap.h"
 
 /* TEST-Chip-level TAP */
-static uint64_t omap_tap_read(void *opaque, hwaddr addr,
-                              unsigned size)
+static uint64_t omap_tap_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+    struct omap_mpu_state_s *s = opaque;
 
     if (size != 4) {
         return omap_badwidth_read32(opaque, addr);
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/omap_mmc.c
+++ b/hw/sd/omap_mmc.c
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
     device_cold_reset(DEVICE(host->card));
 }
 
-static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
-                              unsigned size)
+static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size)
 {
     uint16_t i;
-    struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
+    struct omap_mmc_s *s = opaque;
 
     if (size != 2) {
         return omap_badwidth_read16(opaque, offset);
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_write(void *opaque, hwaddr offset,
                            uint64_t value, unsigned size)
 {
     int i;
-    struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
+    struct omap_mmc_s *s = opaque;
 
     if (size != 2) {
         omap_badwidth_write16(opaque, offset, value);
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_mmc_ops = {
 
 static void omap_mmc_cover_cb(void *opaque, int line, int level)
 {
-    struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
+    struct omap_mmc_s *host = opaque;
 
     if (!host->cdet_state && level) {
         host->status |= 0x0002;
diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/omap_spi.c
+++ b/hw/ssi/omap_spi.c
@@ -XXX,XX +XXX,XX @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
     omap_mcspi_interrupt_update(s);
 }
 
-static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
-                                unsigned size)
+static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
+    struct omap_mcspi_s *s = opaque;
     int ch = 0;
     uint32_t ret;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
 static void omap_mcspi_write(void *opaque, hwaddr addr,
                              uint64_t value, unsigned size)
 {
-    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
+    struct omap_mcspi_s *s = opaque;
     int ch = 0;
 
     if (size != 4) {
diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/omap_gptimer.c
+++ b/hw/timer/omap_gptimer.c
@@ -XXX,XX +XXX,XX @@ static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
 
 static void omap_gp_timer_tick(void *opaque)
 {
-    struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
+    struct omap_gp_timer_s *timer = opaque;
 
     if (!timer->ar) {
         timer->st = 0;
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_tick(void *opaque)
 
 static void omap_gp_timer_match(void *opaque)
 {
-    struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
+    struct omap_gp_timer_s *timer = opaque;
 
     if (timer->trigger == gpt_trigger_both)
         omap_gp_timer_trigger(timer);
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_match(void *opaque)
 
 static void omap_gp_timer_input(void *opaque, int line, int on)
 {
-    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
+    struct omap_gp_timer_s *s = opaque;
     int trigger;
 
     switch (s->capture) {
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_input(void *opaque, int line, int on)
 
 static void omap_gp_timer_clk_update(void *opaque, int line, int on)
 {
-    struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
+    struct omap_gp_timer_s *timer = opaque;
 
     omap_gp_timer_sync(timer);
     timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
@@ -XXX,XX +XXX,XX @@ void omap_gp_timer_reset(struct omap_gp_timer_s *s)
 
 static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
 {
-    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
+    struct omap_gp_timer_s *s = opaque;
 
     switch (addr) {
     case 0x00:	/* TIDR */
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
 
 static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
 {
-    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
+    struct omap_gp_timer_s *s = opaque;
     uint32_t ret;
 
     if (addr & 2)
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
     }
 }
 
-static void omap_gp_timer_write(void *opaque, hwaddr addr,
-                uint32_t value)
+static void omap_gp_timer_write(void *opaque, hwaddr addr, uint32_t value)
 {
-    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
+    struct omap_gp_timer_s *s = opaque;
 
     switch (addr) {
     case 0x00:	/* TIDR */
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_write(void *opaque, hwaddr addr,
     }
 }
 
-static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
-                uint32_t value)
+static void omap_gp_timer_writeh(void *opaque, hwaddr addr, uint32_t value)
 {
-    struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
+    struct omap_gp_timer_s *s = opaque;
 
     if (addr & 2)
         omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/omap_synctimer.c
+++ b/hw/timer/omap_synctimer.c
@@ -XXX,XX +XXX,XX @@ void omap_synctimer_reset(struct omap_synctimer_s *s)
 
 static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
 {
-    struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
+    struct omap_synctimer_s *s = opaque;
 
     switch (addr) {
     case 0x00:	/* 32KSYNCNT_REV */
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
 
 static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
 {
-    struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
+    struct omap_synctimer_s *s = opaque;
     uint32_t ret;
 
     if (addr & 2)
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Following docs/devel/style.rst guidelines, rename omap_gpif_s ->
Omap1GpioState. This also remove a use of 'struct' in the
DECLARE_INSTANCE_CHECKER() macro call.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/omap.h |  6 +++---
 hw/gpio/omap_gpio.c   | 16 ++++++++--------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/omap.h
+++ b/include/hw/arm/omap.h
@@ -XXX,XX +XXX,XX @@ void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk);
 
 /* omap_gpio.c */
 #define TYPE_OMAP1_GPIO "omap-gpio"
-DECLARE_INSTANCE_CHECKER(struct omap_gpif_s, OMAP1_GPIO,
+typedef struct Omap1GpioState Omap1GpioState;
+DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO,
                          TYPE_OMAP1_GPIO)
 
 #define TYPE_OMAP2_GPIO "omap2-gpio"
 DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
                          TYPE_OMAP2_GPIO)
 
-typedef struct omap_gpif_s omap_gpif;
 typedef struct omap2_gpif_s omap2_gpif;
 
 /* TODO: clock framework (see above) */
-void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk);
+void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
 
 void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
 void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/omap_gpio.c
+++ b/hw/gpio/omap_gpio.c
@@ -XXX,XX +XXX,XX @@ struct omap_gpio_s {
     uint16_t pins;
 };
 
-struct omap_gpif_s {
+struct Omap1GpioState {
     SysBusDevice parent_obj;
 
     MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ struct omap_gpif_s {
 /* General-Purpose I/O of OMAP1 */
 static void omap_gpio_set(void *opaque, int line, int level)
 {
-    struct omap_gpif_s *p = opaque;
+    Omap1GpioState *p = opaque;
     struct omap_gpio_s *s = &p->omap1;
     uint16_t prev = s->inputs;
 
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_gpio_module_ops = {
 
 static void omap_gpif_reset(DeviceState *dev)
 {
-    struct omap_gpif_s *s = OMAP1_GPIO(dev);
+    Omap1GpioState *s = OMAP1_GPIO(dev);
 
     omap_gpio_reset(&s->omap1);
 }
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_gpif_top_ops = {
 static void omap_gpio_init(Object *obj)
 {
     DeviceState *dev = DEVICE(obj);
-    struct omap_gpif_s *s = OMAP1_GPIO(obj);
+    Omap1GpioState *s = OMAP1_GPIO(obj);
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 
     qdev_init_gpio_in(dev, omap_gpio_set, 16);
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_init(Object *obj)
 
 static void omap_gpio_realize(DeviceState *dev, Error **errp)
 {
-    struct omap_gpif_s *s = OMAP1_GPIO(dev);
+    Omap1GpioState *s = OMAP1_GPIO(dev);
 
     if (!s->clk) {
         error_setg(errp, "omap-gpio: clk not connected");
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_realize(DeviceState *dev, Error **errp)
     }
 }
 
-void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk)
+void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk)
 {
     gpio->clk = clk;
 }
 
 static Property omap_gpio_properties[] = {
-    DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
+    DEFINE_PROP_INT32("mpu_model", Omap1GpioState, mpu_model, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_class_init(ObjectClass *klass, void *data)
 static const TypeInfo omap_gpio_info = {
     .name          = TYPE_OMAP1_GPIO,
     .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(struct omap_gpif_s),
+    .instance_size = sizeof(Omap1GpioState),
     .instance_init = omap_gpio_init,
     .class_init    = omap_gpio_class_init,
 };
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Following docs/devel/style.rst guidelines, rename omap2_gpif_s ->
Omap2GpioState. This also remove a use of 'struct' in the
DECLARE_INSTANCE_CHECKER() macro call.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/omap.h |  9 ++++-----
 hw/gpio/omap_gpio.c   | 20 ++++++++++----------
 2 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/omap.h
+++ b/include/hw/arm/omap.h
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO,
                          TYPE_OMAP1_GPIO)
 
 #define TYPE_OMAP2_GPIO "omap2-gpio"
-DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
+typedef struct Omap2GpioState Omap2GpioState;
+DECLARE_INSTANCE_CHECKER(Omap2GpioState, OMAP2_GPIO,
                          TYPE_OMAP2_GPIO)
 
-typedef struct omap2_gpif_s omap2_gpif;
-
 /* TODO: clock framework (see above) */
 void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
 
-void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
-void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
+void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk);
+void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk);
 
 /* OMAP2 l4 Interconnect */
 struct omap_l4_s;
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/omap_gpio.c
+++ b/hw/gpio/omap_gpio.c
@@ -XXX,XX +XXX,XX @@ struct omap2_gpio_s {
     uint8_t delay;
 };
 
-struct omap2_gpif_s {
+struct Omap2GpioState {
     SysBusDevice parent_obj;
 
     MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
 
 static void omap2_gpio_set(void *opaque, int line, int level)
 {
-    struct omap2_gpif_s *p = opaque;
+    Omap2GpioState *p = opaque;
     struct omap2_gpio_s *s = &p->modules[line >> 5];
 
     line &= 31;
@@ -XXX,XX +XXX,XX @@ static void omap_gpif_reset(DeviceState *dev)
 
 static void omap2_gpif_reset(DeviceState *dev)
 {
-    struct omap2_gpif_s *s = OMAP2_GPIO(dev);
+    Omap2GpioState *s = OMAP2_GPIO(dev);
     int i;
 
     for (i = 0; i < s->modulecount; i++) {
@@ -XXX,XX +XXX,XX @@ static void omap2_gpif_reset(DeviceState *dev)
 
 static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
 {
-    struct omap2_gpif_s *s = opaque;
+    Omap2GpioState *s = opaque;
 
     switch (addr) {
     case 0x00:	/* IPGENERICOCPSPL_REVISION */
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
 static void omap2_gpif_top_write(void *opaque, hwaddr addr,
                                  uint64_t value, unsigned size)
 {
-    struct omap2_gpif_s *s = opaque;
+    Omap2GpioState *s = opaque;
 
     switch (addr) {
     case 0x00:	/* IPGENERICOCPSPL_REVISION */
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_realize(DeviceState *dev, Error **errp)
 
 static void omap2_gpio_realize(DeviceState *dev, Error **errp)
 {
-    struct omap2_gpif_s *s = OMAP2_GPIO(dev);
+    Omap2GpioState *s = OMAP2_GPIO(dev);
     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     int i;
 
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_gpio_info = {
     .class_init    = omap_gpio_class_init,
 };
 
-void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk)
+void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk)
 {
     gpio->iclk = clk;
 }
 
-void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk)
+void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk)
 {
     assert(i <= 5);
     gpio->fclk[i] = clk;
 }
 
 static Property omap2_gpio_properties[] = {
-    DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
+    DEFINE_PROP_INT32("mpu_model", Omap2GpioState, mpu_model, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_class_init(ObjectClass *klass, void *data)
 static const TypeInfo omap2_gpio_info = {
     .name          = TYPE_OMAP2_GPIO,
     .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(struct omap2_gpif_s),
+    .instance_size = sizeof(Omap2GpioState),
     .class_init    = omap2_gpio_class_init,
 };
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Following docs/devel/style.rst guidelines, rename
omap_intr_handler_s -> OMAPIntcState. This also remove a
use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/omap.h |  9 ++++-----
 hw/intc/omap_intc.c   | 38 +++++++++++++++++++-------------------
 2 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/omap.h
+++ b/include/hw/arm/omap.h
@@ -XXX,XX +XXX,XX @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
 
 /* omap_intc.c */
 #define TYPE_OMAP_INTC "common-omap-intc"
-typedef struct omap_intr_handler_s omap_intr_handler;
-DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
-                         TYPE_OMAP_INTC)
+typedef struct OMAPIntcState OMAPIntcState;
+DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC)
 
 
 /*
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
  * (ie the struct omap_mpu_state_s*) to do the clockname to pointer
  * translation.)
  */
-void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk);
-void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
+void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk);
+void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk);
 
 /* omap_i2c.c */
 #define TYPE_OMAP_I2C "omap_i2c"
diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/omap_intc.c
+++ b/hw/intc/omap_intc.c
@@ -XXX,XX +XXX,XX @@ struct omap_intr_handler_bank_s {
     unsigned char priority[32];
 };
 
-struct omap_intr_handler_s {
+struct OMAPIntcState {
     SysBusDevice parent_obj;
 
     qemu_irq *pins;
@@ -XXX,XX +XXX,XX @@ struct omap_intr_handler_s {
     struct omap_intr_handler_bank_s bank[3];
 };
 
-static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
+static void omap_inth_sir_update(OMAPIntcState *s, int is_fiq)
 {
     int i, j, sir_intr, p_intr, p;
     uint32_t level;
@@ -XXX,XX +XXX,XX @@ static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
     s->sir_intr[is_fiq] = sir_intr;
 }
 
-static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
+static inline void omap_inth_update(OMAPIntcState *s, int is_fiq)
 {
     int i;
     uint32_t has_intr = 0;
@@ -XXX,XX +XXX,XX @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
 
 static void omap_set_intr(void *opaque, int irq, int req)
 {
-    struct omap_intr_handler_s *ih = opaque;
+    OMAPIntcState *ih = opaque;
     uint32_t rise;
 
     struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr(void *opaque, int irq, int req)
 /* Simplified version with no edge detection */
 static void omap_set_intr_noedge(void *opaque, int irq, int req)
 {
-    struct omap_intr_handler_s *ih = opaque;
+    OMAPIntcState *ih = opaque;
     uint32_t rise;
 
     struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
 static uint64_t omap_inth_read(void *opaque, hwaddr addr,
                                unsigned size)
 {
-    struct omap_intr_handler_s *s = opaque;
+    OMAPIntcState *s = opaque;
     int i, offset = addr;
     int bank_no = offset >> 8;
     int line_no;
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
 static void omap_inth_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
 {
-    struct omap_intr_handler_s *s = opaque;
+    OMAPIntcState *s = opaque;
     int i, offset = addr;
     int bank_no = offset >> 8;
     struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_inth_mem_ops = {
 
 static void omap_inth_reset(DeviceState *dev)
 {
-    struct omap_intr_handler_s *s = OMAP_INTC(dev);
+    OMAPIntcState *s = OMAP_INTC(dev);
     int i;
 
     for (i = 0; i < s->nbanks; ++i){
@@ -XXX,XX +XXX,XX @@ static void omap_inth_reset(DeviceState *dev)
 static void omap_intc_init(Object *obj)
 {
     DeviceState *dev = DEVICE(obj);
-    struct omap_intr_handler_s *s = OMAP_INTC(obj);
+    OMAPIntcState *s = OMAP_INTC(obj);
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 
     s->nbanks = 1;
@@ -XXX,XX +XXX,XX @@ static void omap_intc_init(Object *obj)
 
 static void omap_intc_realize(DeviceState *dev, Error **errp)
 {
-    struct omap_intr_handler_s *s = OMAP_INTC(dev);
+    OMAPIntcState *s = OMAP_INTC(dev);
 
     if (!s->iclk) {
         error_setg(errp, "omap-intc: clk not connected");
     }
 }
 
-void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk)
+void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk)
 {
     intc->iclk = clk;
 }
 
-void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk)
+void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk)
 {
     intc->fclk = clk;
 }
 
 static Property omap_intc_properties[] = {
-    DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
+    DEFINE_PROP_UINT32("size", OMAPIntcState, size, 0x100),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_intc_info = {
 static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
                                 unsigned size)
 {
-    struct omap_intr_handler_s *s = opaque;
+    OMAPIntcState *s = opaque;
     int offset = addr;
     int bank_no, line_no;
     struct omap_intr_handler_bank_s *bank = NULL;
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
 static void omap2_inth_write(void *opaque, hwaddr addr,
                              uint64_t value, unsigned size)
 {
-    struct omap_intr_handler_s *s = opaque;
+    OMAPIntcState *s = opaque;
     int offset = addr;
     int bank_no, line_no;
     struct omap_intr_handler_bank_s *bank = NULL;
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_inth_mem_ops = {
 static void omap2_intc_init(Object *obj)
 {
     DeviceState *dev = DEVICE(obj);
-    struct omap_intr_handler_s *s = OMAP_INTC(obj);
+    OMAPIntcState *s = OMAP_INTC(obj);
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 
     s->level_only = 1;
@@ -XXX,XX +XXX,XX @@ static void omap2_intc_init(Object *obj)
 
 static void omap2_intc_realize(DeviceState *dev, Error **errp)
 {
-    struct omap_intr_handler_s *s = OMAP_INTC(dev);
+    OMAPIntcState *s = OMAP_INTC(dev);
 
     if (!s->iclk) {
         error_setg(errp, "omap2-intc: iclk not connected");
@@ -XXX,XX +XXX,XX @@ static void omap2_intc_realize(DeviceState *dev, Error **errp)
 }
 
 static Property omap2_intc_properties[] = {
-    DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
+    DEFINE_PROP_UINT8("revision", OMAPIntcState,
     revision, 0x21),
     DEFINE_PROP_END_OF_LIST(),
 };
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap2_intc_info = {
 static const TypeInfo omap_intc_type_info = {
     .name          = TYPE_OMAP_INTC,
     .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(omap_intr_handler),
+    .instance_size = sizeof(OMAPIntcState),
     .abstract      = true,
 };
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_update(stellaris_adc_state *s)
 
 static void stellaris_adc_trigger(void *opaque, int irq, int level)
 {
-    stellaris_adc_state *s = (stellaris_adc_state *)opaque;
+    stellaris_adc_state *s = opaque;
     int n;
 
     for (n = 0; n < 4; n++) {
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_reset(stellaris_adc_state *s)
 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
                                    unsigned size)
 {
-    stellaris_adc_state *s = (stellaris_adc_state *)opaque;
+    stellaris_adc_state *s = opaque;
 
     /* TODO: Implement this.  */
     if (offset >= 0x40 && offset < 0xc0) {
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
 static void stellaris_adc_write(void *opaque, hwaddr offset,
                                 uint64_t value, unsigned size)
 {
-    stellaris_adc_state *s = (stellaris_adc_state *)opaque;
+    stellaris_adc_state *s = opaque;
 
     /* TODO: Implement this.  */
     if (offset >= 0x40 && offset < 0xc0) {
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Following docs/devel/style.rst guidelines, rename
stellaris_adc_state -> StellarisADCState. This also remove a
use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 73 +++++++++++++++++++++++-----------------------
 1 file changed, 36 insertions(+), 37 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
 #define STELLARIS_ADC_FIFO_FULL     0x1000
 
 #define TYPE_STELLARIS_ADC "stellaris-adc"
-typedef struct StellarisADCState stellaris_adc_state;
-DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
-                         TYPE_STELLARIS_ADC)
+typedef struct StellarisADCState StellarisADCState;
+DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC)
 
 struct StellarisADCState {
     SysBusDevice parent_obj;
@@ -XXX,XX +XXX,XX @@ struct StellarisADCState {
     qemu_irq irq[4];
 };
 
-static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
+static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n)
 {
     int tail;
 
@@ -XXX,XX +XXX,XX @@ static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
     return s->fifo[n].data[tail];
 }
 
-static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
+static void stellaris_adc_fifo_write(StellarisADCState *s, int n,
                                      uint32_t value)
 {
     int head;
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 }
 
-static void stellaris_adc_update(stellaris_adc_state *s)
+static void stellaris_adc_update(StellarisADCState *s)
 {
     int level;
     int n;
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_update(stellaris_adc_state *s)
 
 static void stellaris_adc_trigger(void *opaque, int irq, int level)
 {
-    stellaris_adc_state *s = opaque;
+    StellarisADCState *s = opaque;
     int n;
 
     for (n = 0; n < 4; n++) {
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
     }
 }
 
-static void stellaris_adc_reset(stellaris_adc_state *s)
+static void stellaris_adc_reset(StellarisADCState *s)
 {
     int n;
 
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_reset(stellaris_adc_state *s)
 static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
                                    unsigned size)
 {
-    stellaris_adc_state *s = opaque;
+    StellarisADCState *s = opaque;
 
     /* TODO: Implement this.  */
     if (offset >= 0x40 && offset < 0xc0) {
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
 static void stellaris_adc_write(void *opaque, hwaddr offset,
                                 uint64_t value, unsigned size)
 {
-    stellaris_adc_state *s = opaque;
+    StellarisADCState *s = opaque;
 
     /* TODO: Implement this.  */
     if (offset >= 0x40 && offset < 0xc0) {
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_adc = {
     .version_id = 1,
     .minimum_version_id = 1,
     .fields = (VMStateField[]) {
-        VMSTATE_UINT32(actss, stellaris_adc_state),
-        VMSTATE_UINT32(ris, stellaris_adc_state),
-        VMSTATE_UINT32(im, stellaris_adc_state),
-        VMSTATE_UINT32(emux, stellaris_adc_state),
-        VMSTATE_UINT32(ostat, stellaris_adc_state),
-        VMSTATE_UINT32(ustat, stellaris_adc_state),
-        VMSTATE_UINT32(sspri, stellaris_adc_state),
-        VMSTATE_UINT32(sac, stellaris_adc_state),
-        VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
-        VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
-        VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
-        VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
-        VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
-        VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
-        VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
-        VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
-        VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
-        VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
-        VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
-        VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
-        VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
-        VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
-        VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
-        VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
-        VMSTATE_UINT32(noise, stellaris_adc_state),
+        VMSTATE_UINT32(actss, StellarisADCState),
+        VMSTATE_UINT32(ris, StellarisADCState),
+        VMSTATE_UINT32(im, StellarisADCState),
+        VMSTATE_UINT32(emux, StellarisADCState),
+        VMSTATE_UINT32(ostat, StellarisADCState),
+        VMSTATE_UINT32(ustat, StellarisADCState),
+        VMSTATE_UINT32(sspri, StellarisADCState),
+        VMSTATE_UINT32(sac, StellarisADCState),
+        VMSTATE_UINT32(fifo[0].state, StellarisADCState),
+        VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16),
+        VMSTATE_UINT32(ssmux[0], StellarisADCState),
+        VMSTATE_UINT32(ssctl[0], StellarisADCState),
+        VMSTATE_UINT32(fifo[1].state, StellarisADCState),
+        VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16),
+        VMSTATE_UINT32(ssmux[1], StellarisADCState),
+        VMSTATE_UINT32(ssctl[1], StellarisADCState),
+        VMSTATE_UINT32(fifo[2].state, StellarisADCState),
+        VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16),
+        VMSTATE_UINT32(ssmux[2], StellarisADCState),
+        VMSTATE_UINT32(ssctl[2], StellarisADCState),
+        VMSTATE_UINT32(fifo[3].state, StellarisADCState),
+        VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16),
+        VMSTATE_UINT32(ssmux[3], StellarisADCState),
+        VMSTATE_UINT32(ssctl[3], StellarisADCState),
+        VMSTATE_UINT32(noise, StellarisADCState),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_adc = {
 static void stellaris_adc_init(Object *obj)
 {
     DeviceState *dev = DEVICE(obj);
-    stellaris_adc_state *s = STELLARIS_ADC(obj);
+    StellarisADCState *s = STELLARIS_ADC(obj);
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
     int n;
 
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_class_init(ObjectClass *klass, void *data)
 static const TypeInfo stellaris_adc_info = {
     .name          = TYPE_STELLARIS_ADC,
     .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(stellaris_adc_state),
+    .instance_size = sizeof(StellarisADCState),
     .instance_init = stellaris_adc_init,
     .class_init    = stellaris_adc_class_init,
 };
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The typedef and definitions are generated by the OBJECT_DECLARE_TYPE
macro in "hw/arm/bcm2836.h":

20    #define TYPE_BCM283X "bcm283x"
 21    OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)

The script ran in commit a489d1951c ("Use OBJECT_DECLARE_TYPE when
possible") missed them because they are declared in a different
file unit. Remove them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-10-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/bcm2836.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/raspi_platform.h"
 #include "hw/sysbus.h"
 
-typedef struct BCM283XClass {
+struct BCM283XClass {
     /*< private >*/
     DeviceClass parent_class;
     /*< public >*/
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XClass {
     hwaddr peri_base; /* Peripheral base address seen by the CPU */
     hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
     int clusterid;
-} BCM283XClass;
-
-#define BCM283X_CLASS(klass) \
-    OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
-#define BCM283X_GET_CLASS(obj) \
-    OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
+};
 
 static Property bcm2836_enabled_cores_property =
     DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

NPCM7XX models have been commited after the conversion from
commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
Manually convert them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/adc/npcm7xx_adc.h   |  7 +++----
 include/hw/arm/npcm7xx.h       | 18 ++++++------------
 include/hw/i2c/npcm7xx_smbus.h |  7 +++----
 include/hw/misc/npcm7xx_clk.h  |  2 +-
 include/hw/misc/npcm7xx_gcr.h  |  6 +++---
 include/hw/misc/npcm7xx_mft.h  |  7 +++----
 include/hw/misc/npcm7xx_pwm.h  |  3 +--
 include/hw/misc/npcm7xx_rng.h  |  6 +++---
 include/hw/net/npcm7xx_emc.h   |  5 +----
 include/hw/sd/npcm7xx_sdhci.h  |  4 ++--
 10 files changed, 26 insertions(+), 39 deletions(-)

diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/adc/npcm7xx_adc.h
+++ b/include/hw/adc/npcm7xx_adc.h
@@ -XXX,XX +XXX,XX @@
  * @iref: The internal reference voltage, initialized at launch time.
  * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
  */
-typedef struct {
+struct NPCM7xxADCState {
     SysBusDevice parent;
 
     MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct {
     uint32_t     iref;
 
     uint16_t     calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
-} NPCM7xxADCState;
+};
 
 #define TYPE_NPCM7XX_ADC "npcm7xx-adc"
-#define NPCM7XX_ADC(obj) \
-    OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxADCState, NPCM7XX_ADC)
 
 #endif /* NPCM7XX_ADC_H */
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 
 #define NPCM7XX_NR_PWM_MODULES 2
 
-typedef struct NPCM7xxMachine {
+struct NPCM7xxMachine {
     MachineState        parent;
     /*
      * PWM fan splitter. each splitter connects to one PWM output and
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMachine {
      */
     SplitIRQ            fan_splitter[NPCM7XX_NR_PWM_MODULES *
                                      NPCM7XX_PWM_PER_MODULE];
-} NPCM7xxMachine;
+};
 
 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
-#define NPCM7XX_MACHINE(obj)                                            \
-    OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMachine, NPCM7XX_MACHINE)
 
 typedef struct NPCM7xxMachineClass {
     MachineClass        parent;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMachineClass {
 #define NPCM7XX_MACHINE_GET_CLASS(obj)                                  \
     OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
 
-typedef struct NPCM7xxState {
+struct NPCM7xxState {
     DeviceState         parent;
 
     ARMCPU              cpu[NPCM7XX_MAX_NUM_CPUS];
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxFIUState     fiu[2];
     NPCM7xxEMCState     emc[2];
     NPCM7xxSDHCIState   mmc;
-} NPCM7xxState;
+};
 
 #define TYPE_NPCM7XX    "npcm7xx"
-#define NPCM7XX(obj)    OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
+OBJECT_DECLARE_TYPE(NPCM7xxState, NPCM7xxClass, NPCM7XX)
 
 #define TYPE_NPCM730    "npcm730"
 #define TYPE_NPCM750    "npcm750"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxClass {
     uint32_t            num_cpus;
 } NPCM7xxClass;
 
-#define NPCM7XX_CLASS(klass)                                            \
-    OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
-#define NPCM7XX_GET_CLASS(obj)                                          \
-    OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
-
 /**
  * npcm7xx_load_kernel - Loads memory with everything needed to boot
  * @machine - The machine containing the SoC to be booted.
diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/i2c/npcm7xx_smbus.h
+++ b/include/hw/i2c/npcm7xx_smbus.h
@@ -XXX,XX +XXX,XX @@ typedef enum NPCM7xxSMBusStatus {
  * @rx_cur: The current position of rx_fifo.
  * @status: The current status of the SMBus.
  */
-typedef struct NPCM7xxSMBusState {
+struct NPCM7xxSMBusState {
     SysBusDevice parent;
 
     MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxSMBusState {
     uint8_t      rx_cur;
 
     NPCM7xxSMBusStatus status;
-} NPCM7xxSMBusState;
+};
 
 #define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
-#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \
-                                        TYPE_NPCM7XX_SMBUS)
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxSMBusState, NPCM7XX_SMBUS)
 
 #endif /* NPCM7XX_SMBUS_H */
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxCLKState {
 };
 
 #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
-#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
 
 #endif /* NPCM7XX_CLK_H */
diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_gcr.h
+++ b/include/hw/misc/npcm7xx_gcr.h
@@ -XXX,XX +XXX,XX @@
  */
 #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
 
-typedef struct NPCM7xxGCRState {
+struct NPCM7xxGCRState {
     SysBusDevice parent;
 
     MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxGCRState {
     uint32_t reset_pwron;
     uint32_t reset_mdlr;
     uint32_t reset_intcr3;
-} NPCM7xxGCRState;
+};
 
 #define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
-#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR)
 
 #endif /* NPCM7XX_GCR_H */
diff --git a/include/hw/misc/npcm7xx_mft.h b/include/hw/misc/npcm7xx_mft.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_mft.h
+++ b/include/hw/misc/npcm7xx_mft.h
@@ -XXX,XX +XXX,XX @@
  * @max_rpm: The maximum rpm for fans. Order: A0, B0, A1, B1.
  * @duty: The duty cycles for fans, relative to NPCM7XX_PWM_MAX_DUTY.
  */
-typedef struct NPCM7xxMFTState {
+struct NPCM7xxMFTState {
     SysBusDevice parent;
 
     MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMFTState {
 
     uint32_t    max_rpm[NPCM7XX_MFT_FANIN_COUNT];
     uint32_t    duty[NPCM7XX_MFT_FANIN_COUNT];
-} NPCM7xxMFTState;
+};
 
 #define TYPE_NPCM7XX_MFT "npcm7xx-mft"
-#define NPCM7XX_MFT(obj) \
-    OBJECT_CHECK(NPCM7xxMFTState, (obj), TYPE_NPCM7XX_MFT)
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMFTState, NPCM7XX_MFT)
 
 #endif /* NPCM7XX_MFT_H */
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_pwm.h
+++ b/include/hw/misc/npcm7xx_pwm.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxPWMState {
 };
 
 #define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
-#define NPCM7XX_PWM(obj) \
-    OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxPWMState, NPCM7XX_PWM)
 
 #endif /* NPCM7XX_PWM_H */
diff --git a/include/hw/misc/npcm7xx_rng.h b/include/hw/misc/npcm7xx_rng.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_rng.h
+++ b/include/hw/misc/npcm7xx_rng.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/sysbus.h"
 
-typedef struct NPCM7xxRNGState {
+struct NPCM7xxRNGState {
     SysBusDevice parent;
 
     MemoryRegion iomem;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxRNGState {
     uint8_t rngcs;
     uint8_t rngd;
     uint8_t rngmode;
-} NPCM7xxRNGState;
+};
 
 #define TYPE_NPCM7XX_RNG "npcm7xx-rng"
-#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxRNGState, NPCM7XX_RNG)
 
 #endif /* NPCM7XX_RNG_H */
diff --git a/include/hw/net/npcm7xx_emc.h b/include/hw/net/npcm7xx_emc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/net/npcm7xx_emc.h
+++ b/include/hw/net/npcm7xx_emc.h
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxEMCState {
     bool rx_active;
 };
 
-typedef struct NPCM7xxEMCState NPCM7xxEMCState;
-
 #define TYPE_NPCM7XX_EMC "npcm7xx-emc"
-#define NPCM7XX_EMC(obj) \
-    OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC)
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxEMCState, NPCM7XX_EMC)
 
 #endif /* NPCM7XX_EMC_H */
diff --git a/include/hw/sd/npcm7xx_sdhci.h b/include/hw/sd/npcm7xx_sdhci.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/sd/npcm7xx_sdhci.h
+++ b/include/hw/sd/npcm7xx_sdhci.h
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxRegs {
     uint32_t boottoctrl;
 } NPCM7xxRegisters;
 
-typedef struct NPCM7xxSDHCIState {
+struct NPCM7xxSDHCIState {
     SysBusDevice parent;
 
     MemoryRegion container;
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxSDHCIState {
     NPCM7xxRegisters regs;
 
     SDHCIState sdhci;
-} NPCM7xxSDHCIState;
+};
 
 #endif /* NPCM7XX_SDHCI_H */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The structure is named SECUREECState. Rename the type accordingly.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-12-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/sbsa_ec.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/hw/misc/sbsa_ec.c b/hw/misc/sbsa_ec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/sbsa_ec.c
+++ b/hw/misc/sbsa_ec.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "sysemu/runstate.h"
 
-typedef struct {
+typedef struct SECUREECState {
     SysBusDevice parent_obj;
     MemoryRegion iomem;
 } SECUREECState;
 
-#define TYPE_SBSA_EC      "sbsa-ec"
-#define SECURE_EC(obj) OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_EC)
+#define TYPE_SBSA_SECURE_EC "sbsa-ec"
+#define SBSA_SECURE_EC(obj) \
+        OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_SECURE_EC)
 
 enum sbsa_ec_powerstates {
     SBSA_EC_CMD_POWEROFF = 0x01,
@@ -XXX,XX +XXX,XX @@ static uint64_t sbsa_ec_read(void *opaque, hwaddr offset, unsigned size)
 }
 
 static void sbsa_ec_write(void *opaque, hwaddr offset,
-                     uint64_t value, unsigned size)
+                          uint64_t value, unsigned size)
 {
     if (offset == 0) { /* PSCI machine power command register */
         switch (value) {
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sbsa_ec_ops = {
 
 static void sbsa_ec_init(Object *obj)
 {
-    SECUREECState *s = SECURE_EC(obj);
+    SECUREECState *s = SBSA_SECURE_EC(obj);
     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 
     memory_region_init_io(&s->iomem, obj, &sbsa_ec_ops, s, "sbsa-ec",
@@ -XXX,XX +XXX,XX @@ static void sbsa_ec_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo sbsa_ec_info = {
-    .name          = TYPE_SBSA_EC,
+    .name          = TYPE_SBSA_SECURE_EC,
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(SECUREECState),
     .instance_init = sbsa_ec_init,
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
macro call, to avoid after a QOM refactor:

hw/intc/xilinx_intc.c:45:1: error: declaration of anonymous struct must be a definition
  DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
                           ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Message-id: 20230109140306.23161-14-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/xilinx_intc.c | 28 +++++++++++++---------------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -XXX,XX +XXX,XX @@
 #define R_MAX       8
 
 #define TYPE_XILINX_INTC "xlnx.xps-intc"
-DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
-                         TYPE_XILINX_INTC)
+typedef struct XpsIntc XpsIntc;
+DECLARE_INSTANCE_CHECKER(XpsIntc, XILINX_INTC, TYPE_XILINX_INTC)
 
-struct xlx_pic
+struct XpsIntc
 {
     SysBusDevice parent_obj;
 
@@ -XXX,XX +XXX,XX @@ struct xlx_pic
     uint32_t irq_pin_state;
 };
 
-static void update_irq(struct xlx_pic *p)
+static void update_irq(XpsIntc *p)
 {
     uint32_t i;
 
@@ -XXX,XX +XXX,XX @@ static void update_irq(struct xlx_pic *p)
     qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
 }
 
-static uint64_t
-pic_read(void *opaque, hwaddr addr, unsigned int size)
+static uint64_t pic_read(void *opaque, hwaddr addr, unsigned int size)
 {
-    struct xlx_pic *p = opaque;
+    XpsIntc *p = opaque;
     uint32_t r = 0;
 
     addr >>= 2;
@@ -XXX,XX +XXX,XX @@ pic_read(void *opaque, hwaddr addr, unsigned int size)
     return r;
 }
 
-static void
-pic_write(void *opaque, hwaddr addr,
-          uint64_t val64, unsigned int size)
+static void pic_write(void *opaque, hwaddr addr,
+                      uint64_t val64, unsigned int size)
 {
-    struct xlx_pic *p = opaque;
+    XpsIntc *p = opaque;
     uint32_t value = val64;
 
     addr >>= 2;
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pic_ops = {
 
 static void irq_handler(void *opaque, int irq, int level)
 {
-    struct xlx_pic *p = opaque;
+    XpsIntc *p = opaque;
 
     /* edge triggered interrupt */
     if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
@@ -XXX,XX +XXX,XX @@ static void irq_handler(void *opaque, int irq, int level)
 
 static void xilinx_intc_init(Object *obj)
 {
-    struct xlx_pic *p = XILINX_INTC(obj);
+    XpsIntc *p = XILINX_INTC(obj);
 
     qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
@@ -XXX,XX +XXX,XX @@ static void xilinx_intc_init(Object *obj)
 }
 
 static Property xilinx_intc_properties[] = {
-    DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
+    DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data)
 static const TypeInfo xilinx_intc_info = {
     .name          = TYPE_XILINX_INTC,
     .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(struct xlx_pic),
+    .instance_size = sizeof(XpsIntc),
     .instance_init = xilinx_intc_init,
     .class_init    = xilinx_intc_class_init,
 };
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
macro call, to avoid after a QOM refactor:

hw/timer/xilinx_timer.c:65:1: error: declaration of anonymous struct must be a definition
  DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
                           ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Message-id: 20230109140306.23161-15-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/xilinx_timer.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -XXX,XX +XXX,XX @@ struct xlx_timer
 };
 
 #define TYPE_XILINX_TIMER "xlnx.xps-timer"
-DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
-                         TYPE_XILINX_TIMER)
+typedef struct XpsTimerState XpsTimerState;
+DECLARE_INSTANCE_CHECKER(XpsTimerState, XILINX_TIMER, TYPE_XILINX_TIMER)
 
-struct timerblock
+struct XpsTimerState
 {
     SysBusDevice parent_obj;
 
@@ -XXX,XX +XXX,XX @@ struct timerblock
     struct xlx_timer *timers;
 };
 
-static inline unsigned int num_timers(struct timerblock *t)
+static inline unsigned int num_timers(XpsTimerState *t)
 {
     return 2 - t->one_timer_only;
 }
@@ -XXX,XX +XXX,XX @@ static inline unsigned int timer_from_addr(hwaddr addr)
     return addr >> 2;
 }
 
-static void timer_update_irq(struct timerblock *t)
+static void timer_update_irq(XpsTimerState *t)
 {
     unsigned int i, irq = 0;
     uint32_t csr;
@@ -XXX,XX +XXX,XX @@ static void timer_update_irq(struct timerblock *t)
 static uint64_t
 timer_read(void *opaque, hwaddr addr, unsigned int size)
 {
-    struct timerblock *t = opaque;
+    XpsTimerState *t = opaque;
     struct xlx_timer *xt;
     uint32_t r = 0;
     unsigned int timer;
@@ -XXX,XX +XXX,XX @@ static void
 timer_write(void *opaque, hwaddr addr,
             uint64_t val64, unsigned int size)
 {
-    struct timerblock *t = opaque;
+    XpsTimerState *t = opaque;
     struct xlx_timer *xt;
     unsigned int timer;
     uint32_t value = val64;
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps timer_ops = {
 static void timer_hit(void *opaque)
 {
     struct xlx_timer *xt = opaque;
-    struct timerblock *t = xt->parent;
+    XpsTimerState *t = xt->parent;
     D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
     xt->regs[R_TCSR] |= TCSR_TINT;
 
@@ -XXX,XX +XXX,XX @@ static void timer_hit(void *opaque)
 
 static void xilinx_timer_realize(DeviceState *dev, Error **errp)
 {
-    struct timerblock *t = XILINX_TIMER(dev);
+    XpsTimerState *t = XILINX_TIMER(dev);
     unsigned int i;
 
     /* Init all the ptimers.  */
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
 
 static void xilinx_timer_init(Object *obj)
 {
-    struct timerblock *t = XILINX_TIMER(obj);
+    XpsTimerState *t = XILINX_TIMER(obj);
 
     /* All timers share a single irq line.  */
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
 }
 
 static Property xilinx_timer_properties[] = {
-    DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
-                                                                62 * 1000000),
-    DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
+    DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000),
+    DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_class_init(ObjectClass *klass, void *data)
 static const TypeInfo xilinx_timer_info = {
     .name          = TYPE_XILINX_TIMER,
     .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(struct timerblock),
+    .instance_size = sizeof(XpsTimerState),
     .instance_init = xilinx_timer_init,
     .class_init    = xilinx_timer_class_init,
 };
-- 
2.34.1

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit
to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu
uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3
write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is
enabled and exposed to the guest. As a result EL3 writes of that bit are
ignored.

Cc: qemu-stable@nongnu.org
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Message-id: 20230105221251.17896-4-eiakovlev@linux.microsoft.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         if (cpu_isar_feature(aa64_sme, cpu)) {
             valid_mask |= SCR_ENTP2;
         }
+        if (cpu_isar_feature(aa64_hcx, cpu)) {
+            valid_mask |= SCR_HXEN;
+        }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
         if (cpu_isar_feature(aa32_ras, cpu)) {
-- 
2.34.1