[Qemu-devel] [PULL 0/6] target-arm queue
[PULL 00/26] target-arm queue
1
Last lot of patches for arm before softfreeze tomorrow...
1
Small pile of bug fixes for rc1. I've included my patches to get
2
our docs building with Sphinx 3, just for convenience...
2
3
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit ef3a6af5e789ff078d1fef880f9dfb6adf18e8f1:
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The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96:
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8
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20181029-pull-request' into staging (2018-10-29 12:59:15 +0000)
8
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000)
9
9
10
are available in the Git repository at:
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are available in the Git repository at:
11
11
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181029
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102
13
13
14
for you to fetch changes up to 20cf5663734310a282e27b7389bc9f53ffe227e6:
14
for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a:
15
15
16
tests/boot-serial-test: Add microbit board testcase (2018-10-29 15:19:48 +0000)
16
tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* microbit: Add the UART to our nRF51 SoC model
20
* target/arm: Fix Neon emulation bugs on big-endian hosts
21
* Add a virtual Xilinx Versal board "xlnx-versal-virt"
21
* target/arm: fix handling of HCR.FB
22
* hw/arm/virt: Set VIRT_COMPAT_3_0 compat
22
* target/arm: fix LORID_EL1 access check
23
* disas/capstone: Fix monitor disassembly of >32 bytes
24
* hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
25
* hw/arm/boot: fix SVE for EL3 direct kernel boot
26
* hw/display/omap_lcdc: Fix potential NULL pointer dereference
27
* hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
28
* target/arm: Get correct MMU index for other-security-state
29
* configure: Test that gio libs from pkg-config work
30
* hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
31
* docs: Fix building with Sphinx 3
32
* tests/qtest/npcm7xx_rng-test: Disable randomness tests
23
33
24
----------------------------------------------------------------
34
----------------------------------------------------------------
25
Edgar E. Iglesias (2):
35
AlexChen (2):
26
hw/arm: versal: Add a model of Xilinx Versal SoC
36
hw/display/omap_lcdc: Fix potential NULL pointer dereference
27
hw/arm: versal: Add a virtual Xilinx Versal board
37
hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
28
38
29
Eric Auger (1):
39
Peter Maydell (9):
30
hw/arm/virt: Set VIRT_COMPAT_3_0 compat
40
target/arm: Fix float16 pairwise Neon ops on big-endian hosts
41
target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts
42
disas/capstone: Fix monitor disassembly of >32 bytes
43
target/arm: Get correct MMU index for other-security-state
44
configure: Test that gio libs from pkg-config work
45
hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
46
scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments
47
qemu-option-trace.rst.inc: Don't use option:: markup
48
tests/qtest/npcm7xx_rng-test: Disable randomness tests
31
49
32
Julia Suvorova (3):
50
Philippe Mathieu-Daudé (1):
33
hw/char: Implement nRF51 SoC UART
51
hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
34
hw/arm/nrf51_soc: Connect UART to nRF51 SoC
35
tests/boot-serial-test: Add microbit board testcase
36
52
37
hw/arm/Makefile.objs | 1 +
53
Richard Henderson (11):
38
hw/char/Makefile.objs | 1 +
54
target/arm: Introduce neon_full_reg_offset
39
include/hw/arm/nrf51_soc.h | 3 +
55
target/arm: Move neon_element_offset to translate.c
40
include/hw/arm/xlnx-versal.h | 122 +++++++++
56
target/arm: Use neon_element_offset in neon_load/store_reg
41
include/hw/char/nrf51_uart.h | 78 ++++++
57
target/arm: Use neon_element_offset in vfp_reg_offset
42
hw/arm/microbit.c | 2 +
58
target/arm: Add read/write_neon_element32
43
hw/arm/nrf51_soc.c | 20 ++
59
target/arm: Expand read/write_neon_element32 to all MemOp
44
hw/arm/virt.c | 4 +
60
target/arm: Rename neon_load_reg32 to vfp_load_reg32
45
hw/arm/xlnx-versal-virt.c | 493 ++++++++++++++++++++++++++++++++++++
61
target/arm: Add read/write_neon_element64
46
hw/arm/xlnx-versal.c | 323 +++++++++++++++++++++++
62
target/arm: Rename neon_load_reg64 to vfp_load_reg64
47
hw/char/nrf51_uart.c | 330 ++++++++++++++++++++++++
63
target/arm: Simplify do_long_3d and do_2scalar_long
48
tests/boot-serial-test.c | 19 ++
64
target/arm: Improve do_prewiden_3d
49
default-configs/aarch64-softmmu.mak | 1 +
50
hw/char/trace-events | 4 +
51
14 files changed, 1401 insertions(+)
52
create mode 100644 include/hw/arm/xlnx-versal.h
53
create mode 100644 include/hw/char/nrf51_uart.h
54
create mode 100644 hw/arm/xlnx-versal-virt.c
55
create mode 100644 hw/arm/xlnx-versal.c
56
create mode 100644 hw/char/nrf51_uart.c
57
65
66
Rémi Denis-Courmont (3):
67
target/arm: fix handling of HCR.FB
68
target/arm: fix LORID_EL1 access check
69
hw/arm/boot: fix SVE for EL3 direct kernel boot
70
71
docs/qemu-option-trace.rst.inc | 6 +-
72
configure | 10 +-
73
include/hw/intc/arm_gicv3_common.h | 1 -
74
disas/capstone.c | 2 +-
75
hw/arm/boot.c | 3 +
76
hw/arm/smmuv3.c | 3 +-
77
hw/display/exynos4210_fimd.c | 4 +-
78
hw/display/omap_lcdc.c | 10 +-
79
hw/intc/arm_gicv3_cpuif.c | 5 +-
80
target/arm/helper.c | 24 +-
81
target/arm/m_helper.c | 3 +-
82
target/arm/translate.c | 153 +++++++++---
83
target/arm/vec_helper.c | 12 +-
84
tests/qtest/npcm7xx_rng-test.c | 14 +-
85
scripts/kernel-doc | 18 +-
86
target/arm/translate-neon.c.inc | 472 ++++++++++++++++++++-----------------
87
target/arm/translate-vfp.c.inc | 341 +++++++++++----------------
88
17 files changed, 588 insertions(+), 493 deletions(-)
89
diff view generated by jsdifflib
New patch
[PULL 01/26] target/arm: Introduce neon_full_reg_offset
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This function makes it clear that we're talking about the whole
4
register, and not the 32-bit piece at index 0. This fixes a bug
5
when running on a big-endian host.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201030022618.785675-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate.c | 8 ++++++
13
target/arm/translate-neon.c.inc | 44 ++++++++++++++++-----------------
14
target/arm/translate-vfp.c.inc | 2 +-
15
3 files changed, 31 insertions(+), 23 deletions(-)
16
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate.c
20
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
22
unallocated_encoding(s);
23
}
24
25
+/*
26
+ * Return the offset of a "full" NEON Dreg.
27
+ */
28
+static long neon_full_reg_offset(unsigned reg)
29
+{
30
+ return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
31
+}
32
+
33
static inline long vfp_reg_offset(bool dp, unsigned reg)
34
{
35
if (dp) {
36
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/translate-neon.c.inc
39
+++ b/target/arm/translate-neon.c.inc
40
@@ -XXX,XX +XXX,XX @@ neon_element_offset(int reg, int element, MemOp size)
41
ofs ^= 8 - element_size;
42
}
43
#endif
44
- return neon_reg_offset(reg, 0) + ofs;
45
+ return neon_full_reg_offset(reg) + ofs;
46
}
47
48
static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
49
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
50
* We cannot write 16 bytes at once because the
51
* destination is unaligned.
52
*/
53
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
54
+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),
55
8, 8, tmp);
56
- tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),
57
- neon_reg_offset(vd, 0), 8, 8);
58
+ tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1),
59
+ neon_full_reg_offset(vd), 8, 8);
60
} else {
61
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
62
+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),
63
vec_size, vec_size, tmp);
64
}
65
tcg_gen_addi_i32(addr, addr, 1 << size);
66
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
67
static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
68
{
69
int vec_size = a->q ? 16 : 8;
70
- int rd_ofs = neon_reg_offset(a->vd, 0);
71
- int rn_ofs = neon_reg_offset(a->vn, 0);
72
- int rm_ofs = neon_reg_offset(a->vm, 0);
73
+ int rd_ofs = neon_full_reg_offset(a->vd);
74
+ int rn_ofs = neon_full_reg_offset(a->vn);
75
+ int rm_ofs = neon_full_reg_offset(a->vm);
76
77
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
78
return false;
79
@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
80
{
81
/* Handle a 2-reg-shift insn which can be vectorized. */
82
int vec_size = a->q ? 16 : 8;
83
- int rd_ofs = neon_reg_offset(a->vd, 0);
84
- int rm_ofs = neon_reg_offset(a->vm, 0);
85
+ int rd_ofs = neon_full_reg_offset(a->vd);
86
+ int rm_ofs = neon_full_reg_offset(a->vm);
87
88
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
89
return false;
90
@@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
91
{
92
/* FP operations in 2-reg-and-shift group */
93
int vec_size = a->q ? 16 : 8;
94
- int rd_ofs = neon_reg_offset(a->vd, 0);
95
- int rm_ofs = neon_reg_offset(a->vm, 0);
96
+ int rd_ofs = neon_full_reg_offset(a->vd);
97
+ int rm_ofs = neon_full_reg_offset(a->vm);
98
TCGv_ptr fpst;
99
100
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
101
@@ -XXX,XX +XXX,XX @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
102
return true;
103
}
104
105
- reg_ofs = neon_reg_offset(a->vd, 0);
106
+ reg_ofs = neon_full_reg_offset(a->vd);
107
vec_size = a->q ? 16 : 8;
108
imm = asimd_imm_const(a->imm, a->cmode, a->op);
109
110
@@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a)
111
return true;
112
}
113
114
- tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0),
115
- neon_reg_offset(a->vn, 0),
116
- neon_reg_offset(a->vm, 0),
117
+ tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd),
118
+ neon_full_reg_offset(a->vn),
119
+ neon_full_reg_offset(a->vm),
120
16, 16, 0, fn_gvec);
121
return true;
122
}
123
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
124
{
125
/* Two registers and a scalar, using gvec */
126
int vec_size = a->q ? 16 : 8;
127
- int rd_ofs = neon_reg_offset(a->vd, 0);
128
- int rn_ofs = neon_reg_offset(a->vn, 0);
129
+ int rd_ofs = neon_full_reg_offset(a->vd);
130
+ int rn_ofs = neon_full_reg_offset(a->vn);
131
int rm_ofs;
132
int idx;
133
TCGv_ptr fpstatus;
134
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
135
/* a->vm is M:Vm, which encodes both register and index */
136
idx = extract32(a->vm, a->size + 2, 2);
137
a->vm = extract32(a->vm, 0, a->size + 2);
138
- rm_ofs = neon_reg_offset(a->vm, 0);
139
+ rm_ofs = neon_full_reg_offset(a->vm);
140
141
fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD);
142
tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus,
143
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
144
return true;
145
}
146
147
- tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0),
148
+ tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd),
149
neon_element_offset(a->vm, a->index, a->size),
150
a->q ? 16 : 8, a->q ? 16 : 8);
151
return true;
152
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
153
static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
154
{
155
int vec_size = a->q ? 16 : 8;
156
- int rd_ofs = neon_reg_offset(a->vd, 0);
157
- int rm_ofs = neon_reg_offset(a->vm, 0);
158
+ int rd_ofs = neon_full_reg_offset(a->vd);
159
+ int rm_ofs = neon_full_reg_offset(a->vm);
160
161
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
162
return false;
163
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
164
index XXXXXXX..XXXXXXX 100644
165
--- a/target/arm/translate-vfp.c.inc
166
+++ b/target/arm/translate-vfp.c.inc
167
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
168
}
169
170
tmp = load_reg(s, a->rt);
171
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0),
172
+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn),
173
vec_size, vec_size, tmp);
174
tcg_temp_free_i32(tmp);
175
176
--
177
2.20.1
178
179
diff view generated by jsdifflib
New patch
[PULL 02/26] target/arm: Move neon_element_offset to translate.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This will shortly have users outside of translate-neon.c.inc.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20201030022618.785675-3-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate.c | 20 ++++++++++++++++++++
11
target/arm/translate-neon.c.inc | 19 -------------------
12
2 files changed, 20 insertions(+), 19 deletions(-)
13
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
17
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg)
19
return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
20
}
21
22
+/*
23
+ * Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
24
+ * where 0 is the least significant end of the register.
25
+ */
26
+static long neon_element_offset(int reg, int element, MemOp size)
27
+{
28
+ int element_size = 1 << size;
29
+ int ofs = element * element_size;
30
+#ifdef HOST_WORDS_BIGENDIAN
31
+ /*
32
+ * Calculate the offset assuming fully little-endian,
33
+ * then XOR to account for the order of the 8-byte units.
34
+ */
35
+ if (element_size < 8) {
36
+ ofs ^= 8 - element_size;
37
+ }
38
+#endif
39
+ return neon_full_reg_offset(reg) + ofs;
40
+}
41
+
42
static inline long vfp_reg_offset(bool dp, unsigned reg)
43
{
44
if (dp) {
45
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/translate-neon.c.inc
48
+++ b/target/arm/translate-neon.c.inc
49
@@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x)
50
#include "decode-neon-ls.c.inc"
51
#include "decode-neon-shared.c.inc"
52
53
-/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
54
- * where 0 is the least significant end of the register.
55
- */
56
-static inline long
57
-neon_element_offset(int reg, int element, MemOp size)
58
-{
59
- int element_size = 1 << size;
60
- int ofs = element * element_size;
61
-#ifdef HOST_WORDS_BIGENDIAN
62
- /* Calculate the offset assuming fully little-endian,
63
- * then XOR to account for the order of the 8-byte units.
64
- */
65
- if (element_size < 8) {
66
- ofs ^= 8 - element_size;
67
- }
68
-#endif
69
- return neon_full_reg_offset(reg) + ofs;
70
-}
71
-
72
static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
73
{
74
long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
75
--
76
2.20.1
77
78
diff view generated by jsdifflib
New patch
[PULL 03/26] target/arm: Use neon_element_offset in neon_load/store_reg
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
These are the only users of neon_reg_offset, so remove that.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20201030022618.785675-4-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate.c | 14 ++------------
11
1 file changed, 2 insertions(+), 12 deletions(-)
12
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static inline long vfp_reg_offset(bool dp, unsigned reg)
18
}
19
}
20
21
-/* Return the offset of a 32-bit piece of a NEON register.
22
- zero is the least significant end of the register. */
23
-static inline long
24
-neon_reg_offset (int reg, int n)
25
-{
26
- int sreg;
27
- sreg = reg * 2 + n;
28
- return vfp_reg_offset(0, sreg);
29
-}
30
-
31
static TCGv_i32 neon_load_reg(int reg, int pass)
32
{
33
TCGv_i32 tmp = tcg_temp_new_i32();
34
- tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
35
+ tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
36
return tmp;
37
}
38
39
static void neon_store_reg(int reg, int pass, TCGv_i32 var)
40
{
41
- tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
42
+ tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
43
tcg_temp_free_i32(var);
44
}
45
46
--
47
2.20.1
48
49
diff view generated by jsdifflib
New patch
[PULL 04/26] target/arm: Use neon_element_offset in vfp_reg_offset
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This seems a bit more readable than using offsetof CPU_DoubleU.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20201030022618.785675-5-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate.c | 13 ++++---------
11
1 file changed, 4 insertions(+), 9 deletions(-)
12
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp size)
18
return neon_full_reg_offset(reg) + ofs;
19
}
20
21
-static inline long vfp_reg_offset(bool dp, unsigned reg)
22
+/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */
23
+static long vfp_reg_offset(bool dp, unsigned reg)
24
{
25
if (dp) {
26
- return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
27
+ return neon_element_offset(reg, 0, MO_64);
28
} else {
29
- long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]);
30
- if (reg & 1) {
31
- ofs += offsetof(CPU_DoubleU, l.upper);
32
- } else {
33
- ofs += offsetof(CPU_DoubleU, l.lower);
34
- }
35
- return ofs;
36
+ return neon_element_offset(reg >> 1, reg & 1, MO_32);
37
}
38
}
39
40
--
41
2.20.1
42
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/6] hw/arm: versal: Add a virtual Xilinx Versal board
[PULL 05/26] target/arm: Add read/write_neon_element32
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add a virtual Xilinx Versal board.
3
Model these off the aa64 read/write_vec_element functions.
4
Use it within translate-neon.c.inc. The new functions do
5
not allocate or free temps, so this rearranges the calling
6
code a bit.
4
7
5
This board is based on the Xilinx Versal SoC. The exact
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
details of what peripherals are attached to this board
9
Message-id: 20201030022618.785675-6-richard.henderson@linaro.org
7
will remain in control of QEMU. QEMU will generate an
8
FDT on the fly for Linux and other software to auto-discover
9
peripherals.
10
11
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
[PMM: removed stray blank line at EOF]
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
hw/arm/Makefile.objs | 2 +-
13
target/arm/translate.c | 26 ++++
17
hw/arm/xlnx-versal-virt.c | 493 ++++++++++++++++++++++++++++++++++++++
14
target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------
18
2 files changed, 494 insertions(+), 1 deletion(-)
15
2 files changed, 183 insertions(+), 99 deletions(-)
19
create mode 100644 hw/arm/xlnx-versal-virt.c
20
16
21
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
22
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/Makefile.objs
19
--- a/target/arm/translate.c
24
+++ b/hw/arm/Makefile.objs
20
+++ b/target/arm/translate.c
25
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
21
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)
26
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
22
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
27
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
23
}
28
obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
24
29
-obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o
25
+static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
30
+obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o
31
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
32
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
33
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
34
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
35
new file mode 100644
36
index XXXXXXX..XXXXXXX
37
--- /dev/null
38
+++ b/hw/arm/xlnx-versal-virt.c
39
@@ -XXX,XX +XXX,XX @@
40
+/*
41
+ * Xilinx Versal Virtual board.
42
+ *
43
+ * Copyright (c) 2018 Xilinx Inc.
44
+ * Written by Edgar E. Iglesias
45
+ *
46
+ * This program is free software; you can redistribute it and/or modify
47
+ * it under the terms of the GNU General Public License version 2 or
48
+ * (at your option) any later version.
49
+ */
50
+
51
+#include "qemu/osdep.h"
52
+#include "qemu/log.h"
53
+#include "qemu/error-report.h"
54
+#include "qapi/error.h"
55
+#include "sysemu/device_tree.h"
56
+#include "exec/address-spaces.h"
57
+#include "hw/boards.h"
58
+#include "hw/sysbus.h"
59
+#include "hw/arm/sysbus-fdt.h"
60
+#include "hw/arm/fdt.h"
61
+#include "cpu.h"
62
+#include "hw/arm/xlnx-versal.h"
63
+
64
+#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
65
+#define XLNX_VERSAL_VIRT_MACHINE(obj) \
66
+ OBJECT_CHECK(VersalVirt, (obj), TYPE_XLNX_VERSAL_VIRT_MACHINE)
67
+
68
+typedef struct VersalVirt {
69
+ MachineState parent_obj;
70
+
71
+ Versal soc;
72
+ MemoryRegion mr_ddr;
73
+
74
+ void *fdt;
75
+ int fdt_size;
76
+ struct {
77
+ uint32_t gic;
78
+ uint32_t ethernet_phy[2];
79
+ uint32_t clk_125Mhz;
80
+ uint32_t clk_25Mhz;
81
+ } phandle;
82
+ struct arm_boot_info binfo;
83
+
84
+ struct {
85
+ bool secure;
86
+ } cfg;
87
+} VersalVirt;
88
+
89
+static void fdt_create(VersalVirt *s)
90
+{
26
+{
91
+ MachineClass *mc = MACHINE_GET_CLASS(s);
27
+ long off = neon_element_offset(reg, ele, size);
92
+ int i;
28
+
93
+
29
+ switch (size) {
94
+ s->fdt = create_device_tree(&s->fdt_size);
30
+ case MO_32:
95
+ if (!s->fdt) {
31
+ tcg_gen_ld_i32(dest, cpu_env, off);
96
+ error_report("create_device_tree() failed");
97
+ exit(1);
98
+ }
99
+
100
+ /* Allocate all phandles. */
101
+ s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt);
102
+ for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) {
103
+ s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt);
104
+ }
105
+ s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
106
+ s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
107
+
108
+ /* Create /chosen node for load_dtb. */
109
+ qemu_fdt_add_subnode(s->fdt, "/chosen");
110
+
111
+ /* Header */
112
+ qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic);
113
+ qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2);
114
+ qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2);
115
+ qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc);
116
+ qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt");
117
+}
118
+
119
+static void fdt_add_clk_node(VersalVirt *s, const char *name,
120
+ unsigned int freq_hz, uint32_t phandle)
121
+{
122
+ qemu_fdt_add_subnode(s->fdt, name);
123
+ qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
124
+ qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
125
+ qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
126
+ qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
127
+ qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
128
+}
129
+
130
+static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
131
+{
132
+ int i;
133
+
134
+ qemu_fdt_add_subnode(s->fdt, "/cpus");
135
+ qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0);
136
+ qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1);
137
+
138
+ for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
139
+ char *name = g_strdup_printf("/cpus/cpu@%d", i);
140
+ ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
141
+
142
+ qemu_fdt_add_subnode(s->fdt, name);
143
+ qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
144
+ if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
145
+ qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
146
+ }
147
+ qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu");
148
+ qemu_fdt_setprop_string(s->fdt, name, "compatible",
149
+ armcpu->dtb_compatible);
150
+ g_free(name);
151
+ }
152
+}
153
+
154
+static void fdt_add_gic_nodes(VersalVirt *s)
155
+{
156
+ char *nodename;
157
+
158
+ nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN);
159
+ qemu_fdt_add_subnode(s->fdt, nodename);
160
+ qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic);
161
+ qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts",
162
+ GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ,
163
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
164
+ qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0);
165
+ qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
166
+ 2, MM_GIC_APU_DIST_MAIN,
167
+ 2, MM_GIC_APU_DIST_MAIN_SIZE,
168
+ 2, MM_GIC_APU_REDIST_0,
169
+ 2, MM_GIC_APU_REDIST_0_SIZE);
170
+ qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3);
171
+ qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3");
172
+}
173
+
174
+static void fdt_add_timer_nodes(VersalVirt *s)
175
+{
176
+ const char compat[] = "arm,armv8-timer";
177
+ uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
178
+
179
+ qemu_fdt_add_subnode(s->fdt, "/timer");
180
+ qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts",
181
+ GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags,
182
+ GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags,
183
+ GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags,
184
+ GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags);
185
+ qemu_fdt_setprop(s->fdt, "/timer", "compatible",
186
+ compat, sizeof(compat));
187
+}
188
+
189
+static void fdt_add_uart_nodes(VersalVirt *s)
190
+{
191
+ uint64_t addrs[] = { MM_UART1, MM_UART0 };
192
+ unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 };
193
+ const char compat[] = "arm,pl011\0arm,sbsa-uart";
194
+ const char clocknames[] = "uartclk\0apb_pclk";
195
+ int i;
196
+
197
+ for (i = 0; i < ARRAY_SIZE(addrs); i++) {
198
+ char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]);
199
+ qemu_fdt_add_subnode(s->fdt, name);
200
+ qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200);
201
+ qemu_fdt_setprop_cells(s->fdt, name, "clocks",
202
+ s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
203
+ qemu_fdt_setprop(s->fdt, name, "clock-names",
204
+ clocknames, sizeof(clocknames));
205
+
206
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
207
+ GIC_FDT_IRQ_TYPE_SPI, irqs[i],
208
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
209
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
210
+ 2, addrs[i], 2, 0x1000);
211
+ qemu_fdt_setprop(s->fdt, name, "compatible",
212
+ compat, sizeof(compat));
213
+ qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
214
+
215
+ if (addrs[i] == MM_UART0) {
216
+ /* Select UART0. */
217
+ qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name);
218
+ }
219
+ g_free(name);
220
+ }
221
+}
222
+
223
+static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname,
224
+ uint32_t phandle)
225
+{
226
+ char *name = g_strdup_printf("%s/fixed-link", gemname);
227
+
228
+ qemu_fdt_add_subnode(s->fdt, name);
229
+ qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
230
+ qemu_fdt_setprop_cells(s->fdt, name, "full-duplex");
231
+ qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000);
232
+ g_free(name);
233
+}
234
+
235
+static void fdt_add_gem_nodes(VersalVirt *s)
236
+{
237
+ uint64_t addrs[] = { MM_GEM1, MM_GEM0 };
238
+ unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 };
239
+ const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk";
240
+ const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem";
241
+ int i;
242
+
243
+ for (i = 0; i < ARRAY_SIZE(addrs); i++) {
244
+ char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]);
245
+ qemu_fdt_add_subnode(s->fdt, name);
246
+
247
+ fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]);
248
+ qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id");
249
+ qemu_fdt_setprop_cell(s->fdt, name, "phy-handle",
250
+ s->phandle.ethernet_phy[i]);
251
+ qemu_fdt_setprop_cells(s->fdt, name, "clocks",
252
+ s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
253
+ s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
254
+ qemu_fdt_setprop(s->fdt, name, "clock-names",
255
+ clocknames, sizeof(clocknames));
256
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
257
+ GIC_FDT_IRQ_TYPE_SPI, irqs[i],
258
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI,
259
+ GIC_FDT_IRQ_TYPE_SPI, irqs[i],
260
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
261
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
262
+ 2, addrs[i], 2, 0x1000);
263
+ qemu_fdt_setprop(s->fdt, name, "compatible",
264
+ compat_gem, sizeof(compat_gem));
265
+ qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1);
266
+ qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0);
267
+ g_free(name);
268
+ }
269
+}
270
+
271
+static void fdt_nop_memory_nodes(void *fdt, Error **errp)
272
+{
273
+ Error *err = NULL;
274
+ char **node_path;
275
+ int n = 0;
276
+
277
+ node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
278
+ if (err) {
279
+ error_propagate(errp, err);
280
+ return;
281
+ }
282
+ while (node_path[n]) {
283
+ if (g_str_has_prefix(node_path[n], "/memory")) {
284
+ qemu_fdt_nop_node(fdt, node_path[n]);
285
+ }
286
+ n++;
287
+ }
288
+ g_strfreev(node_path);
289
+}
290
+
291
+static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size)
292
+{
293
+ /* Describes the various split DDR access regions. */
294
+ static const struct {
295
+ uint64_t base;
296
+ uint64_t size;
297
+ } addr_ranges[] = {
298
+ { MM_TOP_DDR, MM_TOP_DDR_SIZE },
299
+ { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
300
+ { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
301
+ { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
302
+ };
303
+ uint64_t mem_reg_prop[8] = {0};
304
+ uint64_t size = ram_size;
305
+ Error *err = NULL;
306
+ char *name;
307
+ int i;
308
+
309
+ fdt_nop_memory_nodes(fdt, &err);
310
+ if (err) {
311
+ error_report_err(err);
312
+ return;
313
+ }
314
+
315
+ name = g_strdup_printf("/memory@%x", MM_TOP_DDR);
316
+ for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
317
+ uint64_t mapsize;
318
+
319
+ mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
320
+
321
+ mem_reg_prop[i * 2] = addr_ranges[i].base;
322
+ mem_reg_prop[i * 2 + 1] = mapsize;
323
+ size -= mapsize;
324
+ }
325
+ qemu_fdt_add_subnode(fdt, name);
326
+ qemu_fdt_setprop_string(fdt, name, "device_type", "memory");
327
+
328
+ switch (i) {
329
+ case 1:
330
+ qemu_fdt_setprop_sized_cells(fdt, name, "reg",
331
+ 2, mem_reg_prop[0],
332
+ 2, mem_reg_prop[1]);
333
+ break;
334
+ case 2:
335
+ qemu_fdt_setprop_sized_cells(fdt, name, "reg",
336
+ 2, mem_reg_prop[0],
337
+ 2, mem_reg_prop[1],
338
+ 2, mem_reg_prop[2],
339
+ 2, mem_reg_prop[3]);
340
+ break;
341
+ case 3:
342
+ qemu_fdt_setprop_sized_cells(fdt, name, "reg",
343
+ 2, mem_reg_prop[0],
344
+ 2, mem_reg_prop[1],
345
+ 2, mem_reg_prop[2],
346
+ 2, mem_reg_prop[3],
347
+ 2, mem_reg_prop[4],
348
+ 2, mem_reg_prop[5]);
349
+ break;
350
+ case 4:
351
+ qemu_fdt_setprop_sized_cells(fdt, name, "reg",
352
+ 2, mem_reg_prop[0],
353
+ 2, mem_reg_prop[1],
354
+ 2, mem_reg_prop[2],
355
+ 2, mem_reg_prop[3],
356
+ 2, mem_reg_prop[4],
357
+ 2, mem_reg_prop[5],
358
+ 2, mem_reg_prop[6],
359
+ 2, mem_reg_prop[7]);
360
+ break;
32
+ break;
361
+ default:
33
+ default:
362
+ g_assert_not_reached();
34
+ g_assert_not_reached();
363
+ }
35
+ }
364
+ g_free(name);
365
+}
36
+}
366
+
37
+
367
+static void versal_virt_modify_dtb(const struct arm_boot_info *binfo,
38
+static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)
368
+ void *fdt)
369
+{
39
+{
370
+ VersalVirt *s = container_of(binfo, VersalVirt, binfo);
40
+ long off = neon_element_offset(reg, ele, size);
371
+
41
+
372
+ fdt_add_memory_nodes(s, fdt, binfo->ram_size);
42
+ switch (size) {
373
+}
43
+ case MO_32:
374
+
44
+ tcg_gen_st_i32(src, cpu_env, off);
375
+static void *versal_virt_get_dtb(const struct arm_boot_info *binfo,
45
+ break;
376
+ int *fdt_size)
46
+ default:
377
+{
47
+ g_assert_not_reached();
378
+ const VersalVirt *board = container_of(binfo, VersalVirt, binfo);
379
+
380
+ *fdt_size = board->fdt_size;
381
+ return board->fdt;
382
+}
383
+
384
+#define NUM_VIRTIO_TRANSPORT 32
385
+static void create_virtio_regions(VersalVirt *s)
386
+{
387
+ int virtio_mmio_size = 0x200;
388
+ int i;
389
+
390
+ for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
391
+ char *name = g_strdup_printf("virtio%d", i);;
392
+ hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
393
+ int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i;
394
+ MemoryRegion *mr;
395
+ DeviceState *dev;
396
+ qemu_irq pic_irq;
397
+
398
+ pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
399
+ dev = qdev_create(NULL, "virtio-mmio");
400
+ object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev),
401
+ &error_fatal);
402
+ qdev_init_nofail(dev);
403
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
404
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
405
+ memory_region_add_subregion(&s->soc.mr_ps, base, mr);
406
+ sysbus_create_simple("virtio-mmio", base, pic_irq);
407
+ }
408
+
409
+ for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
410
+ hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
411
+ int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i;
412
+ char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
413
+
414
+ qemu_fdt_add_subnode(s->fdt, name);
415
+ qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0);
416
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
417
+ GIC_FDT_IRQ_TYPE_SPI, irq,
418
+ GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
419
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
420
+ 2, base, 2, virtio_mmio_size);
421
+ qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio");
422
+ g_free(name);
423
+ }
48
+ }
424
+}
49
+}
425
+
50
+
426
+static void versal_virt_init(MachineState *machine)
51
static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
427
+{
52
{
428
+ VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
53
TCGv_ptr ret = tcg_temp_new_ptr();
429
+ int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
54
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
430
+
55
index XXXXXXX..XXXXXXX 100644
431
+ /*
56
--- a/target/arm/translate-neon.c.inc
432
+ * If the user provides an Operating System to be loaded, we expect them
57
+++ b/target/arm/translate-neon.c.inc
433
+ * to use the -kernel command line option.
58
@@ -XXX,XX +XXX,XX @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn)
434
+ *
59
* early. Since Q is 0 there are always just two passes, so instead
435
+ * Users can load firmware or boot-loaders with the -device loader options.
60
* of a complicated loop over each pass we just unroll.
436
+ *
61
*/
437
+ * When loading an OS, we generate a dtb and let arm_load_kernel() select
62
- tmp = neon_load_reg(a->vn, 0);
438
+ * where it gets loaded. This dtb will be passed to the kernel in x0.
63
- tmp2 = neon_load_reg(a->vn, 1);
439
+ *
64
+ tmp = tcg_temp_new_i32();
440
+ * If there's no -kernel option, we generate a DTB and place it at 0x1000
65
+ tmp2 = tcg_temp_new_i32();
441
+ * for the bootloaders or firmware to pick up.
66
+ tmp3 = tcg_temp_new_i32();
442
+ *
67
+
443
+ * If users want to provide their own DTB, they can use the -dtb option.
68
+ read_neon_element32(tmp, a->vn, 0, MO_32);
444
+ * These dtb's will have their memory nodes modified to match QEMU's
69
+ read_neon_element32(tmp2, a->vn, 1, MO_32);
445
+ * selected ram_size option before they get passed to the kernel or fw.
70
fn(tmp, tmp, tmp2);
446
+ *
71
- tcg_temp_free_i32(tmp2);
447
+ * When loading an OS, we turn on QEMU's PSCI implementation with SMC
72
448
+ * as the PSCI conduit. When there's no -kernel, we assume the user
73
- tmp3 = neon_load_reg(a->vm, 0);
449
+ * provides EL3 firmware to handle PSCI.
74
- tmp2 = neon_load_reg(a->vm, 1);
450
+ */
75
+ read_neon_element32(tmp3, a->vm, 0, MO_32);
451
+ if (machine->kernel_filename) {
76
+ read_neon_element32(tmp2, a->vm, 1, MO_32);
452
+ psci_conduit = QEMU_PSCI_CONDUIT_SMC;
77
fn(tmp3, tmp3, tmp2);
453
+ }
78
- tcg_temp_free_i32(tmp2);
454
+
79
455
+ memory_region_allocate_system_memory(&s->mr_ddr, NULL, "ddr",
80
- neon_store_reg(a->vd, 0, tmp);
456
+ machine->ram_size);
81
- neon_store_reg(a->vd, 1, tmp3);
457
+
82
+ write_neon_element32(tmp, a->vd, 0, MO_32);
458
+ sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
83
+ write_neon_element32(tmp3, a->vd, 1, MO_32);
459
+ sizeof(s->soc), TYPE_XLNX_VERSAL);
84
+
460
+ object_property_set_link(OBJECT(&s->soc), OBJECT(&s->mr_ddr),
85
+ tcg_temp_free_i32(tmp);
461
+ "ddr", &error_abort);
86
+ tcg_temp_free_i32(tmp2);
462
+ object_property_set_int(OBJECT(&s->soc), psci_conduit,
87
+ tcg_temp_free_i32(tmp3);
463
+ "psci-conduit", &error_abort);
88
return true;
464
+ object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
89
}
465
+
90
466
+ fdt_create(s);
91
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
467
+ create_virtio_regions(s);
92
* 2-reg-and-shift operations, size < 3 case, where the
468
+ fdt_add_gem_nodes(s);
93
* helper needs to be passed cpu_env.
469
+ fdt_add_uart_nodes(s);
94
*/
470
+ fdt_add_gic_nodes(s);
95
- TCGv_i32 constimm;
471
+ fdt_add_timer_nodes(s);
96
+ TCGv_i32 constimm, tmp;
472
+ fdt_add_cpu_nodes(s, psci_conduit);
97
int pass;
473
+ fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
98
474
+ fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
99
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
475
+
100
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
476
+ /* Make the APU cpu address space visible to virtio and other
101
* by immediate using the variable shift operations.
477
+ * modules unaware of muliple address-spaces. */
102
*/
478
+ memory_region_add_subregion_overlap(get_system_memory(),
103
constimm = tcg_const_i32(dup_const(a->size, a->shift));
479
+ 0, &s->soc.fpd.apu.mr, 0);
104
+ tmp = tcg_temp_new_i32();
480
+
105
481
+ s->binfo.ram_size = machine->ram_size;
106
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
482
+ s->binfo.kernel_filename = machine->kernel_filename;
107
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
483
+ s->binfo.kernel_cmdline = machine->kernel_cmdline;
108
+ read_neon_element32(tmp, a->vm, pass, MO_32);
484
+ s->binfo.initrd_filename = machine->initrd_filename;
109
fn(tmp, cpu_env, tmp, constimm);
485
+ s->binfo.loader_start = 0x0;
110
- neon_store_reg(a->vd, pass, tmp);
486
+ s->binfo.get_dtb = versal_virt_get_dtb;
111
+ write_neon_element32(tmp, a->vd, pass, MO_32);
487
+ s->binfo.modify_dtb = versal_virt_modify_dtb;
112
}
488
+ if (machine->kernel_filename) {
113
+ tcg_temp_free_i32(tmp);
489
+ arm_load_kernel(s->soc.fpd.apu.cpu[0], &s->binfo);
114
tcg_temp_free_i32(constimm);
490
+ } else {
115
return true;
491
+ AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
116
}
492
+ &s->binfo);
117
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
493
+ /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
118
constimm = tcg_const_i64(-a->shift);
494
+ * Offset things by 4K. */
119
rm1 = tcg_temp_new_i64();
495
+ s->binfo.loader_start = 0x1000;
120
rm2 = tcg_temp_new_i64();
496
+ s->binfo.dtb_limit = 0x1000000;
121
+ rd = tcg_temp_new_i32();
497
+ if (arm_load_dtb(s->binfo.loader_start,
122
498
+ &s->binfo, s->binfo.dtb_limit, as) < 0) {
123
/* Load both inputs first to avoid potential overwrite if rm == rd */
499
+ exit(EXIT_FAILURE);
124
neon_load_reg64(rm1, a->vm);
500
+ }
125
neon_load_reg64(rm2, a->vm + 1);
501
+ }
126
502
+}
127
shiftfn(rm1, rm1, constimm);
503
+
128
- rd = tcg_temp_new_i32();
504
+static void versal_virt_machine_instance_init(Object *obj)
129
narrowfn(rd, cpu_env, rm1);
505
+{
130
- neon_store_reg(a->vd, 0, rd);
506
+}
131
+ write_neon_element32(rd, a->vd, 0, MO_32);
507
+
132
508
+static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
133
shiftfn(rm2, rm2, constimm);
509
+{
134
- rd = tcg_temp_new_i32();
510
+ MachineClass *mc = MACHINE_CLASS(oc);
135
narrowfn(rd, cpu_env, rm2);
511
+
136
- neon_store_reg(a->vd, 1, rd);
512
+ mc->desc = "Xilinx Versal Virtual development board";
137
+ write_neon_element32(rd, a->vd, 1, MO_32);
513
+ mc->init = versal_virt_init;
138
514
+ mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
139
+ tcg_temp_free_i32(rd);
515
+ mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
140
tcg_temp_free_i64(rm1);
516
+ mc->no_cdrom = true;
141
tcg_temp_free_i64(rm2);
517
+}
142
tcg_temp_free_i64(constimm);
518
+
143
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
519
+static const TypeInfo versal_virt_machine_init_typeinfo = {
144
constimm = tcg_const_i32(imm);
520
+ .name = TYPE_XLNX_VERSAL_VIRT_MACHINE,
145
521
+ .parent = TYPE_MACHINE,
146
/* Load all inputs first to avoid potential overwrite */
522
+ .class_init = versal_virt_machine_class_init,
147
- rm1 = neon_load_reg(a->vm, 0);
523
+ .instance_init = versal_virt_machine_instance_init,
148
- rm2 = neon_load_reg(a->vm, 1);
524
+ .instance_size = sizeof(VersalVirt),
149
- rm3 = neon_load_reg(a->vm + 1, 0);
525
+};
150
- rm4 = neon_load_reg(a->vm + 1, 1);
526
+
151
+ rm1 = tcg_temp_new_i32();
527
+static void versal_virt_machine_init_register_types(void)
152
+ rm2 = tcg_temp_new_i32();
528
+{
153
+ rm3 = tcg_temp_new_i32();
529
+ type_register_static(&versal_virt_machine_init_typeinfo);
154
+ rm4 = tcg_temp_new_i32();
530
+}
155
+ read_neon_element32(rm1, a->vm, 0, MO_32);
531
+
156
+ read_neon_element32(rm2, a->vm, 1, MO_32);
532
+type_init(versal_virt_machine_init_register_types)
157
+ read_neon_element32(rm3, a->vm, 2, MO_32);
158
+ read_neon_element32(rm4, a->vm, 3, MO_32);
159
rtmp = tcg_temp_new_i64();
160
161
shiftfn(rm1, rm1, constimm);
162
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
163
tcg_temp_free_i32(rm2);
164
165
narrowfn(rm1, cpu_env, rtmp);
166
- neon_store_reg(a->vd, 0, rm1);
167
+ write_neon_element32(rm1, a->vd, 0, MO_32);
168
+ tcg_temp_free_i32(rm1);
169
170
shiftfn(rm3, rm3, constimm);
171
shiftfn(rm4, rm4, constimm);
172
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
173
174
narrowfn(rm3, cpu_env, rtmp);
175
tcg_temp_free_i64(rtmp);
176
- neon_store_reg(a->vd, 1, rm3);
177
+ write_neon_element32(rm3, a->vd, 1, MO_32);
178
+ tcg_temp_free_i32(rm3);
179
return true;
180
}
181
182
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
183
widen_mask = dup_const(a->size + 1, widen_mask);
184
}
185
186
- rm0 = neon_load_reg(a->vm, 0);
187
- rm1 = neon_load_reg(a->vm, 1);
188
+ rm0 = tcg_temp_new_i32();
189
+ rm1 = tcg_temp_new_i32();
190
+ read_neon_element32(rm0, a->vm, 0, MO_32);
191
+ read_neon_element32(rm1, a->vm, 1, MO_32);
192
tmp = tcg_temp_new_i64();
193
194
widenfn(tmp, rm0);
195
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
196
if (src1_wide) {
197
neon_load_reg64(rn0_64, a->vn);
198
} else {
199
- TCGv_i32 tmp = neon_load_reg(a->vn, 0);
200
+ TCGv_i32 tmp = tcg_temp_new_i32();
201
+ read_neon_element32(tmp, a->vn, 0, MO_32);
202
widenfn(rn0_64, tmp);
203
tcg_temp_free_i32(tmp);
204
}
205
- rm = neon_load_reg(a->vm, 0);
206
+ rm = tcg_temp_new_i32();
207
+ read_neon_element32(rm, a->vm, 0, MO_32);
208
209
widenfn(rm_64, rm);
210
tcg_temp_free_i32(rm);
211
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
212
if (src1_wide) {
213
neon_load_reg64(rn1_64, a->vn + 1);
214
} else {
215
- TCGv_i32 tmp = neon_load_reg(a->vn, 1);
216
+ TCGv_i32 tmp = tcg_temp_new_i32();
217
+ read_neon_element32(tmp, a->vn, 1, MO_32);
218
widenfn(rn1_64, tmp);
219
tcg_temp_free_i32(tmp);
220
}
221
- rm = neon_load_reg(a->vm, 1);
222
+ rm = tcg_temp_new_i32();
223
+ read_neon_element32(rm, a->vm, 1, MO_32);
224
225
neon_store_reg64(rn0_64, a->vd);
226
227
@@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
228
229
narrowfn(rd1, rn_64);
230
231
- neon_store_reg(a->vd, 0, rd0);
232
- neon_store_reg(a->vd, 1, rd1);
233
+ write_neon_element32(rd0, a->vd, 0, MO_32);
234
+ write_neon_element32(rd1, a->vd, 1, MO_32);
235
236
+ tcg_temp_free_i32(rd0);
237
+ tcg_temp_free_i32(rd1);
238
tcg_temp_free_i64(rn_64);
239
tcg_temp_free_i64(rm_64);
240
241
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
242
rd0 = tcg_temp_new_i64();
243
rd1 = tcg_temp_new_i64();
244
245
- rn = neon_load_reg(a->vn, 0);
246
- rm = neon_load_reg(a->vm, 0);
247
+ rn = tcg_temp_new_i32();
248
+ rm = tcg_temp_new_i32();
249
+ read_neon_element32(rn, a->vn, 0, MO_32);
250
+ read_neon_element32(rm, a->vm, 0, MO_32);
251
opfn(rd0, rn, rm);
252
- tcg_temp_free_i32(rn);
253
- tcg_temp_free_i32(rm);
254
255
- rn = neon_load_reg(a->vn, 1);
256
- rm = neon_load_reg(a->vm, 1);
257
+ read_neon_element32(rn, a->vn, 1, MO_32);
258
+ read_neon_element32(rm, a->vm, 1, MO_32);
259
opfn(rd1, rn, rm);
260
tcg_temp_free_i32(rn);
261
tcg_temp_free_i32(rm);
262
@@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var)
263
264
static inline TCGv_i32 neon_get_scalar(int size, int reg)
265
{
266
- TCGv_i32 tmp;
267
- if (size == 1) {
268
- tmp = neon_load_reg(reg & 7, reg >> 4);
269
+ TCGv_i32 tmp = tcg_temp_new_i32();
270
+ if (size == MO_16) {
271
+ read_neon_element32(tmp, reg & 7, reg >> 4, MO_32);
272
if (reg & 8) {
273
gen_neon_dup_high16(tmp);
274
} else {
275
gen_neon_dup_low16(tmp);
276
}
277
} else {
278
- tmp = neon_load_reg(reg & 15, reg >> 4);
279
+ read_neon_element32(tmp, reg & 15, reg >> 4, MO_32);
280
}
281
return tmp;
282
}
283
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a,
284
* perform an accumulation operation of that result into the
285
* destination.
286
*/
287
- TCGv_i32 scalar;
288
+ TCGv_i32 scalar, tmp;
289
int pass;
290
291
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
292
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a,
293
}
294
295
scalar = neon_get_scalar(a->size, a->vm);
296
+ tmp = tcg_temp_new_i32();
297
298
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
299
- TCGv_i32 tmp = neon_load_reg(a->vn, pass);
300
+ read_neon_element32(tmp, a->vn, pass, MO_32);
301
opfn(tmp, tmp, scalar);
302
if (accfn) {
303
- TCGv_i32 rd = neon_load_reg(a->vd, pass);
304
+ TCGv_i32 rd = tcg_temp_new_i32();
305
+ read_neon_element32(rd, a->vd, pass, MO_32);
306
accfn(tmp, rd, tmp);
307
tcg_temp_free_i32(rd);
308
}
309
- neon_store_reg(a->vd, pass, tmp);
310
+ write_neon_element32(tmp, a->vd, pass, MO_32);
311
}
312
+ tcg_temp_free_i32(tmp);
313
tcg_temp_free_i32(scalar);
314
return true;
315
}
316
@@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
317
* performs a kind of fused op-then-accumulate using a helper
318
* function that takes all of rd, rn and the scalar at once.
319
*/
320
- TCGv_i32 scalar;
321
+ TCGv_i32 scalar, rn, rd;
322
int pass;
323
324
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
325
@@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
326
}
327
328
scalar = neon_get_scalar(a->size, a->vm);
329
+ rn = tcg_temp_new_i32();
330
+ rd = tcg_temp_new_i32();
331
332
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
333
- TCGv_i32 rn = neon_load_reg(a->vn, pass);
334
- TCGv_i32 rd = neon_load_reg(a->vd, pass);
335
+ read_neon_element32(rn, a->vn, pass, MO_32);
336
+ read_neon_element32(rd, a->vd, pass, MO_32);
337
opfn(rd, cpu_env, rn, scalar, rd);
338
- tcg_temp_free_i32(rn);
339
- neon_store_reg(a->vd, pass, rd);
340
+ write_neon_element32(rd, a->vd, pass, MO_32);
341
}
342
+ tcg_temp_free_i32(rn);
343
+ tcg_temp_free_i32(rd);
344
tcg_temp_free_i32(scalar);
345
346
return true;
347
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
348
scalar = neon_get_scalar(a->size, a->vm);
349
350
/* Load all inputs before writing any outputs, in case of overlap */
351
- rn = neon_load_reg(a->vn, 0);
352
+ rn = tcg_temp_new_i32();
353
+ read_neon_element32(rn, a->vn, 0, MO_32);
354
rn0_64 = tcg_temp_new_i64();
355
opfn(rn0_64, rn, scalar);
356
- tcg_temp_free_i32(rn);
357
358
- rn = neon_load_reg(a->vn, 1);
359
+ read_neon_element32(rn, a->vn, 1, MO_32);
360
rn1_64 = tcg_temp_new_i64();
361
opfn(rn1_64, rn, scalar);
362
tcg_temp_free_i32(rn);
363
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
364
return false;
365
}
366
n <<= 3;
367
+ tmp = tcg_temp_new_i32();
368
if (a->op) {
369
- tmp = neon_load_reg(a->vd, 0);
370
+ read_neon_element32(tmp, a->vd, 0, MO_32);
371
} else {
372
- tmp = tcg_temp_new_i32();
373
tcg_gen_movi_i32(tmp, 0);
374
}
375
- tmp2 = neon_load_reg(a->vm, 0);
376
+ tmp2 = tcg_temp_new_i32();
377
+ read_neon_element32(tmp2, a->vm, 0, MO_32);
378
ptr1 = vfp_reg_ptr(true, a->vn);
379
tmp4 = tcg_const_i32(n);
380
gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
381
- tcg_temp_free_i32(tmp);
382
+
383
if (a->op) {
384
- tmp = neon_load_reg(a->vd, 1);
385
+ read_neon_element32(tmp, a->vd, 1, MO_32);
386
} else {
387
- tmp = tcg_temp_new_i32();
388
tcg_gen_movi_i32(tmp, 0);
389
}
390
- tmp3 = neon_load_reg(a->vm, 1);
391
+ tmp3 = tcg_temp_new_i32();
392
+ read_neon_element32(tmp3, a->vm, 1, MO_32);
393
gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
394
+ tcg_temp_free_i32(tmp);
395
tcg_temp_free_i32(tmp4);
396
tcg_temp_free_ptr(ptr1);
397
- neon_store_reg(a->vd, 0, tmp2);
398
- neon_store_reg(a->vd, 1, tmp3);
399
- tcg_temp_free_i32(tmp);
400
+
401
+ write_neon_element32(tmp2, a->vd, 0, MO_32);
402
+ write_neon_element32(tmp3, a->vd, 1, MO_32);
403
+ tcg_temp_free_i32(tmp2);
404
+ tcg_temp_free_i32(tmp3);
405
return true;
406
}
407
408
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
409
static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
410
{
411
int pass, half;
412
+ TCGv_i32 tmp[2];
413
414
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
415
return false;
416
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
417
return true;
418
}
419
420
- for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
421
- TCGv_i32 tmp[2];
422
+ tmp[0] = tcg_temp_new_i32();
423
+ tmp[1] = tcg_temp_new_i32();
424
425
+ for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
426
for (half = 0; half < 2; half++) {
427
- tmp[half] = neon_load_reg(a->vm, pass * 2 + half);
428
+ read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32);
429
switch (a->size) {
430
case 0:
431
tcg_gen_bswap32_i32(tmp[half], tmp[half]);
432
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
433
g_assert_not_reached();
434
}
435
}
436
- neon_store_reg(a->vd, pass * 2, tmp[1]);
437
- neon_store_reg(a->vd, pass * 2 + 1, tmp[0]);
438
+ write_neon_element32(tmp[1], a->vd, pass * 2, MO_32);
439
+ write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32);
440
}
441
+
442
+ tcg_temp_free_i32(tmp[0]);
443
+ tcg_temp_free_i32(tmp[1]);
444
return true;
445
}
446
447
@@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
448
rm0_64 = tcg_temp_new_i64();
449
rm1_64 = tcg_temp_new_i64();
450
rd_64 = tcg_temp_new_i64();
451
- tmp = neon_load_reg(a->vm, pass * 2);
452
+
453
+ tmp = tcg_temp_new_i32();
454
+ read_neon_element32(tmp, a->vm, pass * 2, MO_32);
455
widenfn(rm0_64, tmp);
456
- tcg_temp_free_i32(tmp);
457
- tmp = neon_load_reg(a->vm, pass * 2 + 1);
458
+ read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32);
459
widenfn(rm1_64, tmp);
460
tcg_temp_free_i32(tmp);
461
+
462
opfn(rd_64, rm0_64, rm1_64);
463
tcg_temp_free_i64(rm0_64);
464
tcg_temp_free_i64(rm1_64);
465
@@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
466
narrowfn(rd0, cpu_env, rm);
467
neon_load_reg64(rm, a->vm + 1);
468
narrowfn(rd1, cpu_env, rm);
469
- neon_store_reg(a->vd, 0, rd0);
470
- neon_store_reg(a->vd, 1, rd1);
471
+ write_neon_element32(rd0, a->vd, 0, MO_32);
472
+ write_neon_element32(rd1, a->vd, 1, MO_32);
473
+ tcg_temp_free_i32(rd0);
474
+ tcg_temp_free_i32(rd1);
475
tcg_temp_free_i64(rm);
476
return true;
477
}
478
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
479
}
480
481
rd = tcg_temp_new_i64();
482
+ rm0 = tcg_temp_new_i32();
483
+ rm1 = tcg_temp_new_i32();
484
485
- rm0 = neon_load_reg(a->vm, 0);
486
- rm1 = neon_load_reg(a->vm, 1);
487
+ read_neon_element32(rm0, a->vm, 0, MO_32);
488
+ read_neon_element32(rm1, a->vm, 1, MO_32);
489
490
widenfn(rd, rm0);
491
tcg_gen_shli_i64(rd, rd, 8 << a->size);
492
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a)
493
494
fpst = fpstatus_ptr(FPST_STD);
495
ahp = get_ahp_flag();
496
- tmp = neon_load_reg(a->vm, 0);
497
+ tmp = tcg_temp_new_i32();
498
+ read_neon_element32(tmp, a->vm, 0, MO_32);
499
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
500
- tmp2 = neon_load_reg(a->vm, 1);
501
+ tmp2 = tcg_temp_new_i32();
502
+ read_neon_element32(tmp2, a->vm, 1, MO_32);
503
gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
504
tcg_gen_shli_i32(tmp2, tmp2, 16);
505
tcg_gen_or_i32(tmp2, tmp2, tmp);
506
- tcg_temp_free_i32(tmp);
507
- tmp = neon_load_reg(a->vm, 2);
508
+ read_neon_element32(tmp, a->vm, 2, MO_32);
509
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
510
- tmp3 = neon_load_reg(a->vm, 3);
511
- neon_store_reg(a->vd, 0, tmp2);
512
+ tmp3 = tcg_temp_new_i32();
513
+ read_neon_element32(tmp3, a->vm, 3, MO_32);
514
+ write_neon_element32(tmp2, a->vd, 0, MO_32);
515
+ tcg_temp_free_i32(tmp2);
516
gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
517
tcg_gen_shli_i32(tmp3, tmp3, 16);
518
tcg_gen_or_i32(tmp3, tmp3, tmp);
519
- neon_store_reg(a->vd, 1, tmp3);
520
+ write_neon_element32(tmp3, a->vd, 1, MO_32);
521
+ tcg_temp_free_i32(tmp3);
522
tcg_temp_free_i32(tmp);
523
tcg_temp_free_i32(ahp);
524
tcg_temp_free_ptr(fpst);
525
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
526
fpst = fpstatus_ptr(FPST_STD);
527
ahp = get_ahp_flag();
528
tmp3 = tcg_temp_new_i32();
529
- tmp = neon_load_reg(a->vm, 0);
530
- tmp2 = neon_load_reg(a->vm, 1);
531
+ tmp2 = tcg_temp_new_i32();
532
+ tmp = tcg_temp_new_i32();
533
+ read_neon_element32(tmp, a->vm, 0, MO_32);
534
+ read_neon_element32(tmp2, a->vm, 1, MO_32);
535
tcg_gen_ext16u_i32(tmp3, tmp);
536
gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
537
- neon_store_reg(a->vd, 0, tmp3);
538
+ write_neon_element32(tmp3, a->vd, 0, MO_32);
539
tcg_gen_shri_i32(tmp, tmp, 16);
540
gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
541
- neon_store_reg(a->vd, 1, tmp);
542
- tmp3 = tcg_temp_new_i32();
543
+ write_neon_element32(tmp, a->vd, 1, MO_32);
544
+ tcg_temp_free_i32(tmp);
545
tcg_gen_ext16u_i32(tmp3, tmp2);
546
gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
547
- neon_store_reg(a->vd, 2, tmp3);
548
+ write_neon_element32(tmp3, a->vd, 2, MO_32);
549
+ tcg_temp_free_i32(tmp3);
550
tcg_gen_shri_i32(tmp2, tmp2, 16);
551
gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
552
- neon_store_reg(a->vd, 3, tmp2);
553
+ write_neon_element32(tmp2, a->vd, 3, MO_32);
554
+ tcg_temp_free_i32(tmp2);
555
tcg_temp_free_i32(ahp);
556
tcg_temp_free_ptr(fpst);
557
558
@@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
559
560
static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
561
{
562
+ TCGv_i32 tmp;
563
int pass;
564
565
/* Handle a 2-reg-misc operation by iterating 32 bits at a time */
566
@@ -XXX,XX +XXX,XX @@ static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
567
return true;
568
}
569
570
+ tmp = tcg_temp_new_i32();
571
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
572
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
573
+ read_neon_element32(tmp, a->vm, pass, MO_32);
574
fn(tmp, tmp);
575
- neon_store_reg(a->vd, pass, tmp);
576
+ write_neon_element32(tmp, a->vd, pass, MO_32);
577
}
578
+ tcg_temp_free_i32(tmp);
579
580
return true;
581
}
582
@@ -XXX,XX +XXX,XX @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a)
583
return true;
584
}
585
586
- if (a->size == 2) {
587
+ tmp = tcg_temp_new_i32();
588
+ tmp2 = tcg_temp_new_i32();
589
+ if (a->size == MO_32) {
590
for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
591
- tmp = neon_load_reg(a->vm, pass);
592
- tmp2 = neon_load_reg(a->vd, pass + 1);
593
- neon_store_reg(a->vm, pass, tmp2);
594
- neon_store_reg(a->vd, pass + 1, tmp);
595
+ read_neon_element32(tmp, a->vm, pass, MO_32);
596
+ read_neon_element32(tmp2, a->vd, pass + 1, MO_32);
597
+ write_neon_element32(tmp2, a->vm, pass, MO_32);
598
+ write_neon_element32(tmp, a->vd, pass + 1, MO_32);
599
}
600
} else {
601
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
602
- tmp = neon_load_reg(a->vm, pass);
603
- tmp2 = neon_load_reg(a->vd, pass);
604
- if (a->size == 0) {
605
+ read_neon_element32(tmp, a->vm, pass, MO_32);
606
+ read_neon_element32(tmp2, a->vd, pass, MO_32);
607
+ if (a->size == MO_8) {
608
gen_neon_trn_u8(tmp, tmp2);
609
} else {
610
gen_neon_trn_u16(tmp, tmp2);
611
}
612
- neon_store_reg(a->vm, pass, tmp2);
613
- neon_store_reg(a->vd, pass, tmp);
614
+ write_neon_element32(tmp2, a->vm, pass, MO_32);
615
+ write_neon_element32(tmp, a->vd, pass, MO_32);
616
}
617
}
618
+ tcg_temp_free_i32(tmp);
619
+ tcg_temp_free_i32(tmp2);
620
return true;
621
}
533
--
622
--
534
2.19.1
623
2.20.1
535
624
536
625
diff view generated by jsdifflib
New patch
[PULL 06/26] target/arm: Expand read/write_neon_element32 to all MemOp
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
We can then use this to improve VMOV (scalar to gp) and
4
VMOV (gp to scalar) so that we simply perform the memory
5
operation that we wanted, rather than inserting or
6
extracting from a 32-bit quantity.
7
8
These were the last uses of neon_load/store_reg, so remove them.
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20201030022618.785675-7-richard.henderson@linaro.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/translate.c | 50 +++++++++++++-----------
16
target/arm/translate-vfp.c.inc | 71 +++++-----------------------------
17
2 files changed, 37 insertions(+), 84 deletions(-)
18
19
diff --git a/target/arm/translate.c b/target/arm/translate.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate.c
22
+++ b/target/arm/translate.c
23
@@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg)
24
* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
25
* where 0 is the least significant end of the register.
26
*/
27
-static long neon_element_offset(int reg, int element, MemOp size)
28
+static long neon_element_offset(int reg, int element, MemOp memop)
29
{
30
- int element_size = 1 << size;
31
+ int element_size = 1 << (memop & MO_SIZE);
32
int ofs = element * element_size;
33
#ifdef HOST_WORDS_BIGENDIAN
34
/*
35
@@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg)
36
}
37
}
38
39
-static TCGv_i32 neon_load_reg(int reg, int pass)
40
-{
41
- TCGv_i32 tmp = tcg_temp_new_i32();
42
- tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
43
- return tmp;
44
-}
45
-
46
-static void neon_store_reg(int reg, int pass, TCGv_i32 var)
47
-{
48
- tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
49
- tcg_temp_free_i32(var);
50
-}
51
-
52
static inline void neon_load_reg64(TCGv_i64 var, int reg)
53
{
54
tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
55
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)
56
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
57
}
58
59
-static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
60
+static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
61
{
62
- long off = neon_element_offset(reg, ele, size);
63
+ long off = neon_element_offset(reg, ele, memop);
64
65
- switch (size) {
66
- case MO_32:
67
+ switch (memop) {
68
+ case MO_SB:
69
+ tcg_gen_ld8s_i32(dest, cpu_env, off);
70
+ break;
71
+ case MO_UB:
72
+ tcg_gen_ld8u_i32(dest, cpu_env, off);
73
+ break;
74
+ case MO_SW:
75
+ tcg_gen_ld16s_i32(dest, cpu_env, off);
76
+ break;
77
+ case MO_UW:
78
+ tcg_gen_ld16u_i32(dest, cpu_env, off);
79
+ break;
80
+ case MO_UL:
81
+ case MO_SL:
82
tcg_gen_ld_i32(dest, cpu_env, off);
83
break;
84
default:
85
@@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
86
}
87
}
88
89
-static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)
90
+static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
91
{
92
- long off = neon_element_offset(reg, ele, size);
93
+ long off = neon_element_offset(reg, ele, memop);
94
95
- switch (size) {
96
+ switch (memop) {
97
+ case MO_8:
98
+ tcg_gen_st8_i32(src, cpu_env, off);
99
+ break;
100
+ case MO_16:
101
+ tcg_gen_st16_i32(src, cpu_env, off);
102
+ break;
103
case MO_32:
104
tcg_gen_st_i32(src, cpu_env, off);
105
break;
106
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-vfp.c.inc
109
+++ b/target/arm/translate-vfp.c.inc
110
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
111
{
112
/* VMOV scalar to general purpose register */
113
TCGv_i32 tmp;
114
- int pass;
115
- uint32_t offset;
116
117
- /* SIZE == 2 is a VFP instruction; otherwise NEON. */
118
- if (a->size == 2
119
+ /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */
120
+ if (a->size == MO_32
121
? !dc_isar_feature(aa32_fpsp_v2, s)
122
: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
123
return false;
124
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
125
return false;
126
}
127
128
- offset = a->index << a->size;
129
- pass = extract32(offset, 2, 1);
130
- offset = extract32(offset, 0, 2) * 8;
131
-
132
if (!vfp_access_check(s)) {
133
return true;
134
}
135
136
- tmp = neon_load_reg(a->vn, pass);
137
- switch (a->size) {
138
- case 0:
139
- if (offset) {
140
- tcg_gen_shri_i32(tmp, tmp, offset);
141
- }
142
- if (a->u) {
143
- gen_uxtb(tmp);
144
- } else {
145
- gen_sxtb(tmp);
146
- }
147
- break;
148
- case 1:
149
- if (a->u) {
150
- if (offset) {
151
- tcg_gen_shri_i32(tmp, tmp, 16);
152
- } else {
153
- gen_uxth(tmp);
154
- }
155
- } else {
156
- if (offset) {
157
- tcg_gen_sari_i32(tmp, tmp, 16);
158
- } else {
159
- gen_sxth(tmp);
160
- }
161
- }
162
- break;
163
- case 2:
164
- break;
165
- }
166
+ tmp = tcg_temp_new_i32();
167
+ read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN));
168
store_reg(s, a->rt, tmp);
169
170
return true;
171
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
172
static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
173
{
174
/* VMOV general purpose register to scalar */
175
- TCGv_i32 tmp, tmp2;
176
- int pass;
177
- uint32_t offset;
178
+ TCGv_i32 tmp;
179
180
- /* SIZE == 2 is a VFP instruction; otherwise NEON. */
181
- if (a->size == 2
182
+ /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */
183
+ if (a->size == MO_32
184
? !dc_isar_feature(aa32_fpsp_v2, s)
185
: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
186
return false;
187
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
188
return false;
189
}
190
191
- offset = a->index << a->size;
192
- pass = extract32(offset, 2, 1);
193
- offset = extract32(offset, 0, 2) * 8;
194
-
195
if (!vfp_access_check(s)) {
196
return true;
197
}
198
199
tmp = load_reg(s, a->rt);
200
- switch (a->size) {
201
- case 0:
202
- tmp2 = neon_load_reg(a->vn, pass);
203
- tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
204
- tcg_temp_free_i32(tmp2);
205
- break;
206
- case 1:
207
- tmp2 = neon_load_reg(a->vn, pass);
208
- tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
209
- tcg_temp_free_i32(tmp2);
210
- break;
211
- case 2:
212
- break;
213
- }
214
- neon_store_reg(a->vn, pass, tmp);
215
+ write_neon_element32(tmp, a->vn, a->index, a->size);
216
+ tcg_temp_free_i32(tmp);
217
218
return true;
219
}
220
--
221
2.20.1
222
223
diff view generated by jsdifflib
New patch
[PULL 07/26] target/arm: Rename neon_load_reg32 to vfp_load_reg32
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The only uses of this function are for loading VFP
4
single-precision values, and nothing to do with NEON.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201030022618.785675-8-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate.c | 4 +-
12
target/arm/translate-vfp.c.inc | 184 ++++++++++++++++-----------------
13
2 files changed, 94 insertions(+), 94 deletions(-)
14
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
18
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg64(TCGv_i64 var, int reg)
20
tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
21
}
22
23
-static inline void neon_load_reg32(TCGv_i32 var, int reg)
24
+static inline void vfp_load_reg32(TCGv_i32 var, int reg)
25
{
26
tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
27
}
28
29
-static inline void neon_store_reg32(TCGv_i32 var, int reg)
30
+static inline void vfp_store_reg32(TCGv_i32 var, int reg)
31
{
32
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
33
}
34
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/translate-vfp.c.inc
37
+++ b/target/arm/translate-vfp.c.inc
38
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
39
frn = tcg_temp_new_i32();
40
frm = tcg_temp_new_i32();
41
dest = tcg_temp_new_i32();
42
- neon_load_reg32(frn, rn);
43
- neon_load_reg32(frm, rm);
44
+ vfp_load_reg32(frn, rn);
45
+ vfp_load_reg32(frm, rm);
46
switch (a->cc) {
47
case 0: /* eq: Z */
48
tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
49
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
50
if (sz == 1) {
51
tcg_gen_andi_i32(dest, dest, 0xffff);
52
}
53
- neon_store_reg32(dest, rd);
54
+ vfp_store_reg32(dest, rd);
55
tcg_temp_free_i32(frn);
56
tcg_temp_free_i32(frm);
57
tcg_temp_free_i32(dest);
58
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
59
TCGv_i32 tcg_res;
60
tcg_op = tcg_temp_new_i32();
61
tcg_res = tcg_temp_new_i32();
62
- neon_load_reg32(tcg_op, rm);
63
+ vfp_load_reg32(tcg_op, rm);
64
if (sz == 1) {
65
gen_helper_rinth(tcg_res, tcg_op, fpst);
66
} else {
67
gen_helper_rints(tcg_res, tcg_op, fpst);
68
}
69
- neon_store_reg32(tcg_res, rd);
70
+ vfp_store_reg32(tcg_res, rd);
71
tcg_temp_free_i32(tcg_op);
72
tcg_temp_free_i32(tcg_res);
73
}
74
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
75
gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst);
76
}
77
tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res);
78
- neon_store_reg32(tcg_tmp, rd);
79
+ vfp_store_reg32(tcg_tmp, rd);
80
tcg_temp_free_i32(tcg_tmp);
81
tcg_temp_free_i64(tcg_res);
82
tcg_temp_free_i64(tcg_double);
83
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
84
TCGv_i32 tcg_single, tcg_res;
85
tcg_single = tcg_temp_new_i32();
86
tcg_res = tcg_temp_new_i32();
87
- neon_load_reg32(tcg_single, rm);
88
+ vfp_load_reg32(tcg_single, rm);
89
if (sz == 1) {
90
if (is_signed) {
91
gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst);
92
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
93
gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
94
}
95
}
96
- neon_store_reg32(tcg_res, rd);
97
+ vfp_store_reg32(tcg_res, rd);
98
tcg_temp_free_i32(tcg_res);
99
tcg_temp_free_i32(tcg_single);
100
}
101
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
102
if (a->l) {
103
/* VFP to general purpose register */
104
tmp = tcg_temp_new_i32();
105
- neon_load_reg32(tmp, a->vn);
106
+ vfp_load_reg32(tmp, a->vn);
107
tcg_gen_andi_i32(tmp, tmp, 0xffff);
108
store_reg(s, a->rt, tmp);
109
} else {
110
/* general purpose register to VFP */
111
tmp = load_reg(s, a->rt);
112
tcg_gen_andi_i32(tmp, tmp, 0xffff);
113
- neon_store_reg32(tmp, a->vn);
114
+ vfp_store_reg32(tmp, a->vn);
115
tcg_temp_free_i32(tmp);
116
}
117
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
119
if (a->l) {
120
/* VFP to general purpose register */
121
tmp = tcg_temp_new_i32();
122
- neon_load_reg32(tmp, a->vn);
123
+ vfp_load_reg32(tmp, a->vn);
124
if (a->rt == 15) {
125
/* Set the 4 flag bits in the CPSR. */
126
gen_set_nzcv(tmp);
127
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
128
} else {
129
/* general purpose register to VFP */
130
tmp = load_reg(s, a->rt);
131
- neon_store_reg32(tmp, a->vn);
132
+ vfp_store_reg32(tmp, a->vn);
133
tcg_temp_free_i32(tmp);
134
}
135
136
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
137
if (a->op) {
138
/* fpreg to gpreg */
139
tmp = tcg_temp_new_i32();
140
- neon_load_reg32(tmp, a->vm);
141
+ vfp_load_reg32(tmp, a->vm);
142
store_reg(s, a->rt, tmp);
143
tmp = tcg_temp_new_i32();
144
- neon_load_reg32(tmp, a->vm + 1);
145
+ vfp_load_reg32(tmp, a->vm + 1);
146
store_reg(s, a->rt2, tmp);
147
} else {
148
/* gpreg to fpreg */
149
tmp = load_reg(s, a->rt);
150
- neon_store_reg32(tmp, a->vm);
151
+ vfp_store_reg32(tmp, a->vm);
152
tcg_temp_free_i32(tmp);
153
tmp = load_reg(s, a->rt2);
154
- neon_store_reg32(tmp, a->vm + 1);
155
+ vfp_store_reg32(tmp, a->vm + 1);
156
tcg_temp_free_i32(tmp);
157
}
158
159
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
160
if (a->op) {
161
/* fpreg to gpreg */
162
tmp = tcg_temp_new_i32();
163
- neon_load_reg32(tmp, a->vm * 2);
164
+ vfp_load_reg32(tmp, a->vm * 2);
165
store_reg(s, a->rt, tmp);
166
tmp = tcg_temp_new_i32();
167
- neon_load_reg32(tmp, a->vm * 2 + 1);
168
+ vfp_load_reg32(tmp, a->vm * 2 + 1);
169
store_reg(s, a->rt2, tmp);
170
} else {
171
/* gpreg to fpreg */
172
tmp = load_reg(s, a->rt);
173
- neon_store_reg32(tmp, a->vm * 2);
174
+ vfp_store_reg32(tmp, a->vm * 2);
175
tcg_temp_free_i32(tmp);
176
tmp = load_reg(s, a->rt2);
177
- neon_store_reg32(tmp, a->vm * 2 + 1);
178
+ vfp_store_reg32(tmp, a->vm * 2 + 1);
179
tcg_temp_free_i32(tmp);
180
}
181
182
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a)
183
tmp = tcg_temp_new_i32();
184
if (a->l) {
185
gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
186
- neon_store_reg32(tmp, a->vd);
187
+ vfp_store_reg32(tmp, a->vd);
188
} else {
189
- neon_load_reg32(tmp, a->vd);
190
+ vfp_load_reg32(tmp, a->vd);
191
gen_aa32_st16(s, tmp, addr, get_mem_index(s));
192
}
193
tcg_temp_free_i32(tmp);
194
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
195
tmp = tcg_temp_new_i32();
196
if (a->l) {
197
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
198
- neon_store_reg32(tmp, a->vd);
199
+ vfp_store_reg32(tmp, a->vd);
200
} else {
201
- neon_load_reg32(tmp, a->vd);
202
+ vfp_load_reg32(tmp, a->vd);
203
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
204
}
205
tcg_temp_free_i32(tmp);
206
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
207
if (a->l) {
208
/* load */
209
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
210
- neon_store_reg32(tmp, a->vd + i);
211
+ vfp_store_reg32(tmp, a->vd + i);
212
} else {
213
/* store */
214
- neon_load_reg32(tmp, a->vd + i);
215
+ vfp_load_reg32(tmp, a->vd + i);
216
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
217
}
218
tcg_gen_addi_i32(addr, addr, offset);
219
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
220
fd = tcg_temp_new_i32();
221
fpst = fpstatus_ptr(FPST_FPCR);
222
223
- neon_load_reg32(f0, vn);
224
- neon_load_reg32(f1, vm);
225
+ vfp_load_reg32(f0, vn);
226
+ vfp_load_reg32(f1, vm);
227
228
for (;;) {
229
if (reads_vd) {
230
- neon_load_reg32(fd, vd);
231
+ vfp_load_reg32(fd, vd);
232
}
233
fn(fd, f0, f1, fpst);
234
- neon_store_reg32(fd, vd);
235
+ vfp_store_reg32(fd, vd);
236
237
if (veclen == 0) {
238
break;
239
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
240
veclen--;
241
vd = vfp_advance_sreg(vd, delta_d);
242
vn = vfp_advance_sreg(vn, delta_d);
243
- neon_load_reg32(f0, vn);
244
+ vfp_load_reg32(f0, vn);
245
if (delta_m) {
246
vm = vfp_advance_sreg(vm, delta_m);
247
- neon_load_reg32(f1, vm);
248
+ vfp_load_reg32(f1, vm);
249
}
250
}
251
252
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn,
253
fd = tcg_temp_new_i32();
254
fpst = fpstatus_ptr(FPST_FPCR_F16);
255
256
- neon_load_reg32(f0, vn);
257
- neon_load_reg32(f1, vm);
258
+ vfp_load_reg32(f0, vn);
259
+ vfp_load_reg32(f1, vm);
260
261
if (reads_vd) {
262
- neon_load_reg32(fd, vd);
263
+ vfp_load_reg32(fd, vd);
264
}
265
fn(fd, f0, f1, fpst);
266
- neon_store_reg32(fd, vd);
267
+ vfp_store_reg32(fd, vd);
268
269
tcg_temp_free_i32(f0);
270
tcg_temp_free_i32(f1);
271
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
272
f0 = tcg_temp_new_i32();
273
fd = tcg_temp_new_i32();
274
275
- neon_load_reg32(f0, vm);
276
+ vfp_load_reg32(f0, vm);
277
278
for (;;) {
279
fn(fd, f0);
280
- neon_store_reg32(fd, vd);
281
+ vfp_store_reg32(fd, vd);
282
283
if (veclen == 0) {
284
break;
285
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
286
/* single source one-many */
287
while (veclen--) {
288
vd = vfp_advance_sreg(vd, delta_d);
289
- neon_store_reg32(fd, vd);
290
+ vfp_store_reg32(fd, vd);
291
}
292
break;
293
}
294
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
295
veclen--;
296
vd = vfp_advance_sreg(vd, delta_d);
297
vm = vfp_advance_sreg(vm, delta_m);
298
- neon_load_reg32(f0, vm);
299
+ vfp_load_reg32(f0, vm);
300
}
301
302
tcg_temp_free_i32(f0);
303
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
304
}
305
306
f0 = tcg_temp_new_i32();
307
- neon_load_reg32(f0, vm);
308
+ vfp_load_reg32(f0, vm);
309
fn(f0, f0);
310
- neon_store_reg32(f0, vd);
311
+ vfp_store_reg32(f0, vd);
312
tcg_temp_free_i32(f0);
313
314
return true;
315
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
316
vm = tcg_temp_new_i32();
317
vd = tcg_temp_new_i32();
318
319
- neon_load_reg32(vn, a->vn);
320
- neon_load_reg32(vm, a->vm);
321
+ vfp_load_reg32(vn, a->vn);
322
+ vfp_load_reg32(vm, a->vm);
323
if (neg_n) {
324
/* VFNMS, VFMS */
325
gen_helper_vfp_negh(vn, vn);
326
}
327
- neon_load_reg32(vd, a->vd);
328
+ vfp_load_reg32(vd, a->vd);
329
if (neg_d) {
330
/* VFNMA, VFNMS */
331
gen_helper_vfp_negh(vd, vd);
332
}
333
fpst = fpstatus_ptr(FPST_FPCR_F16);
334
gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst);
335
- neon_store_reg32(vd, a->vd);
336
+ vfp_store_reg32(vd, a->vd);
337
338
tcg_temp_free_ptr(fpst);
339
tcg_temp_free_i32(vn);
340
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
341
vm = tcg_temp_new_i32();
342
vd = tcg_temp_new_i32();
343
344
- neon_load_reg32(vn, a->vn);
345
- neon_load_reg32(vm, a->vm);
346
+ vfp_load_reg32(vn, a->vn);
347
+ vfp_load_reg32(vm, a->vm);
348
if (neg_n) {
349
/* VFNMS, VFMS */
350
gen_helper_vfp_negs(vn, vn);
351
}
352
- neon_load_reg32(vd, a->vd);
353
+ vfp_load_reg32(vd, a->vd);
354
if (neg_d) {
355
/* VFNMA, VFNMS */
356
gen_helper_vfp_negs(vd, vd);
357
}
358
fpst = fpstatus_ptr(FPST_FPCR);
359
gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
360
- neon_store_reg32(vd, a->vd);
361
+ vfp_store_reg32(vd, a->vd);
362
363
tcg_temp_free_ptr(fpst);
364
tcg_temp_free_i32(vn);
365
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a)
366
}
367
368
fd = tcg_const_i32(vfp_expand_imm(MO_16, a->imm));
369
- neon_store_reg32(fd, a->vd);
370
+ vfp_store_reg32(fd, a->vd);
371
tcg_temp_free_i32(fd);
372
return true;
373
}
374
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
375
fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
376
377
for (;;) {
378
- neon_store_reg32(fd, vd);
379
+ vfp_store_reg32(fd, vd);
380
381
if (veclen == 0) {
382
break;
383
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a)
384
vd = tcg_temp_new_i32();
385
vm = tcg_temp_new_i32();
386
387
- neon_load_reg32(vd, a->vd);
388
+ vfp_load_reg32(vd, a->vd);
389
if (a->z) {
390
tcg_gen_movi_i32(vm, 0);
391
} else {
392
- neon_load_reg32(vm, a->vm);
393
+ vfp_load_reg32(vm, a->vm);
394
}
395
396
if (a->e) {
397
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
398
vd = tcg_temp_new_i32();
399
vm = tcg_temp_new_i32();
400
401
- neon_load_reg32(vd, a->vd);
402
+ vfp_load_reg32(vd, a->vd);
403
if (a->z) {
404
tcg_gen_movi_i32(vm, 0);
405
} else {
406
- neon_load_reg32(vm, a->vm);
407
+ vfp_load_reg32(vm, a->vm);
408
}
409
410
if (a->e) {
411
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
412
/* The T bit tells us if we want the low or high 16 bits of Vm */
413
tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
414
gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
415
- neon_store_reg32(tmp, a->vd);
416
+ vfp_store_reg32(tmp, a->vd);
417
tcg_temp_free_i32(ahp_mode);
418
tcg_temp_free_ptr(fpst);
419
tcg_temp_free_i32(tmp);
420
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
421
ahp_mode = get_ahp_flag();
422
tmp = tcg_temp_new_i32();
423
424
- neon_load_reg32(tmp, a->vm);
425
+ vfp_load_reg32(tmp, a->vm);
426
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
427
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
428
tcg_temp_free_i32(ahp_mode);
429
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a)
430
}
431
432
tmp = tcg_temp_new_i32();
433
- neon_load_reg32(tmp, a->vm);
434
+ vfp_load_reg32(tmp, a->vm);
435
fpst = fpstatus_ptr(FPST_FPCR_F16);
436
gen_helper_rinth(tmp, tmp, fpst);
437
- neon_store_reg32(tmp, a->vd);
438
+ vfp_store_reg32(tmp, a->vd);
439
tcg_temp_free_ptr(fpst);
440
tcg_temp_free_i32(tmp);
441
return true;
442
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
443
}
444
445
tmp = tcg_temp_new_i32();
446
- neon_load_reg32(tmp, a->vm);
447
+ vfp_load_reg32(tmp, a->vm);
448
fpst = fpstatus_ptr(FPST_FPCR);
449
gen_helper_rints(tmp, tmp, fpst);
450
- neon_store_reg32(tmp, a->vd);
451
+ vfp_store_reg32(tmp, a->vd);
452
tcg_temp_free_ptr(fpst);
453
tcg_temp_free_i32(tmp);
454
return true;
455
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
456
}
457
458
tmp = tcg_temp_new_i32();
459
- neon_load_reg32(tmp, a->vm);
460
+ vfp_load_reg32(tmp, a->vm);
461
fpst = fpstatus_ptr(FPST_FPCR_F16);
462
tcg_rmode = tcg_const_i32(float_round_to_zero);
463
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
464
gen_helper_rinth(tmp, tmp, fpst);
465
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
466
- neon_store_reg32(tmp, a->vd);
467
+ vfp_store_reg32(tmp, a->vd);
468
tcg_temp_free_ptr(fpst);
469
tcg_temp_free_i32(tcg_rmode);
470
tcg_temp_free_i32(tmp);
471
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
472
}
473
474
tmp = tcg_temp_new_i32();
475
- neon_load_reg32(tmp, a->vm);
476
+ vfp_load_reg32(tmp, a->vm);
477
fpst = fpstatus_ptr(FPST_FPCR);
478
tcg_rmode = tcg_const_i32(float_round_to_zero);
479
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
480
gen_helper_rints(tmp, tmp, fpst);
481
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
482
- neon_store_reg32(tmp, a->vd);
483
+ vfp_store_reg32(tmp, a->vd);
484
tcg_temp_free_ptr(fpst);
485
tcg_temp_free_i32(tcg_rmode);
486
tcg_temp_free_i32(tmp);
487
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a)
488
}
489
490
tmp = tcg_temp_new_i32();
491
- neon_load_reg32(tmp, a->vm);
492
+ vfp_load_reg32(tmp, a->vm);
493
fpst = fpstatus_ptr(FPST_FPCR_F16);
494
gen_helper_rinth_exact(tmp, tmp, fpst);
495
- neon_store_reg32(tmp, a->vd);
496
+ vfp_store_reg32(tmp, a->vd);
497
tcg_temp_free_ptr(fpst);
498
tcg_temp_free_i32(tmp);
499
return true;
500
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
501
}
502
503
tmp = tcg_temp_new_i32();
504
- neon_load_reg32(tmp, a->vm);
505
+ vfp_load_reg32(tmp, a->vm);
506
fpst = fpstatus_ptr(FPST_FPCR);
507
gen_helper_rints_exact(tmp, tmp, fpst);
508
- neon_store_reg32(tmp, a->vd);
509
+ vfp_store_reg32(tmp, a->vd);
510
tcg_temp_free_ptr(fpst);
511
tcg_temp_free_i32(tmp);
512
return true;
513
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
514
515
vm = tcg_temp_new_i32();
516
vd = tcg_temp_new_i64();
517
- neon_load_reg32(vm, a->vm);
518
+ vfp_load_reg32(vm, a->vm);
519
gen_helper_vfp_fcvtds(vd, vm, cpu_env);
520
neon_store_reg64(vd, a->vd);
521
tcg_temp_free_i32(vm);
522
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
523
vm = tcg_temp_new_i64();
524
neon_load_reg64(vm, a->vm);
525
gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
526
- neon_store_reg32(vd, a->vd);
527
+ vfp_store_reg32(vd, a->vd);
528
tcg_temp_free_i32(vd);
529
tcg_temp_free_i64(vm);
530
return true;
531
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
532
}
533
534
vm = tcg_temp_new_i32();
535
- neon_load_reg32(vm, a->vm);
536
+ vfp_load_reg32(vm, a->vm);
537
fpst = fpstatus_ptr(FPST_FPCR_F16);
538
if (a->s) {
539
/* i32 -> f16 */
540
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
541
/* u32 -> f16 */
542
gen_helper_vfp_uitoh(vm, vm, fpst);
543
}
544
- neon_store_reg32(vm, a->vd);
545
+ vfp_store_reg32(vm, a->vd);
546
tcg_temp_free_i32(vm);
547
tcg_temp_free_ptr(fpst);
548
return true;
549
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
550
}
551
552
vm = tcg_temp_new_i32();
553
- neon_load_reg32(vm, a->vm);
554
+ vfp_load_reg32(vm, a->vm);
555
fpst = fpstatus_ptr(FPST_FPCR);
556
if (a->s) {
557
/* i32 -> f32 */
558
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
559
/* u32 -> f32 */
560
gen_helper_vfp_uitos(vm, vm, fpst);
561
}
562
- neon_store_reg32(vm, a->vd);
563
+ vfp_store_reg32(vm, a->vd);
564
tcg_temp_free_i32(vm);
565
tcg_temp_free_ptr(fpst);
566
return true;
567
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
568
569
vm = tcg_temp_new_i32();
570
vd = tcg_temp_new_i64();
571
- neon_load_reg32(vm, a->vm);
572
+ vfp_load_reg32(vm, a->vm);
573
fpst = fpstatus_ptr(FPST_FPCR);
574
if (a->s) {
575
/* i32 -> f64 */
576
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
577
vd = tcg_temp_new_i32();
578
neon_load_reg64(vm, a->vm);
579
gen_helper_vjcvt(vd, vm, cpu_env);
580
- neon_store_reg32(vd, a->vd);
581
+ vfp_store_reg32(vd, a->vd);
582
tcg_temp_free_i64(vm);
583
tcg_temp_free_i32(vd);
584
return true;
585
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
586
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
587
588
vd = tcg_temp_new_i32();
589
- neon_load_reg32(vd, a->vd);
590
+ vfp_load_reg32(vd, a->vd);
591
592
fpst = fpstatus_ptr(FPST_FPCR_F16);
593
shift = tcg_const_i32(frac_bits);
594
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
595
g_assert_not_reached();
596
}
597
598
- neon_store_reg32(vd, a->vd);
599
+ vfp_store_reg32(vd, a->vd);
600
tcg_temp_free_i32(vd);
601
tcg_temp_free_i32(shift);
602
tcg_temp_free_ptr(fpst);
603
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
604
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
605
606
vd = tcg_temp_new_i32();
607
- neon_load_reg32(vd, a->vd);
608
+ vfp_load_reg32(vd, a->vd);
609
610
fpst = fpstatus_ptr(FPST_FPCR);
611
shift = tcg_const_i32(frac_bits);
612
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
613
g_assert_not_reached();
614
}
615
616
- neon_store_reg32(vd, a->vd);
617
+ vfp_store_reg32(vd, a->vd);
618
tcg_temp_free_i32(vd);
619
tcg_temp_free_i32(shift);
620
tcg_temp_free_ptr(fpst);
621
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
622
623
fpst = fpstatus_ptr(FPST_FPCR_F16);
624
vm = tcg_temp_new_i32();
625
- neon_load_reg32(vm, a->vm);
626
+ vfp_load_reg32(vm, a->vm);
627
628
if (a->s) {
629
if (a->rz) {
630
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
631
gen_helper_vfp_touih(vm, vm, fpst);
632
}
633
}
634
- neon_store_reg32(vm, a->vd);
635
+ vfp_store_reg32(vm, a->vd);
636
tcg_temp_free_i32(vm);
637
tcg_temp_free_ptr(fpst);
638
return true;
639
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
640
641
fpst = fpstatus_ptr(FPST_FPCR);
642
vm = tcg_temp_new_i32();
643
- neon_load_reg32(vm, a->vm);
644
+ vfp_load_reg32(vm, a->vm);
645
646
if (a->s) {
647
if (a->rz) {
648
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
649
gen_helper_vfp_touis(vm, vm, fpst);
650
}
651
}
652
- neon_store_reg32(vm, a->vd);
653
+ vfp_store_reg32(vm, a->vd);
654
tcg_temp_free_i32(vm);
655
tcg_temp_free_ptr(fpst);
656
return true;
657
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
658
gen_helper_vfp_touid(vd, vm, fpst);
659
}
660
}
661
- neon_store_reg32(vd, a->vd);
662
+ vfp_store_reg32(vd, a->vd);
663
tcg_temp_free_i32(vd);
664
tcg_temp_free_i64(vm);
665
tcg_temp_free_ptr(fpst);
666
@@ -XXX,XX +XXX,XX @@ static bool trans_VINS(DisasContext *s, arg_VINS *a)
667
/* Insert low half of Vm into high half of Vd */
668
rm = tcg_temp_new_i32();
669
rd = tcg_temp_new_i32();
670
- neon_load_reg32(rm, a->vm);
671
- neon_load_reg32(rd, a->vd);
672
+ vfp_load_reg32(rm, a->vm);
673
+ vfp_load_reg32(rd, a->vd);
674
tcg_gen_deposit_i32(rd, rd, rm, 16, 16);
675
- neon_store_reg32(rd, a->vd);
676
+ vfp_store_reg32(rd, a->vd);
677
tcg_temp_free_i32(rm);
678
tcg_temp_free_i32(rd);
679
return true;
680
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a)
681
682
/* Set Vd to high half of Vm */
683
rm = tcg_temp_new_i32();
684
- neon_load_reg32(rm, a->vm);
685
+ vfp_load_reg32(rm, a->vm);
686
tcg_gen_shri_i32(rm, rm, 16);
687
- neon_store_reg32(rm, a->vd);
688
+ vfp_store_reg32(rm, a->vd);
689
tcg_temp_free_i32(rm);
690
return true;
691
}
692
--
693
2.20.1
694
695
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/6] hw/char: Implement nRF51 SoC UART
[PULL 08/26] target/arm: Add read/write_neon_element64
1
From: Julia Suvorova via Qemu-devel <qemu-devel@nongnu.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Not implemented: CTS/NCTS, PSEL*.
3
Replace all uses of neon_load/store_reg64 within translate-neon.c.inc.
4
4
5
Signed-off-by: Julia Suvorova <jusual@mail.ru>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
6
Message-id: 20201030022618.785675-9-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
---
9
hw/char/Makefile.objs | 1 +
10
target/arm/translate.c | 26 +++++++++
10
include/hw/char/nrf51_uart.h | 78 +++++++++
11
target/arm/translate-neon.c.inc | 94 ++++++++++++++++-----------------
11
hw/char/nrf51_uart.c | 330 +++++++++++++++++++++++++++++++++++
12
2 files changed, 73 insertions(+), 47 deletions(-)
12
hw/char/trace-events | 4 +
13
13
4 files changed, 413 insertions(+)
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
create mode 100644 include/hw/char/nrf51_uart.h
15
create mode 100644 hw/char/nrf51_uart.c
16
17
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/char/Makefile.objs
16
--- a/target/arm/translate.c
20
+++ b/hw/char/Makefile.objs
17
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
22
common-obj-$(CONFIG_IPACK) += ipoctal232.o
19
}
23
common-obj-$(CONFIG_ESCC) += escc.o
20
}
24
+common-obj-$(CONFIG_NRF51_SOC) += nrf51_uart.o
21
25
common-obj-$(CONFIG_PARALLEL) += parallel.o
22
+static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
26
common-obj-$(CONFIG_PARALLEL) += parallel-isa.o
23
+{
27
common-obj-$(CONFIG_PL011) += pl011.o
24
+ long off = neon_element_offset(reg, ele, memop);
28
diff --git a/include/hw/char/nrf51_uart.h b/include/hw/char/nrf51_uart.h
29
new file mode 100644
30
index XXXXXXX..XXXXXXX
31
--- /dev/null
32
+++ b/include/hw/char/nrf51_uart.h
33
@@ -XXX,XX +XXX,XX @@
34
+/*
35
+ * nRF51 SoC UART emulation
36
+ *
37
+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
38
+ *
39
+ * This program is free software; you can redistribute it and/or modify
40
+ * it under the terms of the GNU General Public License version 2 or
41
+ * (at your option) any later version.
42
+ */
43
+
25
+
44
+#ifndef NRF51_UART_H
26
+ switch (memop) {
45
+#define NRF51_UART_H
27
+ case MO_Q:
46
+
28
+ tcg_gen_ld_i64(dest, cpu_env, off);
47
+#include "hw/sysbus.h"
48
+#include "chardev/char-fe.h"
49
+#include "hw/registerfields.h"
50
+
51
+#define UART_FIFO_LENGTH 6
52
+#define UART_BASE 0x40002000
53
+#define UART_SIZE 0x1000
54
+
55
+#define TYPE_NRF51_UART "nrf51_soc.uart"
56
+#define NRF51_UART(obj) OBJECT_CHECK(NRF51UARTState, (obj), TYPE_NRF51_UART)
57
+
58
+REG32(UART_STARTRX, 0x000)
59
+REG32(UART_STOPRX, 0x004)
60
+REG32(UART_STARTTX, 0x008)
61
+REG32(UART_STOPTX, 0x00C)
62
+REG32(UART_SUSPEND, 0x01C)
63
+
64
+REG32(UART_CTS, 0x100)
65
+REG32(UART_NCTS, 0x104)
66
+REG32(UART_RXDRDY, 0x108)
67
+REG32(UART_TXDRDY, 0x11C)
68
+REG32(UART_ERROR, 0x124)
69
+REG32(UART_RXTO, 0x144)
70
+
71
+REG32(UART_INTEN, 0x300)
72
+ FIELD(UART_INTEN, CTS, 0, 1)
73
+ FIELD(UART_INTEN, NCTS, 1, 1)
74
+ FIELD(UART_INTEN, RXDRDY, 2, 1)
75
+ FIELD(UART_INTEN, TXDRDY, 7, 1)
76
+ FIELD(UART_INTEN, ERROR, 9, 1)
77
+ FIELD(UART_INTEN, RXTO, 17, 1)
78
+REG32(UART_INTENSET, 0x304)
79
+REG32(UART_INTENCLR, 0x308)
80
+REG32(UART_ERRORSRC, 0x480)
81
+REG32(UART_ENABLE, 0x500)
82
+REG32(UART_PSELRTS, 0x508)
83
+REG32(UART_PSELTXD, 0x50C)
84
+REG32(UART_PSELCTS, 0x510)
85
+REG32(UART_PSELRXD, 0x514)
86
+REG32(UART_RXD, 0x518)
87
+REG32(UART_TXD, 0x51C)
88
+REG32(UART_BAUDRATE, 0x524)
89
+REG32(UART_CONFIG, 0x56C)
90
+
91
+typedef struct NRF51UARTState {
92
+ SysBusDevice parent_obj;
93
+
94
+ MemoryRegion iomem;
95
+ CharBackend chr;
96
+ qemu_irq irq;
97
+ guint watch_tag;
98
+
99
+ uint8_t rx_fifo[UART_FIFO_LENGTH];
100
+ unsigned int rx_fifo_pos;
101
+ unsigned int rx_fifo_len;
102
+
103
+ uint32_t reg[0x56C];
104
+
105
+ bool rx_started;
106
+ bool tx_started;
107
+ bool pending_tx_byte;
108
+ bool enabled;
109
+} NRF51UARTState;
110
+
111
+#endif
112
diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c
113
new file mode 100644
114
index XXXXXXX..XXXXXXX
115
--- /dev/null
116
+++ b/hw/char/nrf51_uart.c
117
@@ -XXX,XX +XXX,XX @@
118
+/*
119
+ * nRF51 SoC UART emulation
120
+ *
121
+ * See nRF51 Series Reference Manual, "29 Universal Asynchronous
122
+ * Receiver/Transmitter" for hardware specifications:
123
+ * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
124
+ *
125
+ * Copyright (c) 2018 Julia Suvorova <jusual@mail.ru>
126
+ *
127
+ * This program is free software; you can redistribute it and/or modify
128
+ * it under the terms of the GNU General Public License version 2 or
129
+ * (at your option) any later version.
130
+ */
131
+
132
+#include "qemu/osdep.h"
133
+#include "qemu/log.h"
134
+#include "hw/char/nrf51_uart.h"
135
+#include "trace.h"
136
+
137
+static void nrf51_uart_update_irq(NRF51UARTState *s)
138
+{
139
+ bool irq = false;
140
+
141
+ irq |= (s->reg[R_UART_RXDRDY] &&
142
+ (s->reg[R_UART_INTEN] & R_UART_INTEN_RXDRDY_MASK));
143
+ irq |= (s->reg[R_UART_TXDRDY] &&
144
+ (s->reg[R_UART_INTEN] & R_UART_INTEN_TXDRDY_MASK));
145
+ irq |= (s->reg[R_UART_ERROR] &&
146
+ (s->reg[R_UART_INTEN] & R_UART_INTEN_ERROR_MASK));
147
+ irq |= (s->reg[R_UART_RXTO] &&
148
+ (s->reg[R_UART_INTEN] & R_UART_INTEN_RXTO_MASK));
149
+
150
+ qemu_set_irq(s->irq, irq);
151
+}
152
+
153
+static uint64_t uart_read(void *opaque, hwaddr addr, unsigned int size)
154
+{
155
+ NRF51UARTState *s = NRF51_UART(opaque);
156
+ uint64_t r;
157
+
158
+ if (!s->enabled) {
159
+ return 0;
160
+ }
161
+
162
+ switch (addr) {
163
+ case A_UART_RXD:
164
+ r = s->rx_fifo[s->rx_fifo_pos];
165
+ if (s->rx_started && s->rx_fifo_len) {
166
+ s->rx_fifo_pos = (s->rx_fifo_pos + 1) % UART_FIFO_LENGTH;
167
+ s->rx_fifo_len--;
168
+ if (s->rx_fifo_len) {
169
+ s->reg[R_UART_RXDRDY] = 1;
170
+ nrf51_uart_update_irq(s);
171
+ }
172
+ qemu_chr_fe_accept_input(&s->chr);
173
+ }
174
+ break;
175
+ case A_UART_INTENSET:
176
+ case A_UART_INTENCLR:
177
+ case A_UART_INTEN:
178
+ r = s->reg[R_UART_INTEN];
179
+ break;
29
+ break;
180
+ default:
30
+ default:
181
+ r = s->reg[addr / 4];
31
+ g_assert_not_reached();
182
+ break;
183
+ }
184
+
185
+ trace_nrf51_uart_read(addr, r, size);
186
+
187
+ return r;
188
+}
189
+
190
+static gboolean uart_transmit(GIOChannel *chan, GIOCondition cond, void *opaque)
191
+{
192
+ NRF51UARTState *s = NRF51_UART(opaque);
193
+ int r;
194
+ uint8_t c = s->reg[R_UART_TXD];
195
+
196
+ s->watch_tag = 0;
197
+
198
+ r = qemu_chr_fe_write(&s->chr, &c, 1);
199
+ if (r <= 0) {
200
+ s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
201
+ uart_transmit, s);
202
+ if (!s->watch_tag) {
203
+ /* The hardware has no transmit error reporting,
204
+ * so silently drop the byte
205
+ */
206
+ goto buffer_drained;
207
+ }
208
+ return FALSE;
209
+ }
210
+
211
+buffer_drained:
212
+ s->reg[R_UART_TXDRDY] = 1;
213
+ s->pending_tx_byte = false;
214
+ return FALSE;
215
+}
216
+
217
+static void uart_cancel_transmit(NRF51UARTState *s)
218
+{
219
+ if (s->watch_tag) {
220
+ g_source_remove(s->watch_tag);
221
+ s->watch_tag = 0;
222
+ }
32
+ }
223
+}
33
+}
224
+
34
+
225
+static void uart_write(void *opaque, hwaddr addr,
35
static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
226
+ uint64_t value, unsigned int size)
36
{
37
long off = neon_element_offset(reg, ele, memop);
38
@@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
39
}
40
}
41
42
+static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
227
+{
43
+{
228
+ NRF51UARTState *s = NRF51_UART(opaque);
44
+ long off = neon_element_offset(reg, ele, memop);
229
+
45
+
230
+ trace_nrf51_uart_write(addr, value, size);
46
+ switch (memop) {
231
+
47
+ case MO_64:
232
+ if (!s->enabled && (addr != A_UART_ENABLE)) {
48
+ tcg_gen_st_i64(src, cpu_env, off);
233
+ return;
234
+ }
235
+
236
+ switch (addr) {
237
+ case A_UART_TXD:
238
+ if (!s->pending_tx_byte && s->tx_started) {
239
+ s->reg[R_UART_TXD] = value;
240
+ s->pending_tx_byte = true;
241
+ uart_transmit(NULL, G_IO_OUT, s);
242
+ }
243
+ break;
244
+ case A_UART_INTEN:
245
+ s->reg[R_UART_INTEN] = value;
246
+ break;
247
+ case A_UART_INTENSET:
248
+ s->reg[R_UART_INTEN] |= value;
249
+ break;
250
+ case A_UART_INTENCLR:
251
+ s->reg[R_UART_INTEN] &= ~value;
252
+ break;
253
+ case A_UART_TXDRDY ... A_UART_RXTO:
254
+ s->reg[addr / 4] = value;
255
+ break;
256
+ case A_UART_ERRORSRC:
257
+ s->reg[addr / 4] &= ~value;
258
+ break;
259
+ case A_UART_RXD:
260
+ break;
261
+ case A_UART_RXDRDY:
262
+ if (value == 0) {
263
+ s->reg[R_UART_RXDRDY] = 0;
264
+ }
265
+ break;
266
+ case A_UART_STARTTX:
267
+ if (value == 1) {
268
+ s->tx_started = true;
269
+ }
270
+ break;
271
+ case A_UART_STARTRX:
272
+ if (value == 1) {
273
+ s->rx_started = true;
274
+ }
275
+ break;
276
+ case A_UART_ENABLE:
277
+ if (value) {
278
+ if (value == 4) {
279
+ s->enabled = true;
280
+ }
281
+ break;
282
+ }
283
+ s->enabled = false;
284
+ value = 1;
285
+ /* fall through */
286
+ case A_UART_SUSPEND:
287
+ case A_UART_STOPTX:
288
+ if (value == 1) {
289
+ s->tx_started = false;
290
+ }
291
+ /* fall through */
292
+ case A_UART_STOPRX:
293
+ if (addr != A_UART_STOPTX && value == 1) {
294
+ s->rx_started = false;
295
+ s->reg[R_UART_RXTO] = 1;
296
+ }
297
+ break;
49
+ break;
298
+ default:
50
+ default:
299
+ s->reg[addr / 4] = value;
51
+ g_assert_not_reached();
300
+ break;
301
+ }
302
+ nrf51_uart_update_irq(s);
303
+}
304
+
305
+static const MemoryRegionOps uart_ops = {
306
+ .read = uart_read,
307
+ .write = uart_write,
308
+ .endianness = DEVICE_LITTLE_ENDIAN,
309
+};
310
+
311
+static void nrf51_uart_reset(DeviceState *dev)
312
+{
313
+ NRF51UARTState *s = NRF51_UART(dev);
314
+
315
+ s->pending_tx_byte = 0;
316
+
317
+ uart_cancel_transmit(s);
318
+
319
+ memset(s->reg, 0, sizeof(s->reg));
320
+
321
+ s->reg[R_UART_PSELRTS] = 0xFFFFFFFF;
322
+ s->reg[R_UART_PSELTXD] = 0xFFFFFFFF;
323
+ s->reg[R_UART_PSELCTS] = 0xFFFFFFFF;
324
+ s->reg[R_UART_PSELRXD] = 0xFFFFFFFF;
325
+ s->reg[R_UART_BAUDRATE] = 0x4000000;
326
+
327
+ s->rx_fifo_len = 0;
328
+ s->rx_fifo_pos = 0;
329
+ s->rx_started = false;
330
+ s->tx_started = false;
331
+ s->enabled = false;
332
+}
333
+
334
+static void uart_receive(void *opaque, const uint8_t *buf, int size)
335
+{
336
+
337
+ NRF51UARTState *s = NRF51_UART(opaque);
338
+ int i;
339
+
340
+ if (size == 0 || s->rx_fifo_len >= UART_FIFO_LENGTH) {
341
+ return;
342
+ }
343
+
344
+ for (i = 0; i < size; i++) {
345
+ uint32_t pos = (s->rx_fifo_pos + s->rx_fifo_len) % UART_FIFO_LENGTH;
346
+ s->rx_fifo[pos] = buf[i];
347
+ s->rx_fifo_len++;
348
+ }
349
+
350
+ s->reg[R_UART_RXDRDY] = 1;
351
+ nrf51_uart_update_irq(s);
352
+}
353
+
354
+static int uart_can_receive(void *opaque)
355
+{
356
+ NRF51UARTState *s = NRF51_UART(opaque);
357
+
358
+ return s->rx_started ? (UART_FIFO_LENGTH - s->rx_fifo_len) : 0;
359
+}
360
+
361
+static void uart_event(void *opaque, int event)
362
+{
363
+ NRF51UARTState *s = NRF51_UART(opaque);
364
+
365
+ if (event == CHR_EVENT_BREAK) {
366
+ s->reg[R_UART_ERRORSRC] |= 3;
367
+ s->reg[R_UART_ERROR] = 1;
368
+ nrf51_uart_update_irq(s);
369
+ }
52
+ }
370
+}
53
+}
371
+
54
+
372
+static void nrf51_uart_realize(DeviceState *dev, Error **errp)
55
static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
373
+{
56
{
374
+ NRF51UARTState *s = NRF51_UART(dev);
57
TCGv_ptr ret = tcg_temp_new_ptr();
375
+
58
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
376
+ qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
377
+ uart_event, NULL, s, NULL, true);
378
+}
379
+
380
+static void nrf51_uart_init(Object *obj)
381
+{
382
+ NRF51UARTState *s = NRF51_UART(obj);
383
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
384
+
385
+ memory_region_init_io(&s->iomem, obj, &uart_ops, s,
386
+ "nrf51_soc.uart", UART_SIZE);
387
+ sysbus_init_mmio(sbd, &s->iomem);
388
+ sysbus_init_irq(sbd, &s->irq);
389
+}
390
+
391
+static int nrf51_uart_post_load(void *opaque, int version_id)
392
+{
393
+ NRF51UARTState *s = NRF51_UART(opaque);
394
+
395
+ if (s->pending_tx_byte) {
396
+ s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
397
+ uart_transmit, s);
398
+ }
399
+
400
+ return 0;
401
+}
402
+
403
+static const VMStateDescription nrf51_uart_vmstate = {
404
+ .name = "nrf51_soc.uart",
405
+ .post_load = nrf51_uart_post_load,
406
+ .fields = (VMStateField[]) {
407
+ VMSTATE_UINT32_ARRAY(reg, NRF51UARTState, 0x56C),
408
+ VMSTATE_UINT8_ARRAY(rx_fifo, NRF51UARTState, UART_FIFO_LENGTH),
409
+ VMSTATE_UINT32(rx_fifo_pos, NRF51UARTState),
410
+ VMSTATE_UINT32(rx_fifo_len, NRF51UARTState),
411
+ VMSTATE_BOOL(rx_started, NRF51UARTState),
412
+ VMSTATE_BOOL(tx_started, NRF51UARTState),
413
+ VMSTATE_BOOL(pending_tx_byte, NRF51UARTState),
414
+ VMSTATE_BOOL(enabled, NRF51UARTState),
415
+ VMSTATE_END_OF_LIST()
416
+ }
417
+};
418
+
419
+static Property nrf51_uart_properties[] = {
420
+ DEFINE_PROP_CHR("chardev", NRF51UARTState, chr),
421
+ DEFINE_PROP_END_OF_LIST(),
422
+};
423
+
424
+static void nrf51_uart_class_init(ObjectClass *klass, void *data)
425
+{
426
+ DeviceClass *dc = DEVICE_CLASS(klass);
427
+
428
+ dc->reset = nrf51_uart_reset;
429
+ dc->realize = nrf51_uart_realize;
430
+ dc->props = nrf51_uart_properties;
431
+ dc->vmsd = &nrf51_uart_vmstate;
432
+}
433
+
434
+static const TypeInfo nrf51_uart_info = {
435
+ .name = TYPE_NRF51_UART,
436
+ .parent = TYPE_SYS_BUS_DEVICE,
437
+ .instance_size = sizeof(NRF51UARTState),
438
+ .instance_init = nrf51_uart_init,
439
+ .class_init = nrf51_uart_class_init
440
+};
441
+
442
+static void nrf51_uart_register_types(void)
443
+{
444
+ type_register_static(&nrf51_uart_info);
445
+}
446
+
447
+type_init(nrf51_uart_register_types)
448
diff --git a/hw/char/trace-events b/hw/char/trace-events
449
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
450
--- a/hw/char/trace-events
60
--- a/target/arm/translate-neon.c.inc
451
+++ b/hw/char/trace-events
61
+++ b/target/arm/translate-neon.c.inc
452
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_uart_receive(uint8_t c) "CMSDK APB UART: got character 0x%x from backe
62
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
453
cmsdk_apb_uart_tx_pending(void) "CMSDK APB UART: character send to backend pending"
63
for (pass = 0; pass < a->q + 1; pass++) {
454
cmsdk_apb_uart_tx(uint8_t c) "CMSDK APB UART: character 0x%x sent to backend"
64
TCGv_i64 tmp = tcg_temp_new_i64();
455
cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
65
456
+
66
- neon_load_reg64(tmp, a->vm + pass);
457
+# hw/char/nrf51_uart.c
67
+ read_neon_element64(tmp, a->vm, pass, MO_64);
458
+nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
68
fn(tmp, cpu_env, tmp, constimm);
459
+nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
69
- neon_store_reg64(tmp, a->vd + pass);
70
+ write_neon_element64(tmp, a->vd, pass, MO_64);
71
tcg_temp_free_i64(tmp);
72
}
73
tcg_temp_free_i64(constimm);
74
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
75
rd = tcg_temp_new_i32();
76
77
/* Load both inputs first to avoid potential overwrite if rm == rd */
78
- neon_load_reg64(rm1, a->vm);
79
- neon_load_reg64(rm2, a->vm + 1);
80
+ read_neon_element64(rm1, a->vm, 0, MO_64);
81
+ read_neon_element64(rm2, a->vm, 1, MO_64);
82
83
shiftfn(rm1, rm1, constimm);
84
narrowfn(rd, cpu_env, rm1);
85
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
86
tcg_gen_shli_i64(tmp, tmp, a->shift);
87
tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
88
}
89
- neon_store_reg64(tmp, a->vd);
90
+ write_neon_element64(tmp, a->vd, 0, MO_64);
91
92
widenfn(tmp, rm1);
93
tcg_temp_free_i32(rm1);
94
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
95
tcg_gen_shli_i64(tmp, tmp, a->shift);
96
tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
97
}
98
- neon_store_reg64(tmp, a->vd + 1);
99
+ write_neon_element64(tmp, a->vd, 1, MO_64);
100
tcg_temp_free_i64(tmp);
101
return true;
102
}
103
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
104
rm_64 = tcg_temp_new_i64();
105
106
if (src1_wide) {
107
- neon_load_reg64(rn0_64, a->vn);
108
+ read_neon_element64(rn0_64, a->vn, 0, MO_64);
109
} else {
110
TCGv_i32 tmp = tcg_temp_new_i32();
111
read_neon_element32(tmp, a->vn, 0, MO_32);
112
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
113
* avoid incorrect results if a narrow input overlaps with the result.
114
*/
115
if (src1_wide) {
116
- neon_load_reg64(rn1_64, a->vn + 1);
117
+ read_neon_element64(rn1_64, a->vn, 1, MO_64);
118
} else {
119
TCGv_i32 tmp = tcg_temp_new_i32();
120
read_neon_element32(tmp, a->vn, 1, MO_32);
121
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
122
rm = tcg_temp_new_i32();
123
read_neon_element32(rm, a->vm, 1, MO_32);
124
125
- neon_store_reg64(rn0_64, a->vd);
126
+ write_neon_element64(rn0_64, a->vd, 0, MO_64);
127
128
widenfn(rm_64, rm);
129
tcg_temp_free_i32(rm);
130
opfn(rn1_64, rn1_64, rm_64);
131
- neon_store_reg64(rn1_64, a->vd + 1);
132
+ write_neon_element64(rn1_64, a->vd, 1, MO_64);
133
134
tcg_temp_free_i64(rn0_64);
135
tcg_temp_free_i64(rn1_64);
136
@@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
137
rd0 = tcg_temp_new_i32();
138
rd1 = tcg_temp_new_i32();
139
140
- neon_load_reg64(rn_64, a->vn);
141
- neon_load_reg64(rm_64, a->vm);
142
+ read_neon_element64(rn_64, a->vn, 0, MO_64);
143
+ read_neon_element64(rm_64, a->vm, 0, MO_64);
144
145
opfn(rn_64, rn_64, rm_64);
146
147
narrowfn(rd0, rn_64);
148
149
- neon_load_reg64(rn_64, a->vn + 1);
150
- neon_load_reg64(rm_64, a->vm + 1);
151
+ read_neon_element64(rn_64, a->vn, 1, MO_64);
152
+ read_neon_element64(rm_64, a->vm, 1, MO_64);
153
154
opfn(rn_64, rn_64, rm_64);
155
156
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
157
/* Don't store results until after all loads: they might overlap */
158
if (accfn) {
159
tmp = tcg_temp_new_i64();
160
- neon_load_reg64(tmp, a->vd);
161
+ read_neon_element64(tmp, a->vd, 0, MO_64);
162
accfn(tmp, tmp, rd0);
163
- neon_store_reg64(tmp, a->vd);
164
- neon_load_reg64(tmp, a->vd + 1);
165
+ write_neon_element64(tmp, a->vd, 0, MO_64);
166
+ read_neon_element64(tmp, a->vd, 1, MO_64);
167
accfn(tmp, tmp, rd1);
168
- neon_store_reg64(tmp, a->vd + 1);
169
+ write_neon_element64(tmp, a->vd, 1, MO_64);
170
tcg_temp_free_i64(tmp);
171
} else {
172
- neon_store_reg64(rd0, a->vd);
173
- neon_store_reg64(rd1, a->vd + 1);
174
+ write_neon_element64(rd0, a->vd, 0, MO_64);
175
+ write_neon_element64(rd1, a->vd, 1, MO_64);
176
}
177
178
tcg_temp_free_i64(rd0);
179
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
180
181
if (accfn) {
182
TCGv_i64 t64 = tcg_temp_new_i64();
183
- neon_load_reg64(t64, a->vd);
184
+ read_neon_element64(t64, a->vd, 0, MO_64);
185
accfn(t64, t64, rn0_64);
186
- neon_store_reg64(t64, a->vd);
187
- neon_load_reg64(t64, a->vd + 1);
188
+ write_neon_element64(t64, a->vd, 0, MO_64);
189
+ read_neon_element64(t64, a->vd, 1, MO_64);
190
accfn(t64, t64, rn1_64);
191
- neon_store_reg64(t64, a->vd + 1);
192
+ write_neon_element64(t64, a->vd, 1, MO_64);
193
tcg_temp_free_i64(t64);
194
} else {
195
- neon_store_reg64(rn0_64, a->vd);
196
- neon_store_reg64(rn1_64, a->vd + 1);
197
+ write_neon_element64(rn0_64, a->vd, 0, MO_64);
198
+ write_neon_element64(rn1_64, a->vd, 1, MO_64);
199
}
200
tcg_temp_free_i64(rn0_64);
201
tcg_temp_free_i64(rn1_64);
202
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
203
right = tcg_temp_new_i64();
204
dest = tcg_temp_new_i64();
205
206
- neon_load_reg64(right, a->vn);
207
- neon_load_reg64(left, a->vm);
208
+ read_neon_element64(right, a->vn, 0, MO_64);
209
+ read_neon_element64(left, a->vm, 0, MO_64);
210
tcg_gen_extract2_i64(dest, right, left, a->imm * 8);
211
- neon_store_reg64(dest, a->vd);
212
+ write_neon_element64(dest, a->vd, 0, MO_64);
213
214
tcg_temp_free_i64(left);
215
tcg_temp_free_i64(right);
216
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
217
destright = tcg_temp_new_i64();
218
219
if (a->imm < 8) {
220
- neon_load_reg64(right, a->vn);
221
- neon_load_reg64(middle, a->vn + 1);
222
+ read_neon_element64(right, a->vn, 0, MO_64);
223
+ read_neon_element64(middle, a->vn, 1, MO_64);
224
tcg_gen_extract2_i64(destright, right, middle, a->imm * 8);
225
- neon_load_reg64(left, a->vm);
226
+ read_neon_element64(left, a->vm, 0, MO_64);
227
tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8);
228
} else {
229
- neon_load_reg64(right, a->vn + 1);
230
- neon_load_reg64(middle, a->vm);
231
+ read_neon_element64(right, a->vn, 1, MO_64);
232
+ read_neon_element64(middle, a->vm, 0, MO_64);
233
tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8);
234
- neon_load_reg64(left, a->vm + 1);
235
+ read_neon_element64(left, a->vm, 1, MO_64);
236
tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8);
237
}
238
239
- neon_store_reg64(destright, a->vd);
240
- neon_store_reg64(destleft, a->vd + 1);
241
+ write_neon_element64(destright, a->vd, 0, MO_64);
242
+ write_neon_element64(destleft, a->vd, 1, MO_64);
243
244
tcg_temp_free_i64(destright);
245
tcg_temp_free_i64(destleft);
246
@@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
247
248
if (accfn) {
249
TCGv_i64 tmp64 = tcg_temp_new_i64();
250
- neon_load_reg64(tmp64, a->vd + pass);
251
+ read_neon_element64(tmp64, a->vd, pass, MO_64);
252
accfn(rd_64, tmp64, rd_64);
253
tcg_temp_free_i64(tmp64);
254
}
255
- neon_store_reg64(rd_64, a->vd + pass);
256
+ write_neon_element64(rd_64, a->vd, pass, MO_64);
257
tcg_temp_free_i64(rd_64);
258
}
259
return true;
260
@@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
261
rd0 = tcg_temp_new_i32();
262
rd1 = tcg_temp_new_i32();
263
264
- neon_load_reg64(rm, a->vm);
265
+ read_neon_element64(rm, a->vm, 0, MO_64);
266
narrowfn(rd0, cpu_env, rm);
267
- neon_load_reg64(rm, a->vm + 1);
268
+ read_neon_element64(rm, a->vm, 1, MO_64);
269
narrowfn(rd1, cpu_env, rm);
270
write_neon_element32(rd0, a->vd, 0, MO_32);
271
write_neon_element32(rd1, a->vd, 1, MO_32);
272
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
273
274
widenfn(rd, rm0);
275
tcg_gen_shli_i64(rd, rd, 8 << a->size);
276
- neon_store_reg64(rd, a->vd);
277
+ write_neon_element64(rd, a->vd, 0, MO_64);
278
widenfn(rd, rm1);
279
tcg_gen_shli_i64(rd, rd, 8 << a->size);
280
- neon_store_reg64(rd, a->vd + 1);
281
+ write_neon_element64(rd, a->vd, 1, MO_64);
282
283
tcg_temp_free_i64(rd);
284
tcg_temp_free_i32(rm0);
285
@@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a)
286
rm = tcg_temp_new_i64();
287
rd = tcg_temp_new_i64();
288
for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
289
- neon_load_reg64(rm, a->vm + pass);
290
- neon_load_reg64(rd, a->vd + pass);
291
- neon_store_reg64(rm, a->vd + pass);
292
- neon_store_reg64(rd, a->vm + pass);
293
+ read_neon_element64(rm, a->vm, pass, MO_64);
294
+ read_neon_element64(rd, a->vd, pass, MO_64);
295
+ write_neon_element64(rm, a->vd, pass, MO_64);
296
+ write_neon_element64(rd, a->vm, pass, MO_64);
297
}
298
tcg_temp_free_i64(rm);
299
tcg_temp_free_i64(rd);
460
--
300
--
461
2.19.1
301
2.20.1
462
302
463
303
diff view generated by jsdifflib
New patch
[PULL 09/26] target/arm: Rename neon_load_reg64 to vfp_load_reg64
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
The only uses of this function are for loading VFP
4
double-precision values, and nothing to do with NEON.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201030022618.785675-10-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate.c | 8 ++--
12
target/arm/translate-vfp.c.inc | 84 +++++++++++++++++-----------------
13
2 files changed, 46 insertions(+), 46 deletions(-)
14
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
18
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg)
20
}
21
}
22
23
-static inline void neon_load_reg64(TCGv_i64 var, int reg)
24
+static inline void vfp_load_reg64(TCGv_i64 var, int reg)
25
{
26
- tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
27
+ tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
28
}
29
30
-static inline void neon_store_reg64(TCGv_i64 var, int reg)
31
+static inline void vfp_store_reg64(TCGv_i64 var, int reg)
32
{
33
- tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
34
+ tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
35
}
36
37
static inline void vfp_load_reg32(TCGv_i32 var, int reg)
38
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/translate-vfp.c.inc
41
+++ b/target/arm/translate-vfp.c.inc
42
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
43
tcg_gen_ext_i32_i64(nf, cpu_NF);
44
tcg_gen_ext_i32_i64(vf, cpu_VF);
45
46
- neon_load_reg64(frn, rn);
47
- neon_load_reg64(frm, rm);
48
+ vfp_load_reg64(frn, rn);
49
+ vfp_load_reg64(frm, rm);
50
switch (a->cc) {
51
case 0: /* eq: Z */
52
tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
53
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
54
tcg_temp_free_i64(tmp);
55
break;
56
}
57
- neon_store_reg64(dest, rd);
58
+ vfp_store_reg64(dest, rd);
59
tcg_temp_free_i64(frn);
60
tcg_temp_free_i64(frm);
61
tcg_temp_free_i64(dest);
62
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
63
TCGv_i64 tcg_res;
64
tcg_op = tcg_temp_new_i64();
65
tcg_res = tcg_temp_new_i64();
66
- neon_load_reg64(tcg_op, rm);
67
+ vfp_load_reg64(tcg_op, rm);
68
gen_helper_rintd(tcg_res, tcg_op, fpst);
69
- neon_store_reg64(tcg_res, rd);
70
+ vfp_store_reg64(tcg_res, rd);
71
tcg_temp_free_i64(tcg_op);
72
tcg_temp_free_i64(tcg_res);
73
} else {
74
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
75
tcg_double = tcg_temp_new_i64();
76
tcg_res = tcg_temp_new_i64();
77
tcg_tmp = tcg_temp_new_i32();
78
- neon_load_reg64(tcg_double, rm);
79
+ vfp_load_reg64(tcg_double, rm);
80
if (is_signed) {
81
gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst);
82
} else {
83
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
84
tmp = tcg_temp_new_i64();
85
if (a->l) {
86
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
87
- neon_store_reg64(tmp, a->vd);
88
+ vfp_store_reg64(tmp, a->vd);
89
} else {
90
- neon_load_reg64(tmp, a->vd);
91
+ vfp_load_reg64(tmp, a->vd);
92
gen_aa32_st64(s, tmp, addr, get_mem_index(s));
93
}
94
tcg_temp_free_i64(tmp);
95
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
96
if (a->l) {
97
/* load */
98
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
99
- neon_store_reg64(tmp, a->vd + i);
100
+ vfp_store_reg64(tmp, a->vd + i);
101
} else {
102
/* store */
103
- neon_load_reg64(tmp, a->vd + i);
104
+ vfp_load_reg64(tmp, a->vd + i);
105
gen_aa32_st64(s, tmp, addr, get_mem_index(s));
106
}
107
tcg_gen_addi_i32(addr, addr, offset);
108
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
109
fd = tcg_temp_new_i64();
110
fpst = fpstatus_ptr(FPST_FPCR);
111
112
- neon_load_reg64(f0, vn);
113
- neon_load_reg64(f1, vm);
114
+ vfp_load_reg64(f0, vn);
115
+ vfp_load_reg64(f1, vm);
116
117
for (;;) {
118
if (reads_vd) {
119
- neon_load_reg64(fd, vd);
120
+ vfp_load_reg64(fd, vd);
121
}
122
fn(fd, f0, f1, fpst);
123
- neon_store_reg64(fd, vd);
124
+ vfp_store_reg64(fd, vd);
125
126
if (veclen == 0) {
127
break;
128
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
129
veclen--;
130
vd = vfp_advance_dreg(vd, delta_d);
131
vn = vfp_advance_dreg(vn, delta_d);
132
- neon_load_reg64(f0, vn);
133
+ vfp_load_reg64(f0, vn);
134
if (delta_m) {
135
vm = vfp_advance_dreg(vm, delta_m);
136
- neon_load_reg64(f1, vm);
137
+ vfp_load_reg64(f1, vm);
138
}
139
}
140
141
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
142
f0 = tcg_temp_new_i64();
143
fd = tcg_temp_new_i64();
144
145
- neon_load_reg64(f0, vm);
146
+ vfp_load_reg64(f0, vm);
147
148
for (;;) {
149
fn(fd, f0);
150
- neon_store_reg64(fd, vd);
151
+ vfp_store_reg64(fd, vd);
152
153
if (veclen == 0) {
154
break;
155
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
156
/* single source one-many */
157
while (veclen--) {
158
vd = vfp_advance_dreg(vd, delta_d);
159
- neon_store_reg64(fd, vd);
160
+ vfp_store_reg64(fd, vd);
161
}
162
break;
163
}
164
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
165
veclen--;
166
vd = vfp_advance_dreg(vd, delta_d);
167
vd = vfp_advance_dreg(vm, delta_m);
168
- neon_load_reg64(f0, vm);
169
+ vfp_load_reg64(f0, vm);
170
}
171
172
tcg_temp_free_i64(f0);
173
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
174
vm = tcg_temp_new_i64();
175
vd = tcg_temp_new_i64();
176
177
- neon_load_reg64(vn, a->vn);
178
- neon_load_reg64(vm, a->vm);
179
+ vfp_load_reg64(vn, a->vn);
180
+ vfp_load_reg64(vm, a->vm);
181
if (neg_n) {
182
/* VFNMS, VFMS */
183
gen_helper_vfp_negd(vn, vn);
184
}
185
- neon_load_reg64(vd, a->vd);
186
+ vfp_load_reg64(vd, a->vd);
187
if (neg_d) {
188
/* VFNMA, VFNMS */
189
gen_helper_vfp_negd(vd, vd);
190
}
191
fpst = fpstatus_ptr(FPST_FPCR);
192
gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
193
- neon_store_reg64(vd, a->vd);
194
+ vfp_store_reg64(vd, a->vd);
195
196
tcg_temp_free_ptr(fpst);
197
tcg_temp_free_i64(vn);
198
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
199
fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
200
201
for (;;) {
202
- neon_store_reg64(fd, vd);
203
+ vfp_store_reg64(fd, vd);
204
205
if (veclen == 0) {
206
break;
207
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
208
vd = tcg_temp_new_i64();
209
vm = tcg_temp_new_i64();
210
211
- neon_load_reg64(vd, a->vd);
212
+ vfp_load_reg64(vd, a->vd);
213
if (a->z) {
214
tcg_gen_movi_i64(vm, 0);
215
} else {
216
- neon_load_reg64(vm, a->vm);
217
+ vfp_load_reg64(vm, a->vm);
218
}
219
220
if (a->e) {
221
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
222
tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
223
vd = tcg_temp_new_i64();
224
gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
225
- neon_store_reg64(vd, a->vd);
226
+ vfp_store_reg64(vd, a->vd);
227
tcg_temp_free_i32(ahp_mode);
228
tcg_temp_free_ptr(fpst);
229
tcg_temp_free_i32(tmp);
230
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
231
tmp = tcg_temp_new_i32();
232
vm = tcg_temp_new_i64();
233
234
- neon_load_reg64(vm, a->vm);
235
+ vfp_load_reg64(vm, a->vm);
236
gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
237
tcg_temp_free_i64(vm);
238
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
239
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
240
}
241
242
tmp = tcg_temp_new_i64();
243
- neon_load_reg64(tmp, a->vm);
244
+ vfp_load_reg64(tmp, a->vm);
245
fpst = fpstatus_ptr(FPST_FPCR);
246
gen_helper_rintd(tmp, tmp, fpst);
247
- neon_store_reg64(tmp, a->vd);
248
+ vfp_store_reg64(tmp, a->vd);
249
tcg_temp_free_ptr(fpst);
250
tcg_temp_free_i64(tmp);
251
return true;
252
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
253
}
254
255
tmp = tcg_temp_new_i64();
256
- neon_load_reg64(tmp, a->vm);
257
+ vfp_load_reg64(tmp, a->vm);
258
fpst = fpstatus_ptr(FPST_FPCR);
259
tcg_rmode = tcg_const_i32(float_round_to_zero);
260
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
261
gen_helper_rintd(tmp, tmp, fpst);
262
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
263
- neon_store_reg64(tmp, a->vd);
264
+ vfp_store_reg64(tmp, a->vd);
265
tcg_temp_free_ptr(fpst);
266
tcg_temp_free_i64(tmp);
267
tcg_temp_free_i32(tcg_rmode);
268
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
269
}
270
271
tmp = tcg_temp_new_i64();
272
- neon_load_reg64(tmp, a->vm);
273
+ vfp_load_reg64(tmp, a->vm);
274
fpst = fpstatus_ptr(FPST_FPCR);
275
gen_helper_rintd_exact(tmp, tmp, fpst);
276
- neon_store_reg64(tmp, a->vd);
277
+ vfp_store_reg64(tmp, a->vd);
278
tcg_temp_free_ptr(fpst);
279
tcg_temp_free_i64(tmp);
280
return true;
281
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
282
vd = tcg_temp_new_i64();
283
vfp_load_reg32(vm, a->vm);
284
gen_helper_vfp_fcvtds(vd, vm, cpu_env);
285
- neon_store_reg64(vd, a->vd);
286
+ vfp_store_reg64(vd, a->vd);
287
tcg_temp_free_i32(vm);
288
tcg_temp_free_i64(vd);
289
return true;
290
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
291
292
vd = tcg_temp_new_i32();
293
vm = tcg_temp_new_i64();
294
- neon_load_reg64(vm, a->vm);
295
+ vfp_load_reg64(vm, a->vm);
296
gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
297
vfp_store_reg32(vd, a->vd);
298
tcg_temp_free_i32(vd);
299
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
300
/* u32 -> f64 */
301
gen_helper_vfp_uitod(vd, vm, fpst);
302
}
303
- neon_store_reg64(vd, a->vd);
304
+ vfp_store_reg64(vd, a->vd);
305
tcg_temp_free_i32(vm);
306
tcg_temp_free_i64(vd);
307
tcg_temp_free_ptr(fpst);
308
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
309
310
vm = tcg_temp_new_i64();
311
vd = tcg_temp_new_i32();
312
- neon_load_reg64(vm, a->vm);
313
+ vfp_load_reg64(vm, a->vm);
314
gen_helper_vjcvt(vd, vm, cpu_env);
315
vfp_store_reg32(vd, a->vd);
316
tcg_temp_free_i64(vm);
317
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
318
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
319
320
vd = tcg_temp_new_i64();
321
- neon_load_reg64(vd, a->vd);
322
+ vfp_load_reg64(vd, a->vd);
323
324
fpst = fpstatus_ptr(FPST_FPCR);
325
shift = tcg_const_i32(frac_bits);
326
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
327
g_assert_not_reached();
328
}
329
330
- neon_store_reg64(vd, a->vd);
331
+ vfp_store_reg64(vd, a->vd);
332
tcg_temp_free_i64(vd);
333
tcg_temp_free_i32(shift);
334
tcg_temp_free_ptr(fpst);
335
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
336
fpst = fpstatus_ptr(FPST_FPCR);
337
vm = tcg_temp_new_i64();
338
vd = tcg_temp_new_i32();
339
- neon_load_reg64(vm, a->vm);
340
+ vfp_load_reg64(vm, a->vm);
341
342
if (a->s) {
343
if (a->rz) {
344
--
345
2.20.1
346
347
diff view generated by jsdifflib
New patch
[PULL 10/26] target/arm: Simplify do_long_3d and do_2scalar_long
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
In both cases, we can sink the write-back and perform
4
the accumulate into the normal destination temps.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201030022618.785675-11-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-neon.c.inc | 23 +++++++++--------------
12
1 file changed, 9 insertions(+), 14 deletions(-)
13
14
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-neon.c.inc
17
+++ b/target/arm/translate-neon.c.inc
18
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
19
if (accfn) {
20
tmp = tcg_temp_new_i64();
21
read_neon_element64(tmp, a->vd, 0, MO_64);
22
- accfn(tmp, tmp, rd0);
23
- write_neon_element64(tmp, a->vd, 0, MO_64);
24
+ accfn(rd0, tmp, rd0);
25
read_neon_element64(tmp, a->vd, 1, MO_64);
26
- accfn(tmp, tmp, rd1);
27
- write_neon_element64(tmp, a->vd, 1, MO_64);
28
+ accfn(rd1, tmp, rd1);
29
tcg_temp_free_i64(tmp);
30
- } else {
31
- write_neon_element64(rd0, a->vd, 0, MO_64);
32
- write_neon_element64(rd1, a->vd, 1, MO_64);
33
}
34
35
+ write_neon_element64(rd0, a->vd, 0, MO_64);
36
+ write_neon_element64(rd1, a->vd, 1, MO_64);
37
tcg_temp_free_i64(rd0);
38
tcg_temp_free_i64(rd1);
39
40
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
41
if (accfn) {
42
TCGv_i64 t64 = tcg_temp_new_i64();
43
read_neon_element64(t64, a->vd, 0, MO_64);
44
- accfn(t64, t64, rn0_64);
45
- write_neon_element64(t64, a->vd, 0, MO_64);
46
+ accfn(rn0_64, t64, rn0_64);
47
read_neon_element64(t64, a->vd, 1, MO_64);
48
- accfn(t64, t64, rn1_64);
49
- write_neon_element64(t64, a->vd, 1, MO_64);
50
+ accfn(rn1_64, t64, rn1_64);
51
tcg_temp_free_i64(t64);
52
- } else {
53
- write_neon_element64(rn0_64, a->vd, 0, MO_64);
54
- write_neon_element64(rn1_64, a->vd, 1, MO_64);
55
}
56
+
57
+ write_neon_element64(rn0_64, a->vd, 0, MO_64);
58
+ write_neon_element64(rn1_64, a->vd, 1, MO_64);
59
tcg_temp_free_i64(rn0_64);
60
tcg_temp_free_i64(rn1_64);
61
return true;
62
--
63
2.20.1
64
65
diff view generated by jsdifflib
New patch
[PULL 11/26] target/arm: Improve do_prewiden_3d
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
We can use proper widening loads to extend 32-bit inputs,
4
and skip the "widenfn" step.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201030022618.785675-12-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate.c | 6 +++
12
target/arm/translate-neon.c.inc | 66 ++++++++++++++++++---------------
13
2 files changed, 43 insertions(+), 29 deletions(-)
14
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
18
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
20
long off = neon_element_offset(reg, ele, memop);
21
22
switch (memop) {
23
+ case MO_SL:
24
+ tcg_gen_ld32s_i64(dest, cpu_env, off);
25
+ break;
26
+ case MO_UL:
27
+ tcg_gen_ld32u_i64(dest, cpu_env, off);
28
+ break;
29
case MO_Q:
30
tcg_gen_ld_i64(dest, cpu_env, off);
31
break;
32
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/translate-neon.c.inc
35
+++ b/target/arm/translate-neon.c.inc
36
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
37
static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
38
NeonGenWidenFn *widenfn,
39
NeonGenTwo64OpFn *opfn,
40
- bool src1_wide)
41
+ int src1_mop, int src2_mop)
42
{
43
/* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */
44
TCGv_i64 rn0_64, rn1_64, rm_64;
45
- TCGv_i32 rm;
46
47
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
48
return false;
49
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
50
return false;
51
}
52
53
- if (!widenfn || !opfn) {
54
+ if (!opfn) {
55
/* size == 3 case, which is an entirely different insn group */
56
return false;
57
}
58
59
- if ((a->vd & 1) || (src1_wide && (a->vn & 1))) {
60
+ if ((a->vd & 1) || (src1_mop == MO_Q && (a->vn & 1))) {
61
return false;
62
}
63
64
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
65
rn1_64 = tcg_temp_new_i64();
66
rm_64 = tcg_temp_new_i64();
67
68
- if (src1_wide) {
69
- read_neon_element64(rn0_64, a->vn, 0, MO_64);
70
+ if (src1_mop >= 0) {
71
+ read_neon_element64(rn0_64, a->vn, 0, src1_mop);
72
} else {
73
TCGv_i32 tmp = tcg_temp_new_i32();
74
read_neon_element32(tmp, a->vn, 0, MO_32);
75
widenfn(rn0_64, tmp);
76
tcg_temp_free_i32(tmp);
77
}
78
- rm = tcg_temp_new_i32();
79
- read_neon_element32(rm, a->vm, 0, MO_32);
80
+ if (src2_mop >= 0) {
81
+ read_neon_element64(rm_64, a->vm, 0, src2_mop);
82
+ } else {
83
+ TCGv_i32 tmp = tcg_temp_new_i32();
84
+ read_neon_element32(tmp, a->vm, 0, MO_32);
85
+ widenfn(rm_64, tmp);
86
+ tcg_temp_free_i32(tmp);
87
+ }
88
89
- widenfn(rm_64, rm);
90
- tcg_temp_free_i32(rm);
91
opfn(rn0_64, rn0_64, rm_64);
92
93
/*
94
* Load second pass inputs before storing the first pass result, to
95
* avoid incorrect results if a narrow input overlaps with the result.
96
*/
97
- if (src1_wide) {
98
- read_neon_element64(rn1_64, a->vn, 1, MO_64);
99
+ if (src1_mop >= 0) {
100
+ read_neon_element64(rn1_64, a->vn, 1, src1_mop);
101
} else {
102
TCGv_i32 tmp = tcg_temp_new_i32();
103
read_neon_element32(tmp, a->vn, 1, MO_32);
104
widenfn(rn1_64, tmp);
105
tcg_temp_free_i32(tmp);
106
}
107
- rm = tcg_temp_new_i32();
108
- read_neon_element32(rm, a->vm, 1, MO_32);
109
+ if (src2_mop >= 0) {
110
+ read_neon_element64(rm_64, a->vm, 1, src2_mop);
111
+ } else {
112
+ TCGv_i32 tmp = tcg_temp_new_i32();
113
+ read_neon_element32(tmp, a->vm, 1, MO_32);
114
+ widenfn(rm_64, tmp);
115
+ tcg_temp_free_i32(tmp);
116
+ }
117
118
write_neon_element64(rn0_64, a->vd, 0, MO_64);
119
120
- widenfn(rm_64, rm);
121
- tcg_temp_free_i32(rm);
122
opfn(rn1_64, rn1_64, rm_64);
123
write_neon_element64(rn1_64, a->vd, 1, MO_64);
124
125
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
126
return true;
127
}
128
129
-#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \
130
+#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN) \
131
static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
132
{ \
133
static NeonGenWidenFn * const widenfn[] = { \
134
gen_helper_neon_widen_##S##8, \
135
gen_helper_neon_widen_##S##16, \
136
- tcg_gen_##EXT##_i32_i64, \
137
- NULL, \
138
+ NULL, NULL, \
139
}; \
140
static NeonGenTwo64OpFn * const addfn[] = { \
141
gen_helper_neon_##OP##l_u16, \
142
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
143
tcg_gen_##OP##_i64, \
144
NULL, \
145
}; \
146
- return do_prewiden_3d(s, a, widenfn[a->size], \
147
- addfn[a->size], SRC1WIDE); \
148
+ int narrow_mop = a->size == MO_32 ? MO_32 | SIGN : -1; \
149
+ return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \
150
+ SRC1WIDE ? MO_Q : narrow_mop, \
151
+ narrow_mop); \
152
}
153
154
-DO_PREWIDEN(VADDL_S, s, ext, add, false)
155
-DO_PREWIDEN(VADDL_U, u, extu, add, false)
156
-DO_PREWIDEN(VSUBL_S, s, ext, sub, false)
157
-DO_PREWIDEN(VSUBL_U, u, extu, sub, false)
158
-DO_PREWIDEN(VADDW_S, s, ext, add, true)
159
-DO_PREWIDEN(VADDW_U, u, extu, add, true)
160
-DO_PREWIDEN(VSUBW_S, s, ext, sub, true)
161
-DO_PREWIDEN(VSUBW_U, u, extu, sub, true)
162
+DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN)
163
+DO_PREWIDEN(VADDL_U, u, add, false, 0)
164
+DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN)
165
+DO_PREWIDEN(VSUBL_U, u, sub, false, 0)
166
+DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN)
167
+DO_PREWIDEN(VADDW_U, u, add, true, 0)
168
+DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN)
169
+DO_PREWIDEN(VSUBW_U, u, sub, true, 0)
170
171
static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
172
NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn)
173
--
174
2.20.1
175
176
diff view generated by jsdifflib
New patch
[PULL 12/26] target/arm: Fix float16 pairwise Neon ops on big-endian hosts
1
In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error
2
meant we were using the H4() address swizzler macro rather than the
3
H2() which is required for 2-byte data. This had no effect on
4
little-endian hosts but meant we put the result data into the
5
destination Dreg in the wrong order on big-endian hosts.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20201028191712.4910-2-peter.maydell@linaro.org
11
---
12
target/arm/vec_helper.c | 8 ++++----
13
1 file changed, 4 insertions(+), 4 deletions(-)
14
15
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vec_helper.c
18
+++ b/target/arm/vec_helper.c
19
@@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t)
20
r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst); \
21
r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst); \
22
\
23
- d[H4(0)] = r0; \
24
- d[H4(1)] = r1; \
25
- d[H4(2)] = r2; \
26
- d[H4(3)] = r3; \
27
+ d[H2(0)] = r0; \
28
+ d[H2(1)] = r1; \
29
+ d[H2(2)] = r2; \
30
+ d[H2(3)] = r3; \
31
}
32
33
DO_NEON_PAIRWISE(neon_padd, add)
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
New patch
[PULL 13/26] target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts
1
The helper functions for performing the udot/sdot operations against
2
a scalar were not using an address-swizzling macro when converting
3
the index of the scalar element into a pointer into the vm array.
4
This had no effect on little-endian hosts but meant we generated
5
incorrect results on big-endian hosts.
1
6
7
For these insns, the index is indexing over group of 4 8-bit values,
8
so 32 bits per indexed entity, and H4() is therefore what we want.
9
(For Neon the only possible input indexes are 0 and 1.)
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20201028191712.4910-3-peter.maydell@linaro.org
15
---
16
target/arm/vec_helper.c | 4 ++--
17
1 file changed, 2 insertions(+), 2 deletions(-)
18
19
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/vec_helper.c
22
+++ b/target/arm/vec_helper.c
23
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
24
intptr_t index = simd_data(desc);
25
uint32_t *d = vd;
26
int8_t *n = vn;
27
- int8_t *m_indexed = (int8_t *)vm + index * 4;
28
+ int8_t *m_indexed = (int8_t *)vm + H4(index) * 4;
29
30
/* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
31
* Otherwise opr_sz is a multiple of 16.
32
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
33
intptr_t index = simd_data(desc);
34
uint32_t *d = vd;
35
uint8_t *n = vn;
36
- uint8_t *m_indexed = (uint8_t *)vm + index * 4;
37
+ uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4;
38
39
/* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
40
* Otherwise opr_sz is a multiple of 16.
41
--
42
2.20.1
43
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 5/6] hw/arm/nrf51_soc: Connect UART to nRF51 SoC
[PULL 14/26] target/arm: fix handling of HCR.FB
1
From: Julia Suvorova via Qemu-devel <qemu-devel@nongnu.org>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
Wire up nRF51 UART in the corresponding SoC.
3
HCR should be applied when NS is set, not when it is cleared.
4
4
5
Signed-off-by: Julia Suvorova <jusual@mail.ru>
5
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
6
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
8
---
11
include/hw/arm/nrf51_soc.h | 3 +++
9
target/arm/helper.c | 5 ++---
12
hw/arm/microbit.c | 2 ++
10
1 file changed, 2 insertions(+), 3 deletions(-)
13
hw/arm/nrf51_soc.c | 20 ++++++++++++++++++++
14
3 files changed, 25 insertions(+)
15
11
16
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/nrf51_soc.h
14
--- a/target/arm/helper.c
19
+++ b/include/hw/arm/nrf51_soc.h
15
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
21
17
22
#include "hw/sysbus.h"
18
/*
23
#include "hw/arm/armv7m.h"
19
* Non-IS variants of TLB operations are upgraded to
24
+#include "hw/char/nrf51_uart.h"
20
- * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
25
21
+ * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
26
#define TYPE_NRF51_SOC "nrf51-soc"
22
* force broadcast of these operations.
27
#define NRF51_SOC(obj) \
23
*/
28
@@ -XXX,XX +XXX,XX @@ typedef struct NRF51State {
24
static bool tlb_force_broadcast(CPUARMState *env)
29
/*< public >*/
30
ARMv7MState cpu;
31
32
+ NRF51UARTState uart;
33
+
34
MemoryRegion iomem;
35
MemoryRegion sram;
36
MemoryRegion flash;
37
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/microbit.c
40
+++ b/hw/arm/microbit.c
41
@@ -XXX,XX +XXX,XX @@
42
#include "qapi/error.h"
43
#include "hw/boards.h"
44
#include "hw/arm/arm.h"
45
+#include "sysemu/sysemu.h"
46
#include "exec/address-spaces.h"
47
48
#include "hw/arm/nrf51_soc.h"
49
@@ -XXX,XX +XXX,XX @@ static void microbit_init(MachineState *machine)
50
51
sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51),
52
TYPE_NRF51_SOC);
53
+ qdev_prop_set_chr(DEVICE(&s->nrf51), "serial0", serial_hd(0));
54
object_property_set_link(soc, OBJECT(system_memory), "memory",
55
&error_fatal);
56
object_property_set_bool(soc, true, "realized", &error_fatal);
57
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/nrf51_soc.c
60
+++ b/hw/arm/nrf51_soc.c
61
@@ -XXX,XX +XXX,XX @@
62
#define NRF51822_FLASH_SIZE (256 * 1024)
63
#define NRF51822_SRAM_SIZE (16 * 1024)
64
65
+#define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
66
+
67
static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
68
{
25
{
69
NRF51State *s = NRF51_SOC(dev_soc);
26
- return (env->cp15.hcr_el2 & HCR_FB) &&
70
+ MemoryRegion *mr;
27
- arm_current_el(env) == 1 && arm_is_secure_below_el3(env);
71
Error *err = NULL;
28
+ return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB);
72
73
if (!s->board_memory) {
74
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
75
}
76
memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
77
78
+ /* UART */
79
+ object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
80
+ if (err) {
81
+ error_propagate(errp, err);
82
+ return;
83
+ }
84
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
85
+ memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0);
86
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
87
+ qdev_get_gpio_in(DEVICE(&s->cpu),
88
+ BASE_TO_IRQ(UART_BASE)));
89
+
90
create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
91
create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
92
create_unimplemented_device("nrf51_soc.private",
93
@@ -XXX,XX +XXX,XX @@ static void nrf51_soc_init(Object *obj)
94
qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
95
ARM_CPU_TYPE_NAME("cortex-m0"));
96
qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
97
+
98
+ sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
99
+ TYPE_NRF51_UART);
100
+ object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",
101
+ &error_abort);
102
}
29
}
103
30
104
static Property nrf51_soc_properties[] = {
31
static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
105
--
32
--
106
2.19.1
33
2.20.1
107
34
108
35
diff view generated by jsdifflib
[Qemu-devel] [PULL 6/6] tests/boot-serial-test: Add microbit board testcase
[PULL 15/26] target/arm: fix LORID_EL1 access check
1
From: Julia Suvorova via Qemu-devel <qemu-devel@nongnu.org>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
New mini-kernel test for nRF51 SoC UART.
3
Secure mode is not exempted from checking SCR_EL3.TLOR, and in the
4
future HCR_EL2.TLOR when S-EL2 is enabled.
4
5
5
Signed-off-by: Julia Suvorova <jusual@mail.ru>
6
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
6
Acked-by: Thomas Huth <thuth@redhat.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
9
---
10
tests/boot-serial-test.c | 19 +++++++++++++++++++
10
target/arm/helper.c | 19 +++++--------------
11
1 file changed, 19 insertions(+)
11
1 file changed, 5 insertions(+), 14 deletions(-)
12
12
13
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/boot-serial-test.c
15
--- a/target/arm/helper.c
16
+++ b/tests/boot-serial-test.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_aarch64[] = {
17
@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
18
0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */
18
#endif
19
};
19
20
20
/* Shared logic between LORID and the rest of the LOR* registers.
21
+static const uint8_t kernel_nrf51[] = {
21
- * Secure state has already been delt with.
22
+ 0x00, 0x00, 0x00, 0x00, /* Stack top address */
22
+ * Secure state exclusion has already been dealt with.
23
+ 0x09, 0x00, 0x00, 0x00, /* Reset handler address */
23
*/
24
+ 0x04, 0x4a, /* ldr r2, [pc, #16] Get ENABLE */
24
-static CPAccessResult access_lor_ns(CPUARMState *env)
25
+ 0x04, 0x21, /* movs r1, #4 */
25
+static CPAccessResult access_lor_ns(CPUARMState *env,
26
+ 0x11, 0x60, /* str r1, [r2] */
26
+ const ARMCPRegInfo *ri, bool isread)
27
+ 0x04, 0x4a, /* ldr r2, [pc, #16] Get STARTTX */
27
{
28
+ 0x01, 0x21, /* movs r1, #1 */
28
int el = arm_current_el(env);
29
+ 0x11, 0x60, /* str r1, [r2] */
29
30
+ 0x03, 0x4a, /* ldr r2, [pc, #12] Get TXD */
30
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_ns(CPUARMState *env)
31
+ 0x54, 0x21, /* movs r1, 'T' */
31
return CP_ACCESS_OK;
32
+ 0x11, 0x60, /* str r1, [r2] */
32
}
33
+ 0xfe, 0xe7, /* b . */
33
34
+ 0x00, 0x25, 0x00, 0x40, /* 0x40002500 = UART ENABLE */
34
-static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri,
35
+ 0x08, 0x20, 0x00, 0x40, /* 0x40002008 = UART STARTTX */
35
- bool isread)
36
+ 0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */
36
-{
37
+};
37
- if (arm_is_secure_below_el3(env)) {
38
+
38
- /* Access ok in secure mode. */
39
typedef struct testdef {
39
- return CP_ACCESS_OK;
40
const char *arch; /* Target architecture */
40
- }
41
const char *machine; /* Name of the machine */
41
- return access_lor_ns(env);
42
@@ -XXX,XX +XXX,XX @@ static testdef_t tests[] = {
42
-}
43
{ "hppa", "hppa", "", "SeaBIOS wants SYSTEM HALT" },
43
-
44
{ "aarch64", "virt", "-cpu cortex-a57", "TT", sizeof(kernel_aarch64),
44
static CPAccessResult access_lor_other(CPUARMState *env,
45
kernel_aarch64 },
45
const ARMCPRegInfo *ri, bool isread)
46
+ { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
46
{
47
47
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env,
48
{ NULL }
48
/* Access denied in secure mode. */
49
return CP_ACCESS_TRAP;
50
}
51
- return access_lor_ns(env);
52
+ return access_lor_ns(env, ri, isread);
53
}
54
55
/*
56
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
57
.type = ARM_CP_CONST, .resetvalue = 0 },
58
{ .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
59
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
60
- .access = PL1_R, .accessfn = access_lorid,
61
+ .access = PL1_R, .accessfn = access_lor_ns,
62
.type = ARM_CP_CONST, .resetvalue = 0 },
63
REGINFO_SENTINEL
49
};
64
};
50
--
65
--
51
2.19.1
66
2.20.1
52
67
53
68
diff view generated by jsdifflib
New patch
[PULL 16/26] disas/capstone: Fix monitor disassembly of >32 bytes
1
If we're using the capstone disassembler, disassembly of a run of
2
instructions more than 32 bytes long disassembles the wrong data for
3
instructions beyond the 32 byte mark:
1
4
5
(qemu) xp /16x 0x100
6
0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000
7
0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000
8
0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574
9
0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000
10
(qemu) xp /16i 0x100
11
0x00000100: 00000005 andeq r0, r0, r5
12
0x00000104: 54410001 strbpl r0, [r1], #-1
13
0x00000108: 00000001 andeq r0, r0, r1
14
0x0000010c: 00001000 andeq r1, r0, r0
15
0x00000110: 00000000 andeq r0, r0, r0
16
0x00000114: 00000004 andeq r0, r0, r4
17
0x00000118: 54410002 strbpl r0, [r1], #-2
18
0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
19
0x00000120: 54410001 strbpl r0, [r1], #-1
20
0x00000124: 00000001 andeq r0, r0, r1
21
0x00000128: 00001000 andeq r1, r0, r0
22
0x0000012c: 00000000 andeq r0, r0, r0
23
0x00000130: 00000004 andeq r0, r0, r4
24
0x00000134: 54410002 strbpl r0, [r1], #-2
25
0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
26
0x0000013c: 00000000 andeq r0, r0, r0
27
28
Here the disassembly of 0x120..0x13f is using the data that is in
29
0x104..0x123.
30
31
This is caused by passing the wrong value to the read_memory_func().
32
The intention is that at this point in the loop the 'cap_buf' buffer
33
already contains 'csize' bytes of data for the instruction at guest
34
addr 'pc', and we want to read in an extra 'tsize' bytes. Those
35
extra bytes are therefore at 'pc + csize', not 'pc'. On the first
36
time through the loop 'csize' happens to be zero, so the initial read
37
of 32 bytes into cap_buf is correct and as long as the disassembly
38
never needs to read more data we return the correct information.
39
40
Use the correct guest address in the call to read_memory_func().
41
42
Cc: qemu-stable@nongnu.org
43
Fixes: https://bugs.launchpad.net/qemu/+bug/1900779
44
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
45
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
46
Message-id: 20201022132445.25039-1-peter.maydell@linaro.org
47
---
48
disas/capstone.c | 2 +-
49
1 file changed, 1 insertion(+), 1 deletion(-)
50
51
diff --git a/disas/capstone.c b/disas/capstone.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/disas/capstone.c
54
+++ b/disas/capstone.c
55
@@ -XXX,XX +XXX,XX @@ bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count)
56
57
/* Make certain that we can make progress. */
58
assert(tsize != 0);
59
- info->read_memory_func(pc, cap_buf + csize, tsize, info);
60
+ info->read_memory_func(pc + csize, cap_buf + csize, tsize, info);
61
csize += tsize;
62
63
if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
64
--
65
2.20.1
66
67
diff view generated by jsdifflib
New patch
[PULL 17/26] hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic.
4
This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN):
5
6
CID 1432363 (#1 of 1): Unintentional integer overflow:
7
8
overflow_before_widen:
9
Potentially overflowing expression 1 << scale with type int
10
(32 bits, signed) is evaluated using 32-bit arithmetic, and
11
then used in a context that expects an expression of type
12
hwaddr (64 bits, unsigned).
13
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Acked-by: Eric Auger <eric.auger@redhat.com>
16
Message-id: 20201030144617.1535064-1-philmd@redhat.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/arm/smmuv3.c | 3 ++-
21
1 file changed, 2 insertions(+), 1 deletion(-)
22
23
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/smmuv3.c
26
+++ b/hw/arm/smmuv3.c
27
@@ -XXX,XX +XXX,XX @@
28
*/
29
30
#include "qemu/osdep.h"
31
+#include "qemu/bitops.h"
32
#include "hw/irq.h"
33
#include "hw/sysbus.h"
34
#include "migration/vmstate.h"
35
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
36
scale = CMD_SCALE(cmd);
37
num = CMD_NUM(cmd);
38
ttl = CMD_TTL(cmd);
39
- num_pages = (num + 1) * (1 << (scale));
40
+ num_pages = (num + 1) * BIT_ULL(scale);
41
}
42
43
if (type == SMMU_CMD_TLBI_NH_VA) {
44
--
45
2.20.1
46
47
diff view generated by jsdifflib
New patch
[PULL 18/26] hw/arm/boot: fix SVE for EL3 direct kernel boot
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
1
2
3
When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so
4
that SVE will not trap to EL3.
5
6
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201030151541.11976-1-remi@remlab.net
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/boot.c | 3 +++
12
1 file changed, 3 insertions(+)
13
14
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/boot.c
17
+++ b/hw/arm/boot.c
18
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
19
if (cpu_isar_feature(aa64_mte, cpu)) {
20
env->cp15.scr_el3 |= SCR_ATA;
21
}
22
+ if (cpu_isar_feature(aa64_sve, cpu)) {
23
+ env->cp15.cptr_el[3] |= CPTR_EZ;
24
+ }
25
/* AArch64 kernels never boot in secure mode */
26
assert(!info->secure_boot);
27
/* This hook is only supported for AArch32 currently:
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/6] hw/arm: versal: Add a model of Xilinx Versal SoC
[PULL 19/26] hw/display/omap_lcdc: Fix potential NULL pointer dereference
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: AlexChen <alex.chen@huawei.com>
2
2
3
Add a model of Xilinx Versal SoC.
3
In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before
4
being check if it is valid, which may lead to NULL pointer dereference.
5
So move the assignment to surface after checking that the omap_lcd is valid
6
and move surface_bits_per_pixel(surface) to after the surface assignment.
4
7
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Reported-by: Euler Robot <euler.robot@huawei.com>
9
Signed-off-by: AlexChen <alex.chen@huawei.com>
10
Message-id: 5F9CDB8A.9000001@huawei.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
13
---
9
hw/arm/Makefile.objs | 1 +
14
hw/display/omap_lcdc.c | 10 +++++++---
10
include/hw/arm/xlnx-versal.h | 122 +++++++++++
15
1 file changed, 7 insertions(+), 3 deletions(-)
11
hw/arm/xlnx-versal.c | 323 ++++++++++++++++++++++++++++
12
default-configs/aarch64-softmmu.mak | 1 +
13
4 files changed, 447 insertions(+)
14
create mode 100644 include/hw/arm/xlnx-versal.h
15
create mode 100644 hw/arm/xlnx-versal.c
16
16
17
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
17
diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
18
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/Makefile.objs
19
--- a/hw/display/omap_lcdc.c
20
+++ b/hw/arm/Makefile.objs
20
+++ b/hw/display/omap_lcdc.c
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
21
@@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
22
obj-$(CONFIG_RASPI) += bcm2835_peripherals.o bcm2836.o raspi.o
22
static void omap_update_display(void *opaque)
23
obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
23
{
24
obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o
24
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
25
+obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o
25
- DisplaySurface *surface = qemu_console_surface(omap_lcd->con);
26
obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
26
+ DisplaySurface *surface;
27
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
27
draw_line_func draw_line;
28
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
28
int size, height, first, last;
29
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
29
int width, linesize, step, bpp, frame_offset;
30
new file mode 100644
30
hwaddr frame_base;
31
index XXXXXXX..XXXXXXX
31
32
--- /dev/null
32
- if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable ||
33
+++ b/include/hw/arm/xlnx-versal.h
33
- !surface_bits_per_pixel(surface)) {
34
@@ -XXX,XX +XXX,XX @@
34
+ if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) {
35
+/*
35
+ return;
36
+ * Model of the Xilinx Versal
37
+ *
38
+ * Copyright (c) 2018 Xilinx Inc.
39
+ * Written by Edgar E. Iglesias
40
+ *
41
+ * This program is free software; you can redistribute it and/or modify
42
+ * it under the terms of the GNU General Public License version 2 or
43
+ * (at your option) any later version.
44
+ */
45
+
46
+#ifndef XLNX_VERSAL_H
47
+#define XLNX_VERSAL_H
48
+
49
+#include "hw/sysbus.h"
50
+#include "hw/arm/arm.h"
51
+#include "hw/intc/arm_gicv3.h"
52
+
53
+#define TYPE_XLNX_VERSAL "xlnx-versal"
54
+#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
55
+
56
+#define XLNX_VERSAL_NR_ACPUS 2
57
+#define XLNX_VERSAL_NR_UARTS 2
58
+#define XLNX_VERSAL_NR_GEMS 2
59
+#define XLNX_VERSAL_NR_IRQS 256
60
+
61
+typedef struct Versal {
62
+ /*< private >*/
63
+ SysBusDevice parent_obj;
64
+
65
+ /*< public >*/
66
+ struct {
67
+ struct {
68
+ MemoryRegion mr;
69
+ ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
70
+ GICv3State gic;
71
+ } apu;
72
+ } fpd;
73
+
74
+ MemoryRegion mr_ps;
75
+
76
+ struct {
77
+ /* 4 ranges to access DDR. */
78
+ MemoryRegion mr_ddr_ranges[4];
79
+ } noc;
80
+
81
+ struct {
82
+ MemoryRegion mr_ocm;
83
+
84
+ struct {
85
+ SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
86
+ SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
87
+ } iou;
88
+ } lpd;
89
+
90
+ struct {
91
+ MemoryRegion *mr_ddr;
92
+ uint32_t psci_conduit;
93
+ } cfg;
94
+} Versal;
95
+
96
+/* Memory-map and IRQ definitions. Copied a subset from
97
+ * auto-generated files. */
98
+
99
+#define VERSAL_GIC_MAINT_IRQ 9
100
+#define VERSAL_TIMER_VIRT_IRQ 11
101
+#define VERSAL_TIMER_S_EL1_IRQ 13
102
+#define VERSAL_TIMER_NS_EL1_IRQ 14
103
+#define VERSAL_TIMER_NS_EL2_IRQ 10
104
+
105
+#define VERSAL_UART0_IRQ_0 18
106
+#define VERSAL_UART1_IRQ_0 19
107
+#define VERSAL_GEM0_IRQ_0 56
108
+#define VERSAL_GEM0_WAKE_IRQ_0 57
109
+#define VERSAL_GEM1_IRQ_0 58
110
+#define VERSAL_GEM1_WAKE_IRQ_0 59
111
+
112
+/* Architecturally eserved IRQs suitable for virtualization. */
113
+#define VERSAL_RSVD_HIGH_IRQ_FIRST 160
114
+#define VERSAL_RSVD_HIGH_IRQ_LAST 255
115
+
116
+#define MM_TOP_RSVD 0xa0000000U
117
+#define MM_TOP_RSVD_SIZE 0x4000000
118
+#define MM_GIC_APU_DIST_MAIN 0xf9000000U
119
+#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
120
+#define MM_GIC_APU_REDIST_0 0xf9080000U
121
+#define MM_GIC_APU_REDIST_0_SIZE 0x80000
122
+
123
+#define MM_UART0 0xff000000U
124
+#define MM_UART0_SIZE 0x10000
125
+#define MM_UART1 0xff010000U
126
+#define MM_UART1_SIZE 0x10000
127
+
128
+#define MM_GEM0 0xff0c0000U
129
+#define MM_GEM0_SIZE 0x10000
130
+#define MM_GEM1 0xff0d0000U
131
+#define MM_GEM1_SIZE 0x10000
132
+
133
+#define MM_OCM 0xfffc0000U
134
+#define MM_OCM_SIZE 0x40000
135
+
136
+#define MM_TOP_DDR 0x0
137
+#define MM_TOP_DDR_SIZE 0x80000000U
138
+#define MM_TOP_DDR_2 0x800000000ULL
139
+#define MM_TOP_DDR_2_SIZE 0x800000000ULL
140
+#define MM_TOP_DDR_3 0xc000000000ULL
141
+#define MM_TOP_DDR_3_SIZE 0x4000000000ULL
142
+#define MM_TOP_DDR_4 0x10000000000ULL
143
+#define MM_TOP_DDR_4_SIZE 0xb780000000ULL
144
+
145
+#define MM_PSM_START 0xffc80000U
146
+#define MM_PSM_END 0xffcf0000U
147
+
148
+#define MM_CRL 0xff5e0000U
149
+#define MM_CRL_SIZE 0x300000
150
+#define MM_IOU_SCNTR 0xff130000U
151
+#define MM_IOU_SCNTR_SIZE 0x10000
152
+#define MM_IOU_SCNTRS 0xff140000U
153
+#define MM_IOU_SCNTRS_SIZE 0x10000
154
+#define MM_FPD_CRF 0xfd1a0000U
155
+#define MM_FPD_CRF_SIZE 0x140000
156
+#endif
157
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
158
new file mode 100644
159
index XXXXXXX..XXXXXXX
160
--- /dev/null
161
+++ b/hw/arm/xlnx-versal.c
162
@@ -XXX,XX +XXX,XX @@
163
+/*
164
+ * Xilinx Versal SoC model.
165
+ *
166
+ * Copyright (c) 2018 Xilinx Inc.
167
+ * Written by Edgar E. Iglesias
168
+ *
169
+ * This program is free software; you can redistribute it and/or modify
170
+ * it under the terms of the GNU General Public License version 2 or
171
+ * (at your option) any later version.
172
+ */
173
+
174
+#include "qemu/osdep.h"
175
+#include "qapi/error.h"
176
+#include "qemu-common.h"
177
+#include "qemu/log.h"
178
+#include "hw/sysbus.h"
179
+#include "net/net.h"
180
+#include "sysemu/sysemu.h"
181
+#include "sysemu/kvm.h"
182
+#include "hw/arm/arm.h"
183
+#include "kvm_arm.h"
184
+#include "hw/misc/unimp.h"
185
+#include "hw/intc/arm_gicv3_common.h"
186
+#include "hw/arm/xlnx-versal.h"
187
+
188
+#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
189
+#define GEM_REVISION 0x40070106
190
+
191
+static void versal_create_apu_cpus(Versal *s)
192
+{
193
+ int i;
194
+
195
+ for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
196
+ Object *obj;
197
+ char *name;
198
+
199
+ obj = object_new(XLNX_VERSAL_ACPU_TYPE);
200
+ if (!obj) {
201
+ /* Secondary CPUs start in PSCI powered-down state */
202
+ error_report("Unable to create apu.cpu[%d] of type %s",
203
+ i, XLNX_VERSAL_ACPU_TYPE);
204
+ exit(EXIT_FAILURE);
205
+ }
206
+
207
+ name = g_strdup_printf("apu-cpu[%d]", i);
208
+ object_property_add_child(OBJECT(s), name, obj, &error_fatal);
209
+ g_free(name);
210
+
211
+ object_property_set_int(obj, s->cfg.psci_conduit,
212
+ "psci-conduit", &error_abort);
213
+ if (i) {
214
+ object_property_set_bool(obj, true,
215
+ "start-powered-off", &error_abort);
216
+ }
217
+
218
+ object_property_set_int(obj, ARRAY_SIZE(s->fpd.apu.cpu),
219
+ "core-count", &error_abort);
220
+ object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
221
+ &error_abort);
222
+ object_property_set_bool(obj, true, "realized", &error_fatal);
223
+ s->fpd.apu.cpu[i] = ARM_CPU(obj);
224
+ }
225
+}
226
+
227
+static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
228
+{
229
+ static const uint64_t addrs[] = {
230
+ MM_GIC_APU_DIST_MAIN,
231
+ MM_GIC_APU_REDIST_0
232
+ };
233
+ SysBusDevice *gicbusdev;
234
+ DeviceState *gicdev;
235
+ int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu);
236
+ int i;
237
+
238
+ sysbus_init_child_obj(OBJECT(s), "apu-gic",
239
+ &s->fpd.apu.gic, sizeof(s->fpd.apu.gic),
240
+ gicv3_class_name());
241
+ gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic);
242
+ gicdev = DEVICE(&s->fpd.apu.gic);
243
+ qdev_prop_set_uint32(gicdev, "revision", 3);
244
+ qdev_prop_set_uint32(gicdev, "num-cpu", 2);
245
+ qdev_prop_set_uint32(gicdev, "num-irq", XLNX_VERSAL_NR_IRQS + 32);
246
+ qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1);
247
+ qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2);
248
+ qdev_prop_set_bit(gicdev, "has-security-extensions", true);
249
+
250
+ object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized",
251
+ &error_fatal);
252
+
253
+ for (i = 0; i < ARRAY_SIZE(addrs); i++) {
254
+ MemoryRegion *mr;
255
+
256
+ mr = sysbus_mmio_get_region(gicbusdev, i);
257
+ memory_region_add_subregion(&s->fpd.apu.mr, addrs[i], mr);
258
+ }
36
+ }
259
+
37
+
260
+ for (i = 0; i < nr_apu_cpus; i++) {
38
+ surface = qemu_console_surface(omap_lcd->con);
261
+ DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);
39
+ if (!surface_bits_per_pixel(surface)) {
262
+ int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
40
return;
263
+ qemu_irq maint_irq;
41
}
264
+ int ti;
42
265
+ /* Mapping from the output timer irq lines from the CPU to the
266
+ * GIC PPI inputs.
267
+ */
268
+ const int timer_irq[] = {
269
+ [GTIMER_PHYS] = VERSAL_TIMER_NS_EL1_IRQ,
270
+ [GTIMER_VIRT] = VERSAL_TIMER_VIRT_IRQ,
271
+ [GTIMER_HYP] = VERSAL_TIMER_NS_EL2_IRQ,
272
+ [GTIMER_SEC] = VERSAL_TIMER_S_EL1_IRQ,
273
+ };
274
+
275
+ for (ti = 0; ti < ARRAY_SIZE(timer_irq); ti++) {
276
+ qdev_connect_gpio_out(cpudev, ti,
277
+ qdev_get_gpio_in(gicdev,
278
+ ppibase + timer_irq[ti]));
279
+ }
280
+ maint_irq = qdev_get_gpio_in(gicdev,
281
+ ppibase + VERSAL_GIC_MAINT_IRQ);
282
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
283
+ 0, maint_irq);
284
+ sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
285
+ sysbus_connect_irq(gicbusdev, i + nr_apu_cpus,
286
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
287
+ sysbus_connect_irq(gicbusdev, i + 2 * nr_apu_cpus,
288
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
289
+ sysbus_connect_irq(gicbusdev, i + 3 * nr_apu_cpus,
290
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
291
+ }
292
+
293
+ for (i = 0; i < XLNX_VERSAL_NR_IRQS; i++) {
294
+ pic[i] = qdev_get_gpio_in(gicdev, i);
295
+ }
296
+}
297
+
298
+static void versal_create_uarts(Versal *s, qemu_irq *pic)
299
+{
300
+ int i;
301
+
302
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
303
+ static const int irqs[] = { VERSAL_UART0_IRQ_0, VERSAL_UART1_IRQ_0};
304
+ static const uint64_t addrs[] = { MM_UART0, MM_UART1 };
305
+ char *name = g_strdup_printf("uart%d", i);
306
+ DeviceState *dev;
307
+ MemoryRegion *mr;
308
+
309
+ dev = qdev_create(NULL, "pl011");
310
+ s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);
311
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
312
+ object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
313
+ qdev_init_nofail(dev);
314
+
315
+ mr = sysbus_mmio_get_region(s->lpd.iou.uart[i], 0);
316
+ memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
317
+
318
+ sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]);
319
+ g_free(name);
320
+ }
321
+}
322
+
323
+static void versal_create_gems(Versal *s, qemu_irq *pic)
324
+{
325
+ int i;
326
+
327
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
328
+ static const int irqs[] = { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0};
329
+ static const uint64_t addrs[] = { MM_GEM0, MM_GEM1 };
330
+ char *name = g_strdup_printf("gem%d", i);
331
+ NICInfo *nd = &nd_table[i];
332
+ DeviceState *dev;
333
+ MemoryRegion *mr;
334
+
335
+ dev = qdev_create(NULL, "cadence_gem");
336
+ s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);
337
+ object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
338
+ if (nd->used) {
339
+ qemu_check_nic_model(nd, "cadence_gem");
340
+ qdev_set_nic_properties(dev, nd);
341
+ }
342
+ object_property_set_int(OBJECT(s->lpd.iou.gem[i]),
343
+ 2, "num-priority-queues",
344
+ &error_abort);
345
+ object_property_set_link(OBJECT(s->lpd.iou.gem[i]),
346
+ OBJECT(&s->mr_ps), "dma",
347
+ &error_abort);
348
+ qdev_init_nofail(dev);
349
+
350
+ mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);
351
+ memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
352
+
353
+ sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);
354
+ g_free(name);
355
+ }
356
+}
357
+
358
+/* This takes the board allocated linear DDR memory and creates aliases
359
+ * for each split DDR range/aperture on the Versal address map.
360
+ */
361
+static void versal_map_ddr(Versal *s)
362
+{
363
+ uint64_t size = memory_region_size(s->cfg.mr_ddr);
364
+ /* Describes the various split DDR access regions. */
365
+ static const struct {
366
+ uint64_t base;
367
+ uint64_t size;
368
+ } addr_ranges[] = {
369
+ { MM_TOP_DDR, MM_TOP_DDR_SIZE },
370
+ { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
371
+ { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
372
+ { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
373
+ };
374
+ uint64_t offset = 0;
375
+ int i;
376
+
377
+ assert(ARRAY_SIZE(addr_ranges) == ARRAY_SIZE(s->noc.mr_ddr_ranges));
378
+ for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
379
+ char *name;
380
+ uint64_t mapsize;
381
+
382
+ mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
383
+ name = g_strdup_printf("noc-ddr-range%d", i);
384
+ /* Create the MR alias. */
385
+ memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s),
386
+ name, s->cfg.mr_ddr,
387
+ offset, mapsize);
388
+
389
+ /* Map it onto the NoC MR. */
390
+ memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base,
391
+ &s->noc.mr_ddr_ranges[i]);
392
+ offset += mapsize;
393
+ size -= mapsize;
394
+ g_free(name);
395
+ }
396
+}
397
+
398
+static void versal_unimp_area(Versal *s, const char *name,
399
+ MemoryRegion *mr,
400
+ hwaddr base, hwaddr size)
401
+{
402
+ DeviceState *dev = qdev_create(NULL, TYPE_UNIMPLEMENTED_DEVICE);
403
+ MemoryRegion *mr_dev;
404
+
405
+ qdev_prop_set_string(dev, "name", name);
406
+ qdev_prop_set_uint64(dev, "size", size);
407
+ object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
408
+ qdev_init_nofail(dev);
409
+
410
+ mr_dev = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
411
+ memory_region_add_subregion(mr, base, mr_dev);
412
+}
413
+
414
+static void versal_unimp(Versal *s)
415
+{
416
+ versal_unimp_area(s, "psm", &s->mr_ps,
417
+ MM_PSM_START, MM_PSM_END - MM_PSM_START);
418
+ versal_unimp_area(s, "crl", &s->mr_ps,
419
+ MM_CRL, MM_CRL_SIZE);
420
+ versal_unimp_area(s, "crf", &s->mr_ps,
421
+ MM_FPD_CRF, MM_FPD_CRF_SIZE);
422
+ versal_unimp_area(s, "iou-scntr", &s->mr_ps,
423
+ MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
424
+ versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
425
+ MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE);
426
+}
427
+
428
+static void versal_realize(DeviceState *dev, Error **errp)
429
+{
430
+ Versal *s = XLNX_VERSAL(dev);
431
+ qemu_irq pic[XLNX_VERSAL_NR_IRQS];
432
+
433
+ versal_create_apu_cpus(s);
434
+ versal_create_apu_gic(s, pic);
435
+ versal_create_uarts(s, pic);
436
+ versal_create_gems(s, pic);
437
+ versal_map_ddr(s);
438
+ versal_unimp(s);
439
+
440
+ /* Create the On Chip Memory (OCM). */
441
+ memory_region_init_ram(&s->lpd.mr_ocm, OBJECT(s), "ocm",
442
+ MM_OCM_SIZE, &error_fatal);
443
+
444
+ memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
445
+ memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
446
+}
447
+
448
+static void versal_init(Object *obj)
449
+{
450
+ Versal *s = XLNX_VERSAL(obj);
451
+
452
+ memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
453
+ memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
454
+}
455
+
456
+static Property versal_properties[] = {
457
+ DEFINE_PROP_LINK("ddr", Versal, cfg.mr_ddr, TYPE_MEMORY_REGION,
458
+ MemoryRegion *),
459
+ DEFINE_PROP_UINT32("psci-conduit", Versal, cfg.psci_conduit, 0),
460
+ DEFINE_PROP_END_OF_LIST()
461
+};
462
+
463
+static void versal_class_init(ObjectClass *klass, void *data)
464
+{
465
+ DeviceClass *dc = DEVICE_CLASS(klass);
466
+
467
+ dc->realize = versal_realize;
468
+ dc->props = versal_properties;
469
+ /* No VMSD since we haven't got any top-level SoC state to save. */
470
+}
471
+
472
+static const TypeInfo versal_info = {
473
+ .name = TYPE_XLNX_VERSAL,
474
+ .parent = TYPE_SYS_BUS_DEVICE,
475
+ .instance_size = sizeof(Versal),
476
+ .instance_init = versal_init,
477
+ .class_init = versal_class_init,
478
+};
479
+
480
+static void versal_register_types(void)
481
+{
482
+ type_register_static(&versal_info);
483
+}
484
+
485
+type_init(versal_register_types);
486
diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
487
index XXXXXXX..XXXXXXX 100644
488
--- a/default-configs/aarch64-softmmu.mak
489
+++ b/default-configs/aarch64-softmmu.mak
490
@@ -XXX,XX +XXX,XX @@ CONFIG_DDC=y
491
CONFIG_DPCD=y
492
CONFIG_XLNX_ZYNQMP=y
493
CONFIG_XLNX_ZYNQMP_ARM=y
494
+CONFIG_XLNX_VERSAL=y
495
CONFIG_ARM_SMMUV3=y
496
--
43
--
497
2.19.1
44
2.20.1
498
45
499
46
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/6] hw/arm/virt: Set VIRT_COMPAT_3_0 compat
[PULL 20/26] hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
1
From: Eric Auger <eric.auger@redhat.com>
1
From: AlexChen <alex.chen@huawei.com>
2
2
3
We are missing the VIRT_COMPAT_3_0 definition and setting.
3
In exynos4210_fimd_update(), the pointer s is dereferinced before
4
Let's add them.
4
being check if it is valid, which may lead to NULL pointer dereference.
5
So move the assignment to global_width after checking that the s is valid.
5
6
6
Signed-off-by: Eric Auger <eric.auger@redhat.com>
7
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20181024085602.16611-1-eric.auger@redhat.com
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 5F9F8D88.9030102@huawei.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
hw/arm/virt.c | 4 ++++
13
hw/display/exynos4210_fimd.c | 4 +++-
12
1 file changed, 4 insertions(+)
14
1 file changed, 3 insertions(+), 1 deletion(-)
13
15
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt.c
18
--- a/hw/display/exynos4210_fimd.c
17
+++ b/hw/arm/virt.c
19
+++ b/hw/display/exynos4210_fimd.c
18
@@ -XXX,XX +XXX,XX @@ static void virt_machine_3_1_options(MachineClass *mc)
20
@@ -XXX,XX +XXX,XX @@ static void exynos4210_fimd_update(void *opaque)
19
}
21
bool blend = false;
20
DEFINE_VIRT_MACHINE_AS_LATEST(3, 1)
22
uint8_t *host_fb_addr;
21
23
bool is_dirty = false;
22
+#define VIRT_COMPAT_3_0 \
24
- const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
23
+ HW_COMPAT_3_0
25
+ int global_width;
26
27
if (!s || !s->console || !s->enabled ||
28
surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
29
return;
30
}
24
+
31
+
25
static void virt_3_0_instance_init(Object *obj)
32
+ global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
26
{
33
exynos4210_update_resolution(s);
27
virt_3_1_instance_init(obj);
34
surface = qemu_console_surface(s->console);
28
@@ -XXX,XX +XXX,XX @@ static void virt_3_0_instance_init(Object *obj)
29
static void virt_machine_3_0_options(MachineClass *mc)
30
{
31
virt_machine_3_1_options(mc);
32
+ SET_MACHINE_COMPAT(mc, VIRT_COMPAT_3_0);
33
}
34
DEFINE_VIRT_MACHINE(3, 0)
35
35
36
--
36
--
37
2.19.1
37
2.20.1
38
38
39
39
diff view generated by jsdifflib
New patch
[PULL 21/26] target/arm: Get correct MMU index for other-security-state
1
In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to
2
armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el().
3
This is incorrect when the security state being queried is not the
4
current one, because arm_current_el() uses the current security state
5
to determine which of the banked CONTROL.nPRIV bits to look at.
6
The effect was that if (for instance) Secure state was in privileged
7
mode but Non-Secure was not then we would return the wrong MMU index.
1
8
9
The only places where we are using this function in a way that could
10
trigger this bug are for the stack loads during a v8M function-return
11
and for the instruction fetch of a v8M SG insn.
12
13
Fix the bug by expanding out the M-profile version of the
14
arm_current_el() logic inline so it can use the passed in secstate
15
rather than env->v7m.secure.
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20201022164408.13214-1-peter.maydell@linaro.org
20
---
21
target/arm/m_helper.c | 3 ++-
22
1 file changed, 2 insertions(+), 1 deletion(-)
23
24
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/m_helper.c
27
+++ b/target/arm/m_helper.c
28
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
29
/* Return the MMU index for a v7M CPU in the specified security state */
30
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
31
{
32
- bool priv = arm_current_el(env) != 0;
33
+ bool priv = arm_v7m_is_handler_mode(env) ||
34
+ !(env->v7m.control[secstate] & 1);
35
36
return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
37
}
38
--
39
2.20.1
40
41
diff view generated by jsdifflib
New patch
[PULL 22/26] configure: Test that gio libs from pkg-config work
1
On some hosts (eg Ubuntu Bionic) pkg-config returns a set of
2
libraries for gio-2.0 which don't actually work when compiling
3
statically. (Specifically, the returned library string includes
4
-lmount, but not -lblkid which -lmount depends upon, so linking
5
fails due to missing symbols.)
1
6
7
Check that the libraries work, and don't enable gio if they don't,
8
in the same way we do for gnutls.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20200928160402.7961-1-peter.maydell@linaro.org
14
---
15
configure | 10 +++++++++-
16
1 file changed, 9 insertions(+), 1 deletion(-)
17
18
diff --git a/configure b/configure
19
index XXXXXXX..XXXXXXX 100755
20
--- a/configure
21
+++ b/configure
22
@@ -XXX,XX +XXX,XX @@ if test "$static" = yes && test "$mingw32" = yes; then
23
fi
24
25
if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
26
- gio=yes
27
gio_cflags=$($pkg_config --cflags gio-2.0)
28
gio_libs=$($pkg_config --libs gio-2.0)
29
gdbus_codegen=$($pkg_config --variable=gdbus_codegen gio-2.0)
30
if [ ! -x "$gdbus_codegen" ]; then
31
gdbus_codegen=
32
fi
33
+ # Check that the libraries actually work -- Ubuntu 18.04 ships
34
+ # with pkg-config --static --libs data for gio-2.0 that is missing
35
+ # -lblkid and will give a link error.
36
+ write_c_skeleton
37
+ if compile_prog "" "gio_libs" ; then
38
+ gio=yes
39
+ else
40
+ gio=no
41
+ fi
42
else
43
gio=no
44
fi
45
--
46
2.20.1
47
48
diff view generated by jsdifflib
New patch
[PULL 23/26] hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
1
In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt
2
into the GICv3CPUState struct's maintenance_irq field. This will
3
only work if the board happens to have already wired up the CPU
4
maintenance IRQ before the GIC was realized. Unfortunately this is
5
not the case for the 'virt' board, and so the value that gets copied
6
is NULL (since a qemu_irq is really a pointer to an IRQState struct
7
under the hood). The effect is that the CPU interface code never
8
actually raises the maintenance interrupt line.
1
9
10
Instead, since the GICv3CPUState has a pointer to the CPUState, make
11
the dereference at the point where we want to raise the interrupt, to
12
avoid an implicit requirement on board code to wire things up in a
13
particular order.
14
15
Reported-by: Jose Martins <josemartins90@gmail.com>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20201009153904.28529-1-peter.maydell@linaro.org
18
Reviewed-by: Luc Michel <luc@lmichel.fr>
19
---
20
include/hw/intc/arm_gicv3_common.h | 1 -
21
hw/intc/arm_gicv3_cpuif.c | 5 ++---
22
2 files changed, 2 insertions(+), 4 deletions(-)
23
24
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/intc/arm_gicv3_common.h
27
+++ b/include/hw/intc/arm_gicv3_common.h
28
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
29
qemu_irq parent_fiq;
30
qemu_irq parent_virq;
31
qemu_irq parent_vfiq;
32
- qemu_irq maintenance_irq;
33
34
/* Redistributor */
35
uint32_t level; /* Current IRQ level */
36
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/intc/arm_gicv3_cpuif.c
39
+++ b/hw/intc/arm_gicv3_cpuif.c
40
@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
41
int irqlevel = 0;
42
int fiqlevel = 0;
43
int maintlevel = 0;
44
+ ARMCPU *cpu = ARM_CPU(cs->cpu);
45
46
idx = hppvi_index(cs);
47
trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx);
48
@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
49
50
qemu_set_irq(cs->parent_vfiq, fiqlevel);
51
qemu_set_irq(cs->parent_virq, irqlevel);
52
- qemu_set_irq(cs->maintenance_irq, maintlevel);
53
+ qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel);
54
}
55
56
static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
57
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
58
&& cpu->gic_num_lrs) {
59
int j;
60
61
- cs->maintenance_irq = cpu->gicv3_maintenance_interrupt;
62
-
63
cs->num_list_regs = cpu->gic_num_lrs;
64
cs->vpribits = cpu->gic_vpribits;
65
cs->vprebits = cpu->gic_vprebits;
66
--
67
2.20.1
68
69
diff view generated by jsdifflib
New patch
[PULL 24/26] scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments
1
The kerneldoc script currently emits Sphinx markup for a macro with
2
arguments that uses the c:function directive. This is correct for
3
Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow
4
documentation of macros with arguments and c:function is not picky
5
about the syntax of what it is passed. However, in Sphinx 3 the
6
c:macro directive was enhanced to support macros with arguments,
7
and c:function was made more picky about what syntax it accepted.
1
8
9
When kerneldoc is told that it needs to produce output for Sphinx
10
3 or later, make it emit c:function only for functions and c:macro
11
for macros with arguments. We assume that anything with a return
12
type is a function and anything without is a macro.
13
14
This fixes the Sphinx error:
15
16
/home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:155:Error in declarator
17
If declarator-id with parameters (e.g., 'void f(int arg)'):
18
Invalid C declaration: Expected identifier in nested name. [error at 25]
19
DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME)
20
-------------------------^
21
If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'):
22
Error in declarator or parameters
23
Invalid C declaration: Expecting "(" in parameters. [error at 39]
24
DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME)
25
---------------------------------------^
26
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
29
Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
30
Message-id: 20201030174700.7204-2-peter.maydell@linaro.org
31
---
32
scripts/kernel-doc | 18 +++++++++++++++++-
33
1 file changed, 17 insertions(+), 1 deletion(-)
34
35
diff --git a/scripts/kernel-doc b/scripts/kernel-doc
36
index XXXXXXX..XXXXXXX 100755
37
--- a/scripts/kernel-doc
38
+++ b/scripts/kernel-doc
39
@@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) {
40
    output_highlight_rst($args{'purpose'});
41
    $start = "\n\n**Syntax**\n\n ``";
42
} else {
43
-    print ".. c:function:: ";
44
+ if ((split(/\./, $sphinx_version))[0] >= 3) {
45
+ # Sphinx 3 and later distinguish macros and functions and
46
+ # complain if you use c:function with something that's not
47
+ # syntactically valid as a function declaration.
48
+ # We assume that anything with a return type is a function
49
+ # and anything without is a macro.
50
+ if ($args{'functiontype'} ne "") {
51
+ print ".. c:function:: ";
52
+ } else {
53
+ print ".. c:macro:: ";
54
+ }
55
+ } else {
56
+ # Older Sphinx don't support documenting macros that take
57
+ # arguments with c:macro, and don't complain about the use
58
+ # of c:function for this.
59
+ print ".. c:function:: ";
60
+ }
61
}
62
if ($args{'functiontype'} ne "") {
63
    $start .= $args{'functiontype'} . " " . $args{'function'} . " (";
64
--
65
2.20.1
66
67
diff view generated by jsdifflib
New patch
[PULL 25/26] qemu-option-trace.rst.inc: Don't use option:: markup
1
Sphinx 3.2 is pickier than earlier versions about the option:: markup,
2
and complains about our usage in qemu-option-trace.rst:
1
3
4
../../docs/qemu-option-trace.rst.inc:4:Malformed option description
5
'[enable=]PATTERN', should look like "opt", "-opt args", "--opt args",
6
"/opt args" or "+opt args"
7
8
In this file, we're really trying to document the different parts of
9
the top-level --trace option, which qemu-nbd.rst and qemu-img.rst
10
have already introduced with an option:: markup. So it's not right
11
to use option:: here anyway. Switch to a different markup
12
(definition lists) which gives about the same formatted output.
13
14
(Unlike option::, this markup doesn't produce index entries; but
15
at the moment we don't do anything much with indexes anyway, and
16
in any case I think it doesn't make much sense to have individual
17
index entries for the sub-parts of the --trace option.)
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
21
Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
22
Message-id: 20201030174700.7204-3-peter.maydell@linaro.org
23
---
24
docs/qemu-option-trace.rst.inc | 6 +++---
25
1 file changed, 3 insertions(+), 3 deletions(-)
26
27
diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/docs/qemu-option-trace.rst.inc
30
+++ b/docs/qemu-option-trace.rst.inc
31
@@ -XXX,XX +XXX,XX @@
32
33
Specify tracing options.
34
35
-.. option:: [enable=]PATTERN
36
+``[enable=]PATTERN``
37
38
Immediately enable events matching *PATTERN*
39
(either event name or a globbing pattern). This option is only
40
@@ -XXX,XX +XXX,XX @@ Specify tracing options.
41
42
Use :option:`-trace help` to print a list of names of trace points.
43
44
-.. option:: events=FILE
45
+``events=FILE``
46
47
Immediately enable events listed in *FILE*.
48
The file must contain one event name (as listed in the ``trace-events-all``
49
@@ -XXX,XX +XXX,XX @@ Specify tracing options.
50
available if QEMU has been compiled with the ``simple``, ``log`` or
51
``ftrace`` tracing backend.
52
53
-.. option:: file=FILE
54
+``file=FILE``
55
56
Log output traces to *FILE*.
57
This option is only available if QEMU has been compiled with
58
--
59
2.20.1
60
61
diff view generated by jsdifflib
New patch
[PULL 26/26] tests/qtest/npcm7xx_rng-test: Disable randomness tests
1
The randomness tests in the NPCM7xx RNG test fail intermittently
2
but fairly frequently. On my machine running the test in a loop:
3
while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test; do true; done
1
4
5
will fail in less than a minute with an error like:
6
ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs:
7
assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): (0.00286205989 > 0.01)
8
9
(Failures have been observed on all 4 of the randomness tests,
10
not just first_byte_runs.)
11
12
It's not clear why these tests are failing like this, but intermittent
13
failures make CI and merge testing awkward, so disable running them
14
unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when
15
running the test suite, until we work out the cause.
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
19
Message-id: 20201102152454.8287-1-peter.maydell@linaro.org
20
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
21
---
22
tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++----
23
1 file changed, 10 insertions(+), 4 deletions(-)
24
25
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/qtest/npcm7xx_rng-test.c
28
+++ b/tests/qtest/npcm7xx_rng-test.c
29
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
30
31
qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable);
32
qtest_add_func("npcm7xx_rng/rosel", test_rosel);
33
- qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
34
- qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
35
- qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
36
- qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
37
+ /*
38
+ * These tests fail intermittently; only run them on explicit
39
+ * request until we figure out why.
40
+ */
41
+ if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) {
42
+ qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
43
+ qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
44
+ qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
45
+ qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
46
+ }
47
48
qtest_start("-machine npcm750-evb");
49
ret = g_test_run();
50
--
51
2.20.1
52
53
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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