[Qemu-devel] [PULL v2 00/44] target-arm queue
[PULL v2 00/57] target-arm queue
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v1->v2 changes: drop the "convert FEATURE_THUMB2EE" patch as
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Squashed in a trivial fix for 32-bit hosts:
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it broke compilation on arm hosts (conversion of KVM related
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code had been forgotten)
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2
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thanks
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--- a/target/arm/mve_helper.c
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+++ b/target/arm/mve_helper.c
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@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
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acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
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m[H##ESIZE(e)])); \
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} \
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- acc = int128_add(acc, 1 << 7); \
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+ acc = int128_add(acc, int128_make64(1 << 7)); \
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} \
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} \
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mve_advance_vpt(env); \
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-- PMM
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-- PMM
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The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
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The following changes since commit 53f306f316549d20c76886903181413d20842423:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22' into staging (2018-10-23 17:20:23 +0100)
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181024
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
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24
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for you to fetch changes up to 93f379b0c43617b1361f742f261479eaed4959cb:
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for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
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target/arm: Only flush tlb if ASID changes (2018-10-24 07:51:37 +0100)
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docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* ssi-sd: Make devices picking up backends unavailable with -device
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* Don't require 'virt' board to be compiled in for ACPI GHES code
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* Add support for VCPU event states
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* docs: Document which architecture extensions we emulate
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* Move towards making ID registers the source of truth for
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* Fix bugs in M-profile FPCXT_NS accesses
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whether a guest CPU implements a feature, rather than having
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* First slice of MVE patches
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parallel ID registers and feature bit flags
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* Implement MTE3
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* Implement various HCR hypervisor trap/config bits
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* docs/system: arm: Add nRF boards description
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* Get IL bit correct for v7 syndrome values
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* Report correct syndrome for FP/SIMD traps to Hyp mode
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* hw/arm/boot: Increase compliance with kernel arm64 boot protocol
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* Refactor A32 Neon to use generic vector infrastructure
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* Fix a bug in A32 VLD2 "(multiple 2-element structures)" insn
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* net: cadence_gem: Report features correctly in ID register
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* Avoid some unnecessary TLB flushes on TTBR register writes
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----------------------------------------------------------------
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----------------------------------------------------------------
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Dongjiu Geng (1):
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Alexandre Iooss (1):
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target/arm: Add support for VCPU event states
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docs/system: arm: Add nRF boards description
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Edgar E. Iglesias (2):
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Peter Collingbourne (1):
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net: cadence_gem: Announce availability of priority queues
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target/arm: Implement MTE3
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net: cadence_gem: Announce 64bit addressing support
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Markus Armbruster (1):
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Peter Maydell (55):
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ssi-sd: Make devices picking up backends unavailable with -device
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hw/acpi: Provide stub version of acpi_ghes_record_errors()
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hw/acpi: Provide function acpi_ghes_present()
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target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
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docs/system/arm: Document which architecture extensions we emulate
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target/arm/translate-vfp.c: Whitespace fixes
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target/arm: Handle FPU being disabled in FPCXT_NS accesses
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target/arm: Don't NOCP fault for FPCXT_NS accesses
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target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
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target/arm: Factor FP context update code out into helper function
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target/arm: Split vfp_access_check() into A and M versions
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target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
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target/arm: Implement MVE VLDR/VSTR (non-widening forms)
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target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
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target/arm: Implement MVE VCLZ
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target/arm: Implement MVE VCLS
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target/arm: Implement MVE VREV16, VREV32, VREV64
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target/arm: Implement MVE VMVN (register)
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target/arm: Implement MVE VABS
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target/arm: Implement MVE VNEG
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tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
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target/arm: Implement MVE VDUP
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target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
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target/arm: Implement MVE VADD, VSUB, VMUL
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target/arm: Implement MVE VMULH
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target/arm: Implement MVE VRMULH
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target/arm: Implement MVE VMAX, VMIN
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target/arm: Implement MVE VABD
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target/arm: Implement MVE VHADD, VHSUB
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target/arm: Implement MVE VMULL
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target/arm: Implement MVE VMLALDAV
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target/arm: Implement MVE VMLSLDAV
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target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
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target/arm: Implement MVE VADD (scalar)
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target/arm: Implement MVE VSUB, VMUL (scalar)
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target/arm: Implement MVE VHADD, VHSUB (scalar)
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target/arm: Implement MVE VBRSR
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target/arm: Implement MVE VPST
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target/arm: Implement MVE VQADD and VQSUB
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target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
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target/arm: Implement MVE VQDMULL scalar
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target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
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target/arm: Implement MVE VQADD, VQSUB (vector)
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target/arm: Implement MVE VQSHL (vector)
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target/arm: Implement MVE VQRSHL
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target/arm: Implement MVE VSHL insn
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target/arm: Implement MVE VRSHL
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target/arm: Implement MVE VQDMLADH and VQRDMLADH
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target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
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target/arm: Implement MVE VQDMULL (vector)
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target/arm: Implement MVE VRHADD
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target/arm: Implement MVE VADC, VSBC
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target/arm: Implement MVE VCADD
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target/arm: Implement MVE VHCADD
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target/arm: Implement MVE VADDV
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target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
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Peter Maydell (10):
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docs/system/arm/emulation.rst | 103 ++++
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target/arm: Improve debug logging of AArch32 exception return
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docs/system/arm/nrf.rst | 51 ++
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target/arm: Make switch_mode() file-local
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docs/system/target-arm.rst | 7 +
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target/arm: Implement HCR.FB
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include/hw/acpi/ghes.h | 9 +
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target/arm: Implement HCR.DC
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include/tcg/tcg-op.h | 8 +
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target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set
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include/tcg/tcg.h | 1 -
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target/arm: Implement HCR.VI and VF
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target/arm/helper-mve.h | 357 +++++++++++++
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target/arm: Implement HCR.PTW
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target/arm/helper.h | 2 +
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target/arm: New utility function to extract EC from syndrome
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target/arm/internals.h | 11 +
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target/arm: Get IL bit correct for v7 syndrome values
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target/arm/translate-a32.h | 3 +
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target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode
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target/arm/translate.h | 10 +
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target/arm/m-nocp.decode | 24 +
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target/arm/mve.decode | 240 +++++++++
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target/arm/vfp.decode | 14 -
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hw/acpi/ghes-stub.c | 22 +
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hw/acpi/ghes.c | 17 +
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target/arm/cpu64.c | 2 +-
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target/arm/kvm64.c | 6 +-
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target/arm/mte_helper.c | 82 +--
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target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
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target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
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target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
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target/arm/translate-vfp.c | 741 +++++++-------------------
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tcg/tcg-op-gvec.c | 20 +-
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MAINTAINERS | 1 +
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hw/acpi/meson.build | 6 +-
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target/arm/meson.build | 1 +
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27 files changed, 3578 insertions(+), 629 deletions(-)
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create mode 100644 docs/system/arm/emulation.rst
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create mode 100644 docs/system/arm/nrf.rst
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create mode 100644 target/arm/helper-mve.h
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create mode 100644 hw/acpi/ghes-stub.c
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create mode 100644 target/arm/mve_helper.c
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Richard Henderson (29):
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target/arm: Move some system registers into a substructure
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target/arm: V8M should not imply V7VE
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target/arm: Convert v8 extensions from feature bits to isar tests
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target/arm: Convert division from feature bits to isar0 tests
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target/arm: Convert jazelle from feature bit to isar1 test
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target/arm: Convert sve from feature bit to aa64pfr0 test
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target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test
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target/arm: Hoist address increment for vector memory ops
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target/arm: Don't call tcg_clear_temp_count
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target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R
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target/arm: Promote consecutive memory ops for aa64
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target/arm: Mark some arrays const
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target/arm: Use gvec for NEON VDUP
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target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)
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target/arm: Use gvec for NEON_3R_LOGIC insns
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target/arm: Use gvec for NEON_3R_VADD_VSUB insns
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target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG
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target/arm: Use gvec for NEON_3R_VMUL
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target/arm: Use gvec for VSHR, VSHL
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target/arm: Use gvec for VSRA
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target/arm: Use gvec for VSRI, VSLI
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target/arm: Use gvec for NEON_3R_VML
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target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE
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target/arm: Use gvec for NEON VLD all lanes
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target/arm: Reorg NEON VLD/VST all elements
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target/arm: Promote consecutive memory ops for aa32
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target/arm: Reorg NEON VLD/VST single element to one lane
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target/arm: Remove writefn from TTBR0_EL3
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target/arm: Only flush tlb if ASID changes
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Stewart Hildebrand (1):
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hw/arm/boot: Increase compliance with kernel arm64 boot protocol
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target/arm/cpu.h | 221 ++++++-
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target/arm/internals.h | 45 +-
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target/arm/kvm_arm.h | 24 +
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target/arm/translate.h | 21 +
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hw/arm/boot.c | 18 +
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hw/intc/armv7m_nvic.c | 12 +-
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hw/net/cadence_gem.c | 9 +-
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hw/sd/ssi-sd.c | 2 +
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linux-user/aarch64/signal.c | 4 +-
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linux-user/elfload.c | 58 +-
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linux-user/syscall.c | 10 +-
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target/arm/cpu.c | 238 +++----
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target/arm/cpu64.c | 148 +++--
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target/arm/helper.c | 395 ++++++++----
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target/arm/kvm.c | 60 ++
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target/arm/kvm32.c | 13 +
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target/arm/kvm64.c | 15 +-
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target/arm/machine.c | 25 +-
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target/arm/op_helper.c | 2 +-
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target/arm/translate-a64.c | 715 ++++-----------------
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target/arm/translate.c | 1451 ++++++++++++++++++++++++++++---------------
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21 files changed, 2013 insertions(+), 1473 deletions(-)
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