| 1 | v1->v2 changes: drop the "convert FEATURE_THUMB2EE" patch as | 1 | v2: drop pvpanic-pci patches. |
|---|---|---|---|
| 2 | it broke compilation on arm hosts (conversion of KVM related | ||
| 3 | code had been forgotten) | ||
| 4 | 2 | ||
| 5 | thanks | 3 | The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c: |
| 6 | -- PMM | ||
| 7 | 4 | ||
| 8 | The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3: | 5 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000) |
| 9 | |||
| 10 | Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22' into staging (2018-10-23 17:20:23 +0100) | ||
| 11 | 6 | ||
| 12 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 13 | 8 | ||
| 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181024 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1 |
| 15 | 10 | ||
| 16 | for you to fetch changes up to 93f379b0c43617b1361f742f261479eaed4959cb: | 11 | for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8: |
| 17 | 12 | ||
| 18 | target/arm: Only flush tlb if ASID changes (2018-10-24 07:51:37 +0100) | 13 | docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000) |
| 19 | 14 | ||
| 20 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 21 | target-arm queue: | 16 | target-arm queue: |
| 22 | * ssi-sd: Make devices picking up backends unavailable with -device | 17 | * Implement IMPDEF pauth algorithm |
| 23 | * Add support for VCPU event states | 18 | * Support ARMv8.4-SEL2 |
| 24 | * Move towards making ID registers the source of truth for | 19 | * Fix bug where we were truncating predicate vector lengths in SVE insns |
| 25 | whether a guest CPU implements a feature, rather than having | 20 | * npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 26 | parallel ID registers and feature bit flags | 21 | * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 27 | * Implement various HCR hypervisor trap/config bits | 22 | * docs: Build and install all the docs in a single manual |
| 28 | * Get IL bit correct for v7 syndrome values | ||
| 29 | * Report correct syndrome for FP/SIMD traps to Hyp mode | ||
| 30 | * hw/arm/boot: Increase compliance with kernel arm64 boot protocol | ||
| 31 | * Refactor A32 Neon to use generic vector infrastructure | ||
| 32 | * Fix a bug in A32 VLD2 "(multiple 2-element structures)" insn | ||
| 33 | * net: cadence_gem: Report features correctly in ID register | ||
| 34 | * Avoid some unnecessary TLB flushes on TTBR register writes | ||
| 35 | 23 | ||
| 36 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 37 | Dongjiu Geng (1): | 25 | Gan Qixin (1): |
| 38 | target/arm: Add support for VCPU event states | 26 | npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 39 | 27 | ||
| 40 | Edgar E. Iglesias (2): | 28 | Peter Maydell (1): |
| 41 | net: cadence_gem: Announce availability of priority queues | 29 | docs: Build and install all the docs in a single manual |
| 42 | net: cadence_gem: Announce 64bit addressing support | ||
| 43 | 30 | ||
| 44 | Markus Armbruster (1): | 31 | Philippe Mathieu-Daudé (1): |
| 45 | ssi-sd: Make devices picking up backends unavailable with -device | 32 | target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 46 | 33 | ||
| 47 | Peter Maydell (10): | 34 | Richard Henderson (7): |
| 48 | target/arm: Improve debug logging of AArch32 exception return | 35 | target/arm: Implement an IMPDEF pauth algorithm |
| 49 | target/arm: Make switch_mode() file-local | 36 | target/arm: Add cpu properties to control pauth |
| 50 | target/arm: Implement HCR.FB | 37 | target/arm: Use object_property_add_bool for "sve" property |
| 51 | target/arm: Implement HCR.DC | 38 | target/arm: Introduce PREDDESC field definitions |
| 52 | target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set | 39 | target/arm: Update PFIRST, PNEXT for pred_desc |
| 53 | target/arm: Implement HCR.VI and VF | 40 | target/arm: Update ZIP, UZP, TRN for pred_desc |
| 54 | target/arm: Implement HCR.PTW | 41 | target/arm: Update REV, PUNPK for pred_desc |
| 55 | target/arm: New utility function to extract EC from syndrome | ||
| 56 | target/arm: Get IL bit correct for v7 syndrome values | ||
| 57 | target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode | ||
| 58 | 42 | ||
| 59 | Richard Henderson (29): | 43 | Rémi Denis-Courmont (19): |
| 60 | target/arm: Move some system registers into a substructure | 44 | target/arm: remove redundant tests |
| 61 | target/arm: V8M should not imply V7VE | 45 | target/arm: add arm_is_el2_enabled() helper |
| 62 | target/arm: Convert v8 extensions from feature bits to isar tests | 46 | target/arm: use arm_is_el2_enabled() where applicable |
| 63 | target/arm: Convert division from feature bits to isar0 tests | 47 | target/arm: use arm_hcr_el2_eff() where applicable |
| 64 | target/arm: Convert jazelle from feature bit to isar1 test | 48 | target/arm: factor MDCR_EL2 common handling |
| 65 | target/arm: Convert sve from feature bit to aa64pfr0 test | 49 | target/arm: Define isar_feature function to test for presence of SEL2 |
| 66 | target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test | 50 | target/arm: add 64-bit S-EL2 to EL exception table |
| 67 | target/arm: Hoist address increment for vector memory ops | 51 | target/arm: add MMU stage 1 for Secure EL2 |
| 68 | target/arm: Don't call tcg_clear_temp_count | 52 | target/arm: add ARMv8.4-SEL2 system registers |
| 69 | target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R | 53 | target/arm: handle VMID change in secure state |
| 70 | target/arm: Promote consecutive memory ops for aa64 | 54 | target/arm: do S1_ptw_translate() before address space lookup |
| 71 | target/arm: Mark some arrays const | 55 | target/arm: translate NS bit in page-walks |
| 72 | target/arm: Use gvec for NEON VDUP | 56 | target/arm: generalize 2-stage page-walk condition |
| 73 | target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate) | 57 | target/arm: secure stage 2 translation regime |
| 74 | target/arm: Use gvec for NEON_3R_LOGIC insns | 58 | target/arm: set HPFAR_EL2.NS on secure stage 2 faults |
| 75 | target/arm: Use gvec for NEON_3R_VADD_VSUB insns | 59 | target/arm: revector to run-time pick target EL |
| 76 | target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG | 60 | target/arm: Implement SCR_EL2.EEL2 |
| 77 | target/arm: Use gvec for NEON_3R_VMUL | 61 | target/arm: enable Secure EL2 in max CPU |
| 78 | target/arm: Use gvec for VSHR, VSHL | 62 | target/arm: refactor vae1_tlbmask() |
| 79 | target/arm: Use gvec for VSRA | ||
| 80 | target/arm: Use gvec for VSRI, VSLI | ||
| 81 | target/arm: Use gvec for NEON_3R_VML | ||
| 82 | target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE | ||
| 83 | target/arm: Use gvec for NEON VLD all lanes | ||
| 84 | target/arm: Reorg NEON VLD/VST all elements | ||
| 85 | target/arm: Promote consecutive memory ops for aa32 | ||
| 86 | target/arm: Reorg NEON VLD/VST single element to one lane | ||
| 87 | target/arm: Remove writefn from TTBR0_EL3 | ||
| 88 | target/arm: Only flush tlb if ASID changes | ||
| 89 | 63 | ||
| 90 | Stewart Hildebrand (1): | 64 | docs/conf.py | 46 ++++- |
| 91 | hw/arm/boot: Increase compliance with kernel arm64 boot protocol | 65 | docs/devel/conf.py | 15 -- |
| 66 | docs/index.html.in | 17 -- | ||
| 67 | docs/interop/conf.py | 28 --- | ||
| 68 | docs/meson.build | 64 +++--- | ||
| 69 | docs/specs/conf.py | 16 -- | ||
| 70 | docs/system/arm/cpu-features.rst | 21 ++ | ||
| 71 | docs/system/conf.py | 28 --- | ||
| 72 | docs/tools/conf.py | 37 ---- | ||
| 73 | docs/user/conf.py | 15 -- | ||
| 74 | include/qemu/xxhash.h | 98 +++++++++ | ||
| 75 | target/arm/cpu-param.h | 2 +- | ||
| 76 | target/arm/cpu.h | 107 ++++++++-- | ||
| 77 | target/arm/internals.h | 45 +++++ | ||
| 78 | target/arm/cpu.c | 23 ++- | ||
| 79 | target/arm/cpu64.c | 65 ++++-- | ||
| 80 | target/arm/helper-a64.c | 8 +- | ||
| 81 | target/arm/helper.c | 414 ++++++++++++++++++++++++++------------- | ||
| 82 | target/arm/m_helper.c | 2 +- | ||
| 83 | target/arm/monitor.c | 1 + | ||
| 84 | target/arm/op_helper.c | 4 +- | ||
| 85 | target/arm/pauth_helper.c | 27 ++- | ||
| 86 | target/arm/sve_helper.c | 33 ++-- | ||
| 87 | target/arm/tlb_helper.c | 3 + | ||
| 88 | target/arm/translate-a64.c | 4 + | ||
| 89 | target/arm/translate-sve.c | 31 ++- | ||
| 90 | target/arm/translate.c | 36 +++- | ||
| 91 | tests/qtest/arm-cpu-features.c | 13 ++ | ||
| 92 | tests/qtest/npcm7xx_adc-test.c | 1 + | ||
| 93 | .gitlab-ci.yml | 4 +- | ||
| 94 | 30 files changed, 770 insertions(+), 438 deletions(-) | ||
| 95 | delete mode 100644 docs/devel/conf.py | ||
| 96 | delete mode 100644 docs/index.html.in | ||
| 97 | delete mode 100644 docs/interop/conf.py | ||
| 98 | delete mode 100644 docs/specs/conf.py | ||
| 99 | delete mode 100644 docs/system/conf.py | ||
| 100 | delete mode 100644 docs/tools/conf.py | ||
| 101 | delete mode 100644 docs/user/conf.py | ||
| 92 | 102 | ||
| 93 | target/arm/cpu.h | 221 ++++++- | ||
| 94 | target/arm/internals.h | 45 +- | ||
| 95 | target/arm/kvm_arm.h | 24 + | ||
| 96 | target/arm/translate.h | 21 + | ||
| 97 | hw/arm/boot.c | 18 + | ||
| 98 | hw/intc/armv7m_nvic.c | 12 +- | ||
| 99 | hw/net/cadence_gem.c | 9 +- | ||
| 100 | hw/sd/ssi-sd.c | 2 + | ||
| 101 | linux-user/aarch64/signal.c | 4 +- | ||
| 102 | linux-user/elfload.c | 58 +- | ||
| 103 | linux-user/syscall.c | 10 +- | ||
| 104 | target/arm/cpu.c | 238 +++---- | ||
| 105 | target/arm/cpu64.c | 148 +++-- | ||
| 106 | target/arm/helper.c | 395 ++++++++---- | ||
| 107 | target/arm/kvm.c | 60 ++ | ||
| 108 | target/arm/kvm32.c | 13 + | ||
| 109 | target/arm/kvm64.c | 15 +- | ||
| 110 | target/arm/machine.c | 25 +- | ||
| 111 | target/arm/op_helper.c | 2 +- | ||
| 112 | target/arm/translate-a64.c | 715 ++++----------------- | ||
| 113 | target/arm/translate.c | 1451 ++++++++++++++++++++++++++++--------------- | ||
| 114 | 21 files changed, 2013 insertions(+), 1473 deletions(-) | ||
| 115 | diff view generated by jsdifflib |