[Qemu-devel] [PULL 00/45] target-arm queue
[PULL 00/21] target-arm queue
1
As promised, another pullreq... This one's mostly RTH's patches.
1
Hi; here's the latest batch of arm changes. The big thing
2
in here is the SMMUv3 changes to add stage-2 translation support.
2
3
3
thanks
4
thanks
4
-- PMM
5
-- PMM
5
6
6
The following changes since commit 784c2e4f232adf5ef47a84a262ec72a07d068d6a:
7
The following changes since commit aa9bbd865502ed517624ab6fe7d4b5d89ca95e43:
7
8
8
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2018-10-19 15:30:40 +0100)
9
Merge tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu into staging (2023-05-29 14:31:52 -0700)
9
10
10
are available in the Git repository at:
11
are available in the Git repository at:
11
12
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181019
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230530
13
14
14
for you to fetch changes up to 88c9add25e7120e8622796c81ad3f3fb7f8d40e7:
15
for you to fetch changes up to b03d0d4f531a8b867e0aac1fab0b876903015680:
15
16
16
target/arm: Only flush tlb if ASID changes (2018-10-19 17:38:48 +0100)
17
docs: sbsa: correct graphics card name (2023-05-30 13:32:46 +0100)
17
18
18
----------------------------------------------------------------
19
----------------------------------------------------------------
19
target-arm queue:
20
target-arm queue:
20
* ssi-sd: Make devices picking up backends unavailable with -device
21
* fsl-imx6: Add SNVS support for i.MX6 boards
21
* Add support for VCPU event states
22
* smmuv3: Add support for stage 2 translations
22
* Move towards making ID registers the source of truth for
23
* hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop
23
whether a guest CPU implements a feature, rather than having
24
* hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
24
parallel ID registers and feature bit flags
25
* cleanups for recent Kconfig changes
25
* Implement various HCR hypervisor trap/config bits
26
* target/arm: Explicitly select short-format FSR for M-profile
26
* Get IL bit correct for v7 syndrome values
27
* tests/qtest: Run arm-specific tests only if the required machine is available
27
* Report correct syndrome for FP/SIMD traps to Hyp mode
28
* hw/arm/sbsa-ref: add GIC node into DT
28
* hw/arm/boot: Increase compliance with kernel arm64 boot protocol
29
* docs: sbsa: correct graphics card name
29
* Refactor A32 Neon to use generic vector infrastructure
30
* Update copyright dates to 2023
30
* Fix a bug in A32 VLD2 "(multiple 2-element structures)" insn
31
* net: cadence_gem: Report features correctly in ID register
32
* Avoid some unnecessary TLB flushes on TTBR register writes
33
31
34
----------------------------------------------------------------
32
----------------------------------------------------------------
35
Dongjiu Geng (1):
33
Clément Chigot (1):
36
target/arm: Add support for VCPU event states
34
hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
37
35
38
Edgar E. Iglesias (2):
36
Enze Li (1):
39
net: cadence_gem: Announce availability of priority queues
37
Update copyright dates to 2023
40
net: cadence_gem: Announce 64bit addressing support
41
38
42
Markus Armbruster (1):
39
Fabiano Rosas (3):
43
ssi-sd: Make devices picking up backends unavailable with -device
40
target/arm: Explain why we need to select ARM_V7M
41
arm/Kconfig: Keep Kconfig default entries in default.mak as documentation
42
arm/Kconfig: Make TCG dependence explicit
44
43
45
Peter Maydell (10):
44
Marcin Juszkiewicz (2):
46
target/arm: Improve debug logging of AArch32 exception return
45
hw/arm/sbsa-ref: add GIC node into DT
47
target/arm: Make switch_mode() file-local
46
docs: sbsa: correct graphics card name
48
target/arm: Implement HCR.FB
49
target/arm: Implement HCR.DC
50
target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set
51
target/arm: Implement HCR.VI and VF
52
target/arm: Implement HCR.PTW
53
target/arm: New utility function to extract EC from syndrome
54
target/arm: Get IL bit correct for v7 syndrome values
55
target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode
56
47
57
Richard Henderson (30):
48
Mostafa Saleh (10):
58
target/arm: Move some system registers into a substructure
49
hw/arm/smmuv3: Add missing fields for IDR0
59
target/arm: V8M should not imply V7VE
50
hw/arm/smmuv3: Update translation config to hold stage-2
60
target/arm: Convert v8 extensions from feature bits to isar tests
51
hw/arm/smmuv3: Refactor stage-1 PTW
61
target/arm: Convert division from feature bits to isar0 tests
52
hw/arm/smmuv3: Add page table walk for stage-2
62
target/arm: Convert jazelle from feature bit to isar1 test
53
hw/arm/smmuv3: Parse STE config for stage-2
63
target/arm: Convert t32ee from feature bit to isar3 test
54
hw/arm/smmuv3: Make TLB lookup work for stage-2
64
target/arm: Convert sve from feature bit to aa64pfr0 test
55
hw/arm/smmuv3: Add VMID to TLB tagging
65
target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test
56
hw/arm/smmuv3: Add CMDs related to stage-2
66
target/arm: Hoist address increment for vector memory ops
57
hw/arm/smmuv3: Add stage-2 support in iova notifier
67
target/arm: Don't call tcg_clear_temp_count
58
hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2
68
target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R
69
target/arm: Promote consecutive memory ops for aa64
70
target/arm: Mark some arrays const
71
target/arm: Use gvec for NEON VDUP
72
target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)
73
target/arm: Use gvec for NEON_3R_LOGIC insns
74
target/arm: Use gvec for NEON_3R_VADD_VSUB insns
75
target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG
76
target/arm: Use gvec for NEON_3R_VMUL
77
target/arm: Use gvec for VSHR, VSHL
78
target/arm: Use gvec for VSRA
79
target/arm: Use gvec for VSRI, VSLI
80
target/arm: Use gvec for NEON_3R_VML
81
target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE
82
target/arm: Use gvec for NEON VLD all lanes
83
target/arm: Reorg NEON VLD/VST all elements
84
target/arm: Promote consecutive memory ops for aa32
85
target/arm: Reorg NEON VLD/VST single element to one lane
86
target/arm: Remove writefn from TTBR0_EL3
87
target/arm: Only flush tlb if ASID changes
88
59
89
Stewart Hildebrand (1):
60
Peter Maydell (1):
90
hw/arm/boot: Increase compliance with kernel arm64 boot protocol
61
target/arm: Explicitly select short-format FSR for M-profile
91
62
92
target/arm/cpu.h | 227 ++++++-
63
Thomas Huth (1):
93
target/arm/internals.h | 45 +-
64
tests/qtest: Run arm-specific tests only if the required machine is available
94
target/arm/kvm_arm.h | 24 +
95
target/arm/translate.h | 21 +
96
hw/arm/boot.c | 18 +
97
hw/intc/armv7m_nvic.c | 12 +-
98
hw/net/cadence_gem.c | 9 +-
99
hw/sd/ssi-sd.c | 2 +
100
linux-user/aarch64/signal.c | 4 +-
101
linux-user/elfload.c | 60 +-
102
linux-user/syscall.c | 10 +-
103
target/arm/cpu.c | 242 ++++----
104
target/arm/cpu64.c | 148 +++--
105
target/arm/helper.c | 397 ++++++++----
106
target/arm/kvm.c | 60 ++
107
target/arm/kvm32.c | 13 +
108
target/arm/kvm64.c | 15 +-
109
target/arm/machine.c | 28 +-
110
target/arm/op_helper.c | 2 +-
111
target/arm/translate-a64.c | 715 ++++-----------------
112
target/arm/translate.c | 1451 ++++++++++++++++++++++++++++---------------
113
21 files changed, 2021 insertions(+), 1482 deletions(-)
114
65
66
Tommy Wu (1):
67
hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.
68
69
Vitaly Cheptsov (1):
70
fsl-imx6: Add SNVS support for i.MX6 boards
71
72
docs/conf.py | 2 +-
73
docs/system/arm/sbsa.rst | 2 +-
74
configs/devices/aarch64-softmmu/default.mak | 6 +
75
configs/devices/arm-softmmu/default.mak | 40 ++++
76
hw/arm/smmu-internal.h | 37 +++
77
hw/arm/smmuv3-internal.h | 12 +-
78
include/hw/arm/fsl-imx6.h | 2 +
79
include/hw/arm/smmu-common.h | 45 +++-
80
include/hw/arm/smmuv3.h | 4 +
81
include/qemu/help-texts.h | 2 +-
82
hw/arm/fsl-imx6.c | 8 +
83
hw/arm/sbsa-ref.c | 19 +-
84
hw/arm/smmu-common.c | 209 ++++++++++++++--
85
hw/arm/smmuv3.c | 357 ++++++++++++++++++++++++----
86
hw/arm/xlnx-zynqmp.c | 2 +-
87
hw/dma/xilinx_axidma.c | 11 +-
88
target/arm/tcg/tlb_helper.c | 13 +-
89
hw/arm/Kconfig | 123 ++++++----
90
hw/arm/trace-events | 14 +-
91
target/arm/Kconfig | 3 +
92
tests/qtest/meson.build | 7 +-
93
21 files changed, 773 insertions(+), 145 deletions(-)
94
diff view generated by jsdifflib
[Qemu-devel] [PULL 43/45] net: cadence_gem: Announce 64bit addressing support
[PULL 01/21] fsl-imx6: Add SNVS support for i.MX6 boards
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Vitaly Cheptsov <cheptsov@ispras.ru>
2
2
3
Announce 64bit addressing support.
3
SNVS is supported on both i.MX6 and i.MX6UL and is needed
4
to support shutdown on the board.
4
5
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Cc: Peter Maydell <peter.maydell@linaro.org> (odd fixer:SABRELITE / i.MX6)
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Cc: Jean-Christophe Dubois <jcd@tribudubois.net> (reviewer:SABRELITE / i.MX6)
7
Message-id: 20181017213932.19973-3-edgar.iglesias@gmail.com
8
Cc: qemu-arm@nongnu.org (open list:SABRELITE / i.MX6)
9
Cc: qemu-devel@nongnu.org (open list:All patches CC here)
10
Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru>
11
Message-id: 20230515095015.66860-1-cheptsov@ispras.ru
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
14
---
11
hw/net/cadence_gem.c | 3 ++-
15
include/hw/arm/fsl-imx6.h | 2 ++
12
1 file changed, 2 insertions(+), 1 deletion(-)
16
hw/arm/fsl-imx6.c | 8 ++++++++
17
2 files changed, 10 insertions(+)
13
18
14
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
19
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/cadence_gem.c
21
--- a/include/hw/arm/fsl-imx6.h
17
+++ b/hw/net/cadence_gem.c
22
+++ b/include/hw/arm/fsl-imx6.h
18
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
19
#define GEM_DESCONF4 (0x0000028C/4)
24
#include "hw/cpu/a9mpcore.h"
20
#define GEM_DESCONF5 (0x00000290/4)
25
#include "hw/misc/imx6_ccm.h"
21
#define GEM_DESCONF6 (0x00000294/4)
26
#include "hw/misc/imx6_src.h"
22
+#define GEM_DESCONF6_64B_MASK (1U << 23)
27
+#include "hw/misc/imx7_snvs.h"
23
#define GEM_DESCONF7 (0x00000298/4)
28
#include "hw/watchdog/wdt_imx2.h"
24
29
#include "hw/char/imx_serial.h"
25
#define GEM_INT_Q1_STATUS (0x00000400 / 4)
30
#include "hw/timer/imx_gpt.h"
26
@@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d)
31
@@ -XXX,XX +XXX,XX @@ struct FslIMX6State {
27
s->regs[GEM_DESCONF] = 0x02500111;
32
A9MPPrivState a9mpcore;
28
s->regs[GEM_DESCONF2] = 0x2ab13fff;
33
IMX6CCMState ccm;
29
s->regs[GEM_DESCONF5] = 0x002f2045;
34
IMX6SRCState src;
30
- s->regs[GEM_DESCONF6] = 0x0;
35
+ IMX7SNVSState snvs;
31
+ s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
36
IMXSerialState uart[FSL_IMX6_NUM_UARTS];
32
37
IMXGPTState gpt;
33
if (s->num_priority_queues > 1) {
38
IMXEPITState epit[FSL_IMX6_NUM_EPITS];
34
queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
39
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/fsl-imx6.c
42
+++ b/hw/arm/fsl-imx6.c
43
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
44
45
object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC);
46
47
+ object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
48
+
49
for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
50
snprintf(name, NAME_SIZE, "uart%d", i + 1);
51
object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL);
52
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
53
qdev_get_gpio_in(DEVICE(&s->a9mpcore),
54
FSL_IMX6_ENET_MAC_1588_IRQ));
55
56
+ /*
57
+ * SNVS
58
+ */
59
+ sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
60
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6_SNVSHP_ADDR);
61
+
62
/*
63
* Watchdog
64
*/
35
--
65
--
36
2.19.1
66
2.34.1
37
38
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/45] ssi-sd: Make devices picking up backends unavailable with -device
[PULL 02/21] hw/arm/smmuv3: Add missing fields for IDR0
1
From: Markus Armbruster <armbru@redhat.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
Device models aren't supposed to go on fishing expeditions for
3
In preparation for adding stage-2 support.
4
backends. They should expose suitable properties for the user to set.
4
Add IDR0 fields related to stage-2.
5
For onboard devices, board code sets them.
6
5
7
Device ssi-sd picks up its block backend in its init() method with
6
VMID16: 16-bit VMID supported.
8
drive_get_next() instead. This mistake is already marked FIXME since
7
S2P: Stage-2 translation supported.
9
commit af9e40a.
10
8
11
Unset user_creatable to remove the mistake from our external
9
They are described in 6.3.1 SMMU_IDR0.
12
interface. Since the SSI bus doesn't support hotplug, only -device
13
can be affected. Only certain ARM machines have ssi-sd and provide an
14
SSI bus for it; this patch breaks -device ssi-sd for these machines.
15
No actual use of -device ssi-sd is known.
16
10
17
Signed-off-by: Markus Armbruster <armbru@redhat.com>
11
No functional change intended.
18
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
19
Acked-by: Thomas Huth <thuth@redhat.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20181009060835.4608-1-armbru@redhat.com
14
Reviewed-by: Eric Auger <eric.auger@redhat.com>
15
Signed-off-by: Mostafa Saleh <smostafa@google.com>
16
Tested-by: Eric Auger <eric.auger@redhat.com>
17
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
18
Message-id: 20230516203327.2051088-2-smostafa@google.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
20
---
23
hw/sd/ssi-sd.c | 2 ++
21
hw/arm/smmuv3-internal.h | 2 ++
24
1 file changed, 2 insertions(+)
22
1 file changed, 2 insertions(+)
25
23
26
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
24
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
27
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/sd/ssi-sd.c
26
--- a/hw/arm/smmuv3-internal.h
29
+++ b/hw/sd/ssi-sd.c
27
+++ b/hw/arm/smmuv3-internal.h
30
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_class_init(ObjectClass *klass, void *data)
28
@@ -XXX,XX +XXX,XX @@ typedef enum SMMUTranslationStatus {
31
k->cs_polarity = SSI_CS_LOW;
29
/* MMIO Registers */
32
dc->vmsd = &vmstate_ssi_sd;
30
33
dc->reset = ssi_sd_reset;
31
REG32(IDR0, 0x0)
34
+ /* Reason: init() method uses drive_get_next() */
32
+ FIELD(IDR0, S2P, 0 , 1)
35
+ dc->user_creatable = false;
33
FIELD(IDR0, S1P, 1 , 1)
36
}
34
FIELD(IDR0, TTF, 2 , 2)
37
35
FIELD(IDR0, COHACC, 4 , 1)
38
static const TypeInfo ssi_sd_info = {
36
FIELD(IDR0, ASID16, 12, 1)
37
+ FIELD(IDR0, VMID16, 18, 1)
38
FIELD(IDR0, TTENDIAN, 21, 2)
39
FIELD(IDR0, STALL_MODEL, 24, 2)
40
FIELD(IDR0, TERM_MODEL, 26, 1)
39
--
41
--
40
2.19.1
42
2.34.1
41
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/45] target/arm: Use gvec for NEON_3R_LOGIC insns
[PULL 03/21] hw/arm/smmuv3: Update translation config to hold stage-2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
Move expanders for VBSL, VBIT, and VBIF from translate-a64.c.
3
In preparation for adding stage-2 support, add a S2 config
4
struct(SMMUS2Cfg), composed of the following fields and embedded in
5
the main SMMUTransCfg:
6
-tsz: Size of IPA input region (S2T0SZ)
7
-sl0: Start level of translation (S2SL0)
8
-affd: AF Fault Disable (S2AFFD)
9
-record_faults: Record fault events (S2R)
10
-granule_sz: Granule page shift (based on S2TG)
11
-vmid: Virtual Machine ID (S2VMID)
12
-vttb: Address of translation table base (S2TTB)
13
-eff_ps: Effective PA output range (based on S2PS)
4
14
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
They will be used in the next patches in stage-2 address translation.
6
Message-id: 20181011205206.3552-9-richard.henderson@linaro.org
16
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
The fields in SMMUS2Cfg, are reordered to make the shared and stage-1
18
fields next to each other, this reordering didn't change the struct
19
size (104 bytes before and after).
20
21
Stage-1 only fields: aa64, asid, tt, ttb, tbi, record_faults, oas.
22
oas is stage-1 output address size. However, it is used to check
23
input address in case stage-1 is unimplemented or bypassed according
24
to SMMUv3 manual IHI0070.E "3.4. Address sizes"
25
26
Shared fields: stage, disabled, bypassed, aborted, iotlb_*.
27
28
No functional change intended.
29
30
Reviewed-by: Eric Auger <eric.auger@redhat.com>
31
Signed-off-by: Mostafa Saleh <smostafa@google.com>
32
Tested-by: Eric Auger <eric.auger@redhat.com>
33
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
34
Message-id: 20230516203327.2051088-3-smostafa@google.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
36
---
10
target/arm/translate.h | 6 ++
37
include/hw/arm/smmu-common.h | 22 +++++++++++++++++++---
11
target/arm/translate-a64.c | 61 --------------
38
1 file changed, 19 insertions(+), 3 deletions(-)
12
target/arm/translate.c | 162 +++++++++++++++++++++++++++----------
13
3 files changed, 124 insertions(+), 105 deletions(-)
14
39
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
40
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
16
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
42
--- a/include/hw/arm/smmu-common.h
18
+++ b/target/arm/translate.h
43
+++ b/include/hw/arm/smmu-common.h
19
@@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 get_ahp_flag(void)
44
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTLBEntry {
20
return ret;
45
uint8_t granule;
21
}
46
} SMMUTLBEntry;
22
47
23
+
48
+/* Stage-2 configuration. */
24
+/* Vector operations shared between ARM and AArch64. */
49
+typedef struct SMMUS2Cfg {
25
+extern const GVecGen3 bsl_op;
50
+ uint8_t tsz; /* Size of IPA input region (S2T0SZ) */
26
+extern const GVecGen3 bit_op;
51
+ uint8_t sl0; /* Start level of translation (S2SL0) */
27
+extern const GVecGen3 bif_op;
52
+ bool affd; /* AF Fault Disable (S2AFFD) */
53
+ bool record_faults; /* Record fault events (S2R) */
54
+ uint8_t granule_sz; /* Granule page shift (based on S2TG) */
55
+ uint8_t eff_ps; /* Effective PA output range (based on S2PS) */
56
+ uint16_t vmid; /* Virtual Machine ID (S2VMID) */
57
+ uint64_t vttb; /* Address of translation table base (S2TTB) */
58
+} SMMUS2Cfg;
28
+
59
+
29
/*
60
/*
30
* Forward to the isar_feature_* tests given a DisasContext pointer.
61
* Generic structure populated by derived SMMU devices
62
* after decoding the configuration information and used as
63
* input to the page table walk
31
*/
64
*/
32
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
65
typedef struct SMMUTransCfg {
33
index XXXXXXX..XXXXXXX 100644
66
+ /* Shared fields between stage-1 and stage-2. */
34
--- a/target/arm/translate-a64.c
67
int stage; /* translation stage */
35
+++ b/target/arm/translate-a64.c
68
- bool aa64; /* arch64 or aarch32 translation table */
36
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
69
bool disabled; /* smmu is disabled */
37
}
70
bool bypassed; /* translation is bypassed */
38
}
71
bool aborted; /* translation is aborted */
39
72
+ uint32_t iotlb_hits; /* counts IOTLB hits */
40
-static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
73
+ uint32_t iotlb_misses; /* counts IOTLB misses*/
41
-{
74
+ /* Used by stage-1 only. */
42
- tcg_gen_xor_i64(rn, rn, rm);
75
+ bool aa64; /* arch64 or aarch32 translation table */
43
- tcg_gen_and_i64(rn, rn, rd);
76
bool record_faults; /* record fault events */
44
- tcg_gen_xor_i64(rd, rm, rn);
77
uint64_t ttb; /* TT base address */
45
-}
78
uint8_t oas; /* output address width */
46
-
79
uint8_t tbi; /* Top Byte Ignore */
47
-static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
80
uint16_t asid;
48
-{
81
SMMUTransTableInfo tt[2];
49
- tcg_gen_xor_i64(rn, rn, rd);
82
- uint32_t iotlb_hits; /* counts IOTLB hits for this asid */
50
- tcg_gen_and_i64(rn, rn, rm);
83
- uint32_t iotlb_misses; /* counts IOTLB misses for this asid */
51
- tcg_gen_xor_i64(rd, rd, rn);
84
+ /* Used by stage-2 only. */
52
-}
85
+ struct SMMUS2Cfg s2cfg;
53
-
86
} SMMUTransCfg;
54
-static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
87
55
-{
88
typedef struct SMMUDevice {
56
- tcg_gen_xor_i64(rn, rn, rd);
57
- tcg_gen_andc_i64(rn, rn, rm);
58
- tcg_gen_xor_i64(rd, rd, rn);
59
-}
60
-
61
-static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
62
-{
63
- tcg_gen_xor_vec(vece, rn, rn, rm);
64
- tcg_gen_and_vec(vece, rn, rn, rd);
65
- tcg_gen_xor_vec(vece, rd, rm, rn);
66
-}
67
-
68
-static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
69
-{
70
- tcg_gen_xor_vec(vece, rn, rn, rd);
71
- tcg_gen_and_vec(vece, rn, rn, rm);
72
- tcg_gen_xor_vec(vece, rd, rd, rn);
73
-}
74
-
75
-static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
76
-{
77
- tcg_gen_xor_vec(vece, rn, rn, rd);
78
- tcg_gen_andc_vec(vece, rn, rn, rm);
79
- tcg_gen_xor_vec(vece, rd, rd, rn);
80
-}
81
-
82
/* Logic op (opcode == 3) subgroup of C3.6.16. */
83
static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
84
{
85
- static const GVecGen3 bsl_op = {
86
- .fni8 = gen_bsl_i64,
87
- .fniv = gen_bsl_vec,
88
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
89
- .load_dest = true
90
- };
91
- static const GVecGen3 bit_op = {
92
- .fni8 = gen_bit_i64,
93
- .fniv = gen_bit_vec,
94
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
95
- .load_dest = true
96
- };
97
- static const GVecGen3 bif_op = {
98
- .fni8 = gen_bif_i64,
99
- .fniv = gen_bif_vec,
100
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
101
- .load_dest = true
102
- };
103
-
104
int rd = extract32(insn, 0, 5);
105
int rn = extract32(insn, 5, 5);
106
int rm = extract32(insn, 16, 5);
107
diff --git a/target/arm/translate.c b/target/arm/translate.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/translate.c
110
+++ b/target/arm/translate.c
111
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
112
return 0;
113
}
114
115
-/* Bitwise select. dest = c ? t : f. Clobbers T and F. */
116
-static void gen_neon_bsl(TCGv_i32 dest, TCGv_i32 t, TCGv_i32 f, TCGv_i32 c)
117
-{
118
- tcg_gen_and_i32(t, t, c);
119
- tcg_gen_andc_i32(f, f, c);
120
- tcg_gen_or_i32(dest, t, f);
121
-}
122
-
123
static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
124
{
125
switch (size) {
126
@@ -XXX,XX +XXX,XX @@ static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
127
return 1;
128
}
129
130
+/*
131
+ * Expanders for VBitOps_VBIF, VBIT, VBSL.
132
+ */
133
+static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
134
+{
135
+ tcg_gen_xor_i64(rn, rn, rm);
136
+ tcg_gen_and_i64(rn, rn, rd);
137
+ tcg_gen_xor_i64(rd, rm, rn);
138
+}
139
+
140
+static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
141
+{
142
+ tcg_gen_xor_i64(rn, rn, rd);
143
+ tcg_gen_and_i64(rn, rn, rm);
144
+ tcg_gen_xor_i64(rd, rd, rn);
145
+}
146
+
147
+static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
148
+{
149
+ tcg_gen_xor_i64(rn, rn, rd);
150
+ tcg_gen_andc_i64(rn, rn, rm);
151
+ tcg_gen_xor_i64(rd, rd, rn);
152
+}
153
+
154
+static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
155
+{
156
+ tcg_gen_xor_vec(vece, rn, rn, rm);
157
+ tcg_gen_and_vec(vece, rn, rn, rd);
158
+ tcg_gen_xor_vec(vece, rd, rm, rn);
159
+}
160
+
161
+static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
162
+{
163
+ tcg_gen_xor_vec(vece, rn, rn, rd);
164
+ tcg_gen_and_vec(vece, rn, rn, rm);
165
+ tcg_gen_xor_vec(vece, rd, rd, rn);
166
+}
167
+
168
+static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
169
+{
170
+ tcg_gen_xor_vec(vece, rn, rn, rd);
171
+ tcg_gen_andc_vec(vece, rn, rn, rm);
172
+ tcg_gen_xor_vec(vece, rd, rd, rn);
173
+}
174
+
175
+const GVecGen3 bsl_op = {
176
+ .fni8 = gen_bsl_i64,
177
+ .fniv = gen_bsl_vec,
178
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
179
+ .load_dest = true
180
+};
181
+
182
+const GVecGen3 bit_op = {
183
+ .fni8 = gen_bit_i64,
184
+ .fniv = gen_bit_vec,
185
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
186
+ .load_dest = true
187
+};
188
+
189
+const GVecGen3 bif_op = {
190
+ .fni8 = gen_bif_i64,
191
+ .fniv = gen_bif_vec,
192
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
193
+ .load_dest = true
194
+};
195
+
196
+
197
/* Translate a NEON data processing instruction. Return nonzero if the
198
instruction is invalid.
199
We process data in a mixture of 32-bit and 64-bit chunks.
200
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
201
{
202
int op;
203
int q;
204
- int rd, rn, rm;
205
+ int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs;
206
int size;
207
int shift;
208
int pass;
209
int count;
210
int pairwise;
211
int u;
212
+ int vec_size;
213
uint32_t imm, mask;
214
TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
215
TCGv_ptr ptr1, ptr2, ptr3;
216
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
217
VFP_DREG_N(rn, insn);
218
VFP_DREG_M(rm, insn);
219
size = (insn >> 20) & 3;
220
+ vec_size = q ? 16 : 8;
221
+ rd_ofs = neon_reg_offset(rd, 0);
222
+ rn_ofs = neon_reg_offset(rn, 0);
223
+ rm_ofs = neon_reg_offset(rm, 0);
224
+
225
if ((insn & (1 << 23)) == 0) {
226
/* Three register same length. */
227
op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
228
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
229
q, rd, rn, rm);
230
}
231
return 1;
232
+
233
+ case NEON_3R_LOGIC: /* Logic ops. */
234
+ switch ((u << 2) | size) {
235
+ case 0: /* VAND */
236
+ tcg_gen_gvec_and(0, rd_ofs, rn_ofs, rm_ofs,
237
+ vec_size, vec_size);
238
+ break;
239
+ case 1: /* VBIC */
240
+ tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
241
+ vec_size, vec_size);
242
+ break;
243
+ case 2:
244
+ if (rn == rm) {
245
+ /* VMOV */
246
+ tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size);
247
+ } else {
248
+ /* VORR */
249
+ tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
250
+ vec_size, vec_size);
251
+ }
252
+ break;
253
+ case 3: /* VORN */
254
+ tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
255
+ vec_size, vec_size);
256
+ break;
257
+ case 4: /* VEOR */
258
+ tcg_gen_gvec_xor(0, rd_ofs, rn_ofs, rm_ofs,
259
+ vec_size, vec_size);
260
+ break;
261
+ case 5: /* VBSL */
262
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
263
+ vec_size, vec_size, &bsl_op);
264
+ break;
265
+ case 6: /* VBIT */
266
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
267
+ vec_size, vec_size, &bit_op);
268
+ break;
269
+ case 7: /* VBIF */
270
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
271
+ vec_size, vec_size, &bif_op);
272
+ break;
273
+ }
274
+ return 0;
275
}
276
- if (size == 3 && op != NEON_3R_LOGIC) {
277
+ if (size == 3) {
278
/* 64-bit element instructions. */
279
for (pass = 0; pass < (q ? 2 : 1); pass++) {
280
neon_load_reg64(cpu_V0, rn + pass);
281
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
282
case NEON_3R_VRHADD:
283
GEN_NEON_INTEGER_OP(rhadd);
284
break;
285
- case NEON_3R_LOGIC: /* Logic ops. */
286
- switch ((u << 2) | size) {
287
- case 0: /* VAND */
288
- tcg_gen_and_i32(tmp, tmp, tmp2);
289
- break;
290
- case 1: /* BIC */
291
- tcg_gen_andc_i32(tmp, tmp, tmp2);
292
- break;
293
- case 2: /* VORR */
294
- tcg_gen_or_i32(tmp, tmp, tmp2);
295
- break;
296
- case 3: /* VORN */
297
- tcg_gen_orc_i32(tmp, tmp, tmp2);
298
- break;
299
- case 4: /* VEOR */
300
- tcg_gen_xor_i32(tmp, tmp, tmp2);
301
- break;
302
- case 5: /* VBSL */
303
- tmp3 = neon_load_reg(rd, pass);
304
- gen_neon_bsl(tmp, tmp, tmp2, tmp3);
305
- tcg_temp_free_i32(tmp3);
306
- break;
307
- case 6: /* VBIT */
308
- tmp3 = neon_load_reg(rd, pass);
309
- gen_neon_bsl(tmp, tmp, tmp3, tmp2);
310
- tcg_temp_free_i32(tmp3);
311
- break;
312
- case 7: /* VBIF */
313
- tmp3 = neon_load_reg(rd, pass);
314
- gen_neon_bsl(tmp, tmp3, tmp, tmp2);
315
- tcg_temp_free_i32(tmp3);
316
- break;
317
- }
318
- break;
319
case NEON_3R_VHSUB:
320
GEN_NEON_INTEGER_OP(hsub);
321
break;
322
--
89
--
323
2.19.1
90
2.34.1
324
325
diff view generated by jsdifflib
[Qemu-devel] [PULL 38/45] target/arm: Use gvec for NEON VLD all lanes
[PULL 04/21] hw/arm/smmuv3: Refactor stage-1 PTW
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
In preparation for adding stage-2 support, rename smmu_ptw_64 to
4
Message-id: 20181011205206.3552-18-richard.henderson@linaro.org
4
smmu_ptw_64_s1 and refactor some of the code so it can be reused in
5
[PMM: added parens in ?: expression]
5
stage-2 page table walk.
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
7
Remove AA64 check from PTW as decode_cd already ensures that AA64 is
8
used, otherwise it faults with C_BAD_CD.
9
10
A stage member is added to SMMUPTWEventInfo to differentiate
11
between stage-1 and stage-2 ptw faults.
12
13
Add stage argument to trace_smmu_ptw_level be consistent with other
14
trace events.
15
16
Signed-off-by: Mostafa Saleh <smostafa@google.com>
17
Reviewed-by: Eric Auger <eric.auger@redhat.com>
18
Tested-by: Eric Auger <eric.auger@redhat.com>
19
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
20
Message-id: 20230516203327.2051088-4-smostafa@google.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
22
---
9
target/arm/translate.c | 81 ++++++++++++++----------------------------
23
include/hw/arm/smmu-common.h | 16 +++++++++++++---
10
1 file changed, 26 insertions(+), 55 deletions(-)
24
hw/arm/smmu-common.c | 27 ++++++++++-----------------
25
hw/arm/smmuv3.c | 2 ++
26
hw/arm/trace-events | 2 +-
27
4 files changed, 26 insertions(+), 21 deletions(-)
11
28
12
diff --git a/target/arm/translate.c b/target/arm/translate.c
29
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
13
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate.c
31
--- a/include/hw/arm/smmu-common.h
15
+++ b/target/arm/translate.c
32
+++ b/include/hw/arm/smmu-common.h
16
@@ -XXX,XX +XXX,XX @@ static void gen_vfp_msr(TCGv_i32 tmp)
33
@@ -XXX,XX +XXX,XX @@
17
tcg_temp_free_i32(tmp);
34
#include "hw/pci/pci.h"
35
#include "qom/object.h"
36
37
-#define SMMU_PCI_BUS_MAX 256
38
-#define SMMU_PCI_DEVFN_MAX 256
39
-#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
40
+#define SMMU_PCI_BUS_MAX 256
41
+#define SMMU_PCI_DEVFN_MAX 256
42
+#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
43
+
44
+/* VMSAv8-64 Translation constants and functions */
45
+#define VMSA_LEVELS 4
46
+
47
+#define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1)
48
+#define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \
49
+ (VMSA_LEVELS - (lvl)))
50
+#define VMSA_IDXMSK(isz, strd, lvl) ((1ULL << \
51
+ VMSA_BIT_LVL(isz, strd, lvl)) - 1)
52
53
/*
54
* Page table walk error types
55
@@ -XXX,XX +XXX,XX @@ typedef enum {
56
} SMMUPTWEventType;
57
58
typedef struct SMMUPTWEventInfo {
59
+ int stage;
60
SMMUPTWEventType type;
61
dma_addr_t addr; /* fetched address that induced an abort, if any */
62
} SMMUPTWEventInfo;
63
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/smmu-common.c
66
+++ b/hw/arm/smmu-common.c
67
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
18
}
68
}
19
69
20
-static void gen_neon_dup_u8(TCGv_i32 var, int shift)
70
/**
21
-{
71
- * smmu_ptw_64 - VMSAv8-64 Walk of the page tables for a given IOVA
22
- TCGv_i32 tmp = tcg_temp_new_i32();
72
+ * smmu_ptw_64_s1 - VMSAv8-64 Walk of the page tables for a given IOVA
23
- if (shift)
73
* @cfg: translation config
24
- tcg_gen_shri_i32(var, var, shift);
74
* @iova: iova to translate
25
- tcg_gen_ext8u_i32(var, var);
75
* @perm: access type
26
- tcg_gen_shli_i32(tmp, var, 8);
76
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
27
- tcg_gen_or_i32(var, var, tmp);
77
* Upon success, @tlbe is filled with translated_addr and entry
28
- tcg_gen_shli_i32(tmp, var, 16);
78
* permission rights.
29
- tcg_gen_or_i32(var, var, tmp);
79
*/
30
- tcg_temp_free_i32(tmp);
80
-static int smmu_ptw_64(SMMUTransCfg *cfg,
31
-}
81
- dma_addr_t iova, IOMMUAccessFlags perm,
82
- SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
83
+static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
84
+ dma_addr_t iova, IOMMUAccessFlags perm,
85
+ SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
86
{
87
dma_addr_t baseaddr, indexmask;
88
int stage = cfg->stage;
89
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
90
}
91
92
granule_sz = tt->granule_sz;
93
- stride = granule_sz - 3;
94
+ stride = VMSA_STRIDE(granule_sz);
95
inputsize = 64 - tt->tsz;
96
level = 4 - (inputsize - 4) / stride;
97
- indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
98
+ indexmask = VMSA_IDXMSK(inputsize, stride, level);
99
baseaddr = extract64(tt->ttb, 0, 48);
100
baseaddr &= ~indexmask;
101
102
- while (level <= 3) {
103
+ while (level < VMSA_LEVELS) {
104
uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
105
uint64_t mask = subpage_size - 1;
106
uint32_t offset = iova_level_offset(iova, inputsize, level, granule_sz);
107
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
108
if (get_pte(baseaddr, offset, &pte, info)) {
109
goto error;
110
}
111
- trace_smmu_ptw_level(level, iova, subpage_size,
112
+ trace_smmu_ptw_level(stage, level, iova, subpage_size,
113
baseaddr, offset, pte);
114
115
if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
116
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
117
info->type = SMMU_PTW_ERR_TRANSLATION;
118
119
error:
120
+ info->stage = 1;
121
tlbe->entry.perm = IOMMU_NONE;
122
return -EINVAL;
123
}
124
@@ -XXX,XX +XXX,XX @@ error:
125
int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
126
SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
127
{
128
- if (!cfg->aa64) {
129
- /*
130
- * This code path is not entered as we check this while decoding
131
- * the configuration data in the derived SMMU model.
132
- */
133
- g_assert_not_reached();
134
- }
32
-
135
-
33
static void gen_neon_dup_low16(TCGv_i32 var)
136
- return smmu_ptw_64(cfg, iova, perm, tlbe, info);
34
{
137
+ return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info);
35
TCGv_i32 tmp = tcg_temp_new_i32();
36
@@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var)
37
tcg_temp_free_i32(tmp);
38
}
138
}
39
139
40
-static TCGv_i32 gen_load_and_replicate(DisasContext *s, TCGv_i32 addr, int size)
140
/**
41
-{
141
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
42
- /* Load a single Neon element and replicate into a 32 bit TCG reg */
142
index XXXXXXX..XXXXXXX 100644
43
- TCGv_i32 tmp = tcg_temp_new_i32();
143
--- a/hw/arm/smmuv3.c
44
- switch (size) {
144
+++ b/hw/arm/smmuv3.c
45
- case 0:
145
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
46
- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
146
cached_entry = g_new0(SMMUTLBEntry, 1);
47
- gen_neon_dup_u8(tmp, 0);
147
48
- break;
148
if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) {
49
- case 1:
149
+ /* All faults from PTW has S2 field. */
50
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
150
+ event.u.f_walk_eabt.s2 = (ptw_info.stage == 2);
51
- gen_neon_dup_low16(tmp);
151
g_free(cached_entry);
52
- break;
152
switch (ptw_info.type) {
53
- case 2:
153
case SMMU_PTW_ERR_WALK_EABT:
54
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
154
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
55
- break;
155
index XXXXXXX..XXXXXXX 100644
56
- default: /* Avoid compiler warnings. */
156
--- a/hw/arm/trace-events
57
- abort();
157
+++ b/hw/arm/trace-events
58
- }
158
@@ -XXX,XX +XXX,XX @@ virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."
59
- return tmp;
159
60
-}
160
# smmu-common.c
61
-
161
smmu_add_mr(const char *name) "%s"
62
static int handle_vsel(uint32_t insn, uint32_t rd, uint32_t rn, uint32_t rm,
162
-smmu_ptw_level(int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64
63
uint32_t dp)
163
+smmu_ptw_level(int stage, int level, uint64_t iova, size_t subpage_size, uint64_t baseaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d iova=0x%"PRIx64" subpage_sz=0x%zx baseaddr=0x%"PRIx64" offset=%d => pte=0x%"PRIx64
64
{
164
smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint32_t offset, uint64_t pte) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" offset=%d pte=0x%"PRIx64
65
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
165
smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64
66
int load;
166
smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"
67
int shift;
68
int n;
69
+ int vec_size;
70
TCGv_i32 addr;
71
TCGv_i32 tmp;
72
TCGv_i32 tmp2;
73
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
74
}
75
addr = tcg_temp_new_i32();
76
load_reg_var(s, addr, rn);
77
- if (nregs == 1) {
78
- /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
79
- tmp = gen_load_and_replicate(s, addr, size);
80
- tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
81
- tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
82
- if (insn & (1 << 5)) {
83
- tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0));
84
- tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1));
85
- }
86
- tcg_temp_free_i32(tmp);
87
- } else {
88
- /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
89
- stride = (insn & (1 << 5)) ? 2 : 1;
90
- for (reg = 0; reg < nregs; reg++) {
91
- tmp = gen_load_and_replicate(s, addr, size);
92
- tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
93
- tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
94
- tcg_temp_free_i32(tmp);
95
- tcg_gen_addi_i32(addr, addr, 1 << size);
96
- rd += stride;
97
+
98
+ /* VLD1 to all lanes: bit 5 indicates how many Dregs to write.
99
+ * VLD2/3/4 to all lanes: bit 5 indicates register stride.
100
+ */
101
+ stride = (insn & (1 << 5)) ? 2 : 1;
102
+ vec_size = nregs == 1 ? stride * 8 : 8;
103
+
104
+ tmp = tcg_temp_new_i32();
105
+ for (reg = 0; reg < nregs; reg++) {
106
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
107
+ s->be_data | size);
108
+ if ((rd & 1) && vec_size == 16) {
109
+ /* We cannot write 16 bytes at once because the
110
+ * destination is unaligned.
111
+ */
112
+ tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0),
113
+ 8, 8, tmp);
114
+ tcg_gen_gvec_mov(0, neon_reg_offset(rd + 1, 0),
115
+ neon_reg_offset(rd, 0), 8, 8);
116
+ } else {
117
+ tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0),
118
+ vec_size, vec_size, tmp);
119
}
120
+ tcg_gen_addi_i32(addr, addr, 1 << size);
121
+ rd += stride;
122
}
123
+ tcg_temp_free_i32(tmp);
124
tcg_temp_free_i32(addr);
125
stride = (1 << size) * nregs;
126
} else {
127
--
167
--
128
2.19.1
168
2.34.1
129
130
diff view generated by jsdifflib
[Qemu-devel] [PULL 41/45] target/arm: Reorg NEON VLD/VST single element to one lane
[PULL 05/21] hw/arm/smmuv3: Add page table walk for stage-2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
Instead of shifts and masks, use direct loads and stores from
3
In preparation for adding stage-2 support, add Stage-2 PTW code.
4
the neon register file.
4
Only Aarch64 format is supported as stage-1.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Nesting stage-1 and stage-2 is not supported right now.
7
Message-id: 20181011205206.3552-21-richard.henderson@linaro.org
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
HTTU is not supported, SW is expected to maintain the Access flag.
9
This is described in the SMMUv3 manual(IHI 0070.E.a)
10
"5.2. Stream Table Entry" in "[181] S2AFFD".
11
This flag determines the behavior on access of a stage-2 page whose
12
descriptor has AF == 0:
13
- 0b0: An Access flag fault occurs (stall not supported).
14
- 0b1: An Access flag fault never occurs.
15
An Access fault takes priority over a Permission fault.
16
17
There are 3 address size checks for stage-2 according to
18
(IHI 0070.E.a) in "3.4. Address sizes".
19
- As nesting is not supported, input address is passed directly to
20
stage-2, and is checked against IAS.
21
We use cfg->oas to hold the OAS when stage-1 is not used, this is set
22
in the next patch.
23
This check is done outside of smmu_ptw_64_s2 as it is not part of
24
stage-2(it throws stage-1 fault), and the stage-2 function shouldn't
25
change it's behavior when nesting is supported.
26
When nesting is supported and we figure out how to combine TLB for
27
stage-1 and stage-2 we can move this check into the stage-1 function
28
as described in ARM DDI0487I.a in pseudocode
29
aarch64/translation/vmsa_translation/AArch64.S1Translate
30
aarch64/translation/vmsa_translation/AArch64.S1DisabledOutput
31
32
- Input to stage-2 is checked against s2t0sz, and throws stage-2
33
transaltion fault if exceeds it.
34
35
- Output of stage-2 is checked against effective PA output range.
36
37
Reviewed-by: Eric Auger <eric.auger@redhat.com>
38
Signed-off-by: Mostafa Saleh <smostafa@google.com>
39
Tested-by: Eric Auger <eric.auger@redhat.com>
40
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
41
Message-id: 20230516203327.2051088-5-smostafa@google.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
43
---
11
target/arm/translate.c | 92 +++++++++++++++++++++++-------------------
44
hw/arm/smmu-internal.h | 35 ++++++++++
12
1 file changed, 50 insertions(+), 42 deletions(-)
45
hw/arm/smmu-common.c | 142 ++++++++++++++++++++++++++++++++++++++++-
13
46
2 files changed, 176 insertions(+), 1 deletion(-)
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
47
48
diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
15
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
50
--- a/hw/arm/smmu-internal.h
17
+++ b/target/arm/translate.c
51
+++ b/hw/arm/smmu-internal.h
18
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 neon_load_reg(int reg, int pass)
52
@@ -XXX,XX +XXX,XX @@
19
return tmp;
53
#define PTE_APTABLE(pte) \
54
(extract64(pte, 61, 2))
55
56
+#define PTE_AF(pte) \
57
+ (extract64(pte, 10, 1))
58
/*
59
* TODO: At the moment all transactions are considered as privileged (EL1)
60
* as IOMMU translation callback does not pass user/priv attributes.
61
@@ -XXX,XX +XXX,XX @@
62
#define is_permission_fault(ap, perm) \
63
(((perm) & IOMMU_WO) && ((ap) & 0x2))
64
65
+#define is_permission_fault_s2(s2ap, perm) \
66
+ (!(((s2ap) & (perm)) == (perm)))
67
+
68
#define PTE_AP_TO_PERM(ap) \
69
(IOMMU_ACCESS_FLAG(true, !((ap) & 0x2)))
70
71
@@ -XXX,XX +XXX,XX @@ uint64_t iova_level_offset(uint64_t iova, int inputsize,
72
MAKE_64BIT_MASK(0, gsz - 3);
20
}
73
}
21
74
22
+static void neon_load_element(TCGv_i32 var, int reg, int ele, TCGMemOp mop)
75
+/* FEAT_LPA2 and FEAT_TTST are not implemented. */
76
+static inline int get_start_level(int sl0 , int granule_sz)
23
+{
77
+{
24
+ long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
78
+ /* ARM DDI0487I.a: Table D8-12. */
25
+
79
+ if (granule_sz == 12) {
26
+ switch (mop) {
80
+ return 2 - sl0;
27
+ case MO_UB:
81
+ }
28
+ tcg_gen_ld8u_i32(var, cpu_env, offset);
82
+ /* ARM DDI0487I.a: Table D8-22 and Table D8-31. */
29
+ break;
83
+ return 3 - sl0;
30
+ case MO_UW:
31
+ tcg_gen_ld16u_i32(var, cpu_env, offset);
32
+ break;
33
+ case MO_UL:
34
+ tcg_gen_ld_i32(var, cpu_env, offset);
35
+ break;
36
+ default:
37
+ g_assert_not_reached();
38
+ }
39
+}
84
+}
40
+
85
+
41
static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp mop)
86
+/*
87
+ * Index in a concatenated first level stage-2 page table.
88
+ * ARM DDI0487I.a: D8.2.2 Concatenated translation tables.
89
+ */
90
+static inline int pgd_concat_idx(int start_level, int granule_sz,
91
+ dma_addr_t ipa)
92
+{
93
+ uint64_t ret;
94
+ /*
95
+ * Get the number of bits handled by next levels, then any extra bits in
96
+ * the address should index the concatenated tables. This relation can be
97
+ * deduced from tables in ARM DDI0487I.a: D8.2.7-9
98
+ */
99
+ int shift = level_shift(start_level - 1, granule_sz);
100
+
101
+ ret = ipa >> shift;
102
+ return ret;
103
+}
104
+
105
#define SMMU_IOTLB_ASID(key) ((key).asid)
106
107
typedef struct SMMUIOTLBPageInvInfo {
108
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/arm/smmu-common.c
111
+++ b/hw/arm/smmu-common.c
112
@@ -XXX,XX +XXX,XX @@ error:
113
return -EINVAL;
114
}
115
116
+/**
117
+ * smmu_ptw_64_s2 - VMSAv8-64 Walk of the page tables for a given ipa
118
+ * for stage-2.
119
+ * @cfg: translation config
120
+ * @ipa: ipa to translate
121
+ * @perm: access type
122
+ * @tlbe: SMMUTLBEntry (out)
123
+ * @info: handle to an error info
124
+ *
125
+ * Return 0 on success, < 0 on error. In case of error, @info is filled
126
+ * and tlbe->perm is set to IOMMU_NONE.
127
+ * Upon success, @tlbe is filled with translated_addr and entry
128
+ * permission rights.
129
+ */
130
+static int smmu_ptw_64_s2(SMMUTransCfg *cfg,
131
+ dma_addr_t ipa, IOMMUAccessFlags perm,
132
+ SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
133
+{
134
+ const int stage = 2;
135
+ int granule_sz = cfg->s2cfg.granule_sz;
136
+ /* ARM DDI0487I.a: Table D8-7. */
137
+ int inputsize = 64 - cfg->s2cfg.tsz;
138
+ int level = get_start_level(cfg->s2cfg.sl0, granule_sz);
139
+ int stride = VMSA_STRIDE(granule_sz);
140
+ int idx = pgd_concat_idx(level, granule_sz, ipa);
141
+ /*
142
+ * Get the ttb from concatenated structure.
143
+ * The offset is the idx * size of each ttb(number of ptes * (sizeof(pte))
144
+ */
145
+ uint64_t baseaddr = extract64(cfg->s2cfg.vttb, 0, 48) + (1 << stride) *
146
+ idx * sizeof(uint64_t);
147
+ dma_addr_t indexmask = VMSA_IDXMSK(inputsize, stride, level);
148
+
149
+ baseaddr &= ~indexmask;
150
+
151
+ /*
152
+ * On input, a stage 2 Translation fault occurs if the IPA is outside the
153
+ * range configured by the relevant S2T0SZ field of the STE.
154
+ */
155
+ if (ipa >= (1ULL << inputsize)) {
156
+ info->type = SMMU_PTW_ERR_TRANSLATION;
157
+ goto error;
158
+ }
159
+
160
+ while (level < VMSA_LEVELS) {
161
+ uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
162
+ uint64_t mask = subpage_size - 1;
163
+ uint32_t offset = iova_level_offset(ipa, inputsize, level, granule_sz);
164
+ uint64_t pte, gpa;
165
+ dma_addr_t pte_addr = baseaddr + offset * sizeof(pte);
166
+ uint8_t s2ap;
167
+
168
+ if (get_pte(baseaddr, offset, &pte, info)) {
169
+ goto error;
170
+ }
171
+ trace_smmu_ptw_level(stage, level, ipa, subpage_size,
172
+ baseaddr, offset, pte);
173
+ if (is_invalid_pte(pte) || is_reserved_pte(pte, level)) {
174
+ trace_smmu_ptw_invalid_pte(stage, level, baseaddr,
175
+ pte_addr, offset, pte);
176
+ break;
177
+ }
178
+
179
+ if (is_table_pte(pte, level)) {
180
+ baseaddr = get_table_pte_address(pte, granule_sz);
181
+ level++;
182
+ continue;
183
+ } else if (is_page_pte(pte, level)) {
184
+ gpa = get_page_pte_address(pte, granule_sz);
185
+ trace_smmu_ptw_page_pte(stage, level, ipa,
186
+ baseaddr, pte_addr, pte, gpa);
187
+ } else {
188
+ uint64_t block_size;
189
+
190
+ gpa = get_block_pte_address(pte, level, granule_sz,
191
+ &block_size);
192
+ trace_smmu_ptw_block_pte(stage, level, baseaddr,
193
+ pte_addr, pte, ipa, gpa,
194
+ block_size >> 20);
195
+ }
196
+
197
+ /*
198
+ * If S2AFFD and PTE.AF are 0 => fault. (5.2. Stream Table Entry)
199
+ * An Access fault takes priority over a Permission fault.
200
+ */
201
+ if (!PTE_AF(pte) && !cfg->s2cfg.affd) {
202
+ info->type = SMMU_PTW_ERR_ACCESS;
203
+ goto error;
204
+ }
205
+
206
+ s2ap = PTE_AP(pte);
207
+ if (is_permission_fault_s2(s2ap, perm)) {
208
+ info->type = SMMU_PTW_ERR_PERMISSION;
209
+ goto error;
210
+ }
211
+
212
+ /*
213
+ * The address output from the translation causes a stage 2 Address
214
+ * Size fault if it exceeds the effective PA output range.
215
+ */
216
+ if (gpa >= (1ULL << cfg->s2cfg.eff_ps)) {
217
+ info->type = SMMU_PTW_ERR_ADDR_SIZE;
218
+ goto error;
219
+ }
220
+
221
+ tlbe->entry.translated_addr = gpa;
222
+ tlbe->entry.iova = ipa & ~mask;
223
+ tlbe->entry.addr_mask = mask;
224
+ tlbe->entry.perm = s2ap;
225
+ tlbe->level = level;
226
+ tlbe->granule = granule_sz;
227
+ return 0;
228
+ }
229
+ info->type = SMMU_PTW_ERR_TRANSLATION;
230
+
231
+error:
232
+ info->stage = 2;
233
+ tlbe->entry.perm = IOMMU_NONE;
234
+ return -EINVAL;
235
+}
236
+
237
/**
238
* smmu_ptw - Walk the page tables for an IOVA, according to @cfg
239
*
240
@@ -XXX,XX +XXX,XX @@ error:
241
int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
242
SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
42
{
243
{
43
long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
244
- return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info);
44
@@ -XXX,XX +XXX,XX @@ static void neon_store_reg(int reg, int pass, TCGv_i32 var)
245
+ if (cfg->stage == 1) {
45
tcg_temp_free_i32(var);
246
+ return smmu_ptw_64_s1(cfg, iova, perm, tlbe, info);
247
+ } else if (cfg->stage == 2) {
248
+ /*
249
+ * If bypassing stage 1(or unimplemented), the input address is passed
250
+ * directly to stage 2 as IPA. If the input address of a transaction
251
+ * exceeds the size of the IAS, a stage 1 Address Size fault occurs.
252
+ * For AA64, IAS = OAS according to (IHI 0070.E.a) "3.4 Address sizes"
253
+ */
254
+ if (iova >= (1ULL << cfg->oas)) {
255
+ info->type = SMMU_PTW_ERR_ADDR_SIZE;
256
+ info->stage = 1;
257
+ tlbe->entry.perm = IOMMU_NONE;
258
+ return -EINVAL;
259
+ }
260
+
261
+ return smmu_ptw_64_s2(cfg, iova, perm, tlbe, info);
262
+ }
263
+
264
+ g_assert_not_reached();
46
}
265
}
47
266
48
+static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 var)
267
/**
49
+{
50
+ long offset = neon_element_offset(reg, ele, size);
51
+
52
+ switch (size) {
53
+ case MO_8:
54
+ tcg_gen_st8_i32(var, cpu_env, offset);
55
+ break;
56
+ case MO_16:
57
+ tcg_gen_st16_i32(var, cpu_env, offset);
58
+ break;
59
+ case MO_32:
60
+ tcg_gen_st_i32(var, cpu_env, offset);
61
+ break;
62
+ default:
63
+ g_assert_not_reached();
64
+ }
65
+}
66
+
67
static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)
68
{
69
long offset = neon_element_offset(reg, ele, size);
70
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
71
int stride;
72
int size;
73
int reg;
74
- int pass;
75
int load;
76
- int shift;
77
int n;
78
int vec_size;
79
int mmu_idx;
80
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
81
} else {
82
/* Single element. */
83
int idx = (insn >> 4) & 0xf;
84
- pass = (insn >> 7) & 1;
85
+ int reg_idx;
86
switch (size) {
87
case 0:
88
- shift = ((insn >> 5) & 3) * 8;
89
+ reg_idx = (insn >> 5) & 7;
90
stride = 1;
91
break;
92
case 1:
93
- shift = ((insn >> 6) & 1) * 16;
94
+ reg_idx = (insn >> 6) & 3;
95
stride = (insn & (1 << 5)) ? 2 : 1;
96
break;
97
case 2:
98
- shift = 0;
99
+ reg_idx = (insn >> 7) & 1;
100
stride = (insn & (1 << 6)) ? 2 : 1;
101
break;
102
default:
103
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
104
*/
105
return 1;
106
}
107
+ tmp = tcg_temp_new_i32();
108
addr = tcg_temp_new_i32();
109
load_reg_var(s, addr, rn);
110
for (reg = 0; reg < nregs; reg++) {
111
if (load) {
112
- tmp = tcg_temp_new_i32();
113
- switch (size) {
114
- case 0:
115
- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
116
- break;
117
- case 1:
118
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
119
- break;
120
- case 2:
121
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
122
- break;
123
- default: /* Avoid compiler warnings. */
124
- abort();
125
- }
126
- if (size != 2) {
127
- tmp2 = neon_load_reg(rd, pass);
128
- tcg_gen_deposit_i32(tmp, tmp2, tmp,
129
- shift, size ? 16 : 8);
130
- tcg_temp_free_i32(tmp2);
131
- }
132
- neon_store_reg(rd, pass, tmp);
133
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
134
+ s->be_data | size);
135
+ neon_store_element(rd, reg_idx, size, tmp);
136
} else { /* Store */
137
- tmp = neon_load_reg(rd, pass);
138
- if (shift)
139
- tcg_gen_shri_i32(tmp, tmp, shift);
140
- switch (size) {
141
- case 0:
142
- gen_aa32_st8(s, tmp, addr, get_mem_index(s));
143
- break;
144
- case 1:
145
- gen_aa32_st16(s, tmp, addr, get_mem_index(s));
146
- break;
147
- case 2:
148
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
149
- break;
150
- }
151
- tcg_temp_free_i32(tmp);
152
+ neon_load_element(tmp, rd, reg_idx, size);
153
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
154
+ s->be_data | size);
155
}
156
rd += stride;
157
tcg_gen_addi_i32(addr, addr, 1 << size);
158
}
159
tcg_temp_free_i32(addr);
160
+ tcg_temp_free_i32(tmp);
161
stride = nregs * (1 << size);
162
}
163
}
164
--
268
--
165
2.19.1
269
2.34.1
166
167
diff view generated by jsdifflib
[Qemu-devel] [PULL 39/45] target/arm: Reorg NEON VLD/VST all elements
[PULL 06/21] hw/arm/smmuv3: Parse STE config for stage-2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
Instead of shifts and masks, use direct loads and stores from the neon
3
Parse stage-2 configuration from STE and populate it in SMMUS2Cfg.
4
register file. Mirror the iteration structure of the ARM pseudocode
4
Validity of field values are checked when possible.
5
more closely. Correct the parameters of the VLD2 A2 insn.
5
6
6
Only AA64 tables are supported and Small Translation Tables (STT) are
7
Note that this includes a bugfix for handling of the insn
7
not supported.
8
"VLD2 (multiple 2-element structures)" -- we were using an
8
9
incorrect stride value.
9
According to SMMUv3 UM(IHI0070E) "5.2 Stream Table Entry": All fields
10
10
with an S2 prefix (with the exception of S2VMID) are IGNORED when
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
stage-2 bypasses translation (Config[1] == 0).
12
Message-id: 20181011205206.3552-19-richard.henderson@linaro.org
12
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Which means that VMID can be used(for TLB tagging) even if stage-2 is
14
bypassed, so we parse it unconditionally when S2P exists. Otherwise
15
it is set to -1.(only S1P)
16
17
As stall is not supported, if S2S is set the translation would abort.
18
For S2R, we reuse the same code used for stage-1 with flag
19
record_faults. However when nested translation is supported we would
20
need to separate stage-1 and stage-2 faults.
21
22
Fix wrong shift in STE_S2HD, STE_S2HA, STE_S2S.
23
24
Signed-off-by: Mostafa Saleh <smostafa@google.com>
25
Tested-by: Eric Auger <eric.auger@redhat.com>
26
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
27
Reviewed-by: Eric Auger <eric.auger@redhat.com>
28
Message-id: 20230516203327.2051088-6-smostafa@google.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
30
---
16
target/arm/translate.c | 170 ++++++++++++++++++-----------------------
31
hw/arm/smmuv3-internal.h | 10 +-
17
1 file changed, 74 insertions(+), 96 deletions(-)
32
include/hw/arm/smmu-common.h | 1 +
18
33
include/hw/arm/smmuv3.h | 3 +
19
diff --git a/target/arm/translate.c b/target/arm/translate.c
34
hw/arm/smmuv3.c | 181 +++++++++++++++++++++++++++++++++--
35
4 files changed, 185 insertions(+), 10 deletions(-)
36
37
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
20
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate.c
39
--- a/hw/arm/smmuv3-internal.h
22
+++ b/target/arm/translate.c
40
+++ b/hw/arm/smmuv3-internal.h
23
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 neon_load_reg(int reg, int pass)
41
@@ -XXX,XX +XXX,XX @@ typedef struct CD {
24
return tmp;
42
#define STE_S2TG(x) extract32((x)->word[5], 14, 2)
43
#define STE_S2PS(x) extract32((x)->word[5], 16, 3)
44
#define STE_S2AA64(x) extract32((x)->word[5], 19, 1)
45
-#define STE_S2HD(x) extract32((x)->word[5], 24, 1)
46
-#define STE_S2HA(x) extract32((x)->word[5], 25, 1)
47
-#define STE_S2S(x) extract32((x)->word[5], 26, 1)
48
+#define STE_S2ENDI(x) extract32((x)->word[5], 20, 1)
49
+#define STE_S2AFFD(x) extract32((x)->word[5], 21, 1)
50
+#define STE_S2HD(x) extract32((x)->word[5], 23, 1)
51
+#define STE_S2HA(x) extract32((x)->word[5], 24, 1)
52
+#define STE_S2S(x) extract32((x)->word[5], 25, 1)
53
+#define STE_S2R(x) extract32((x)->word[5], 26, 1)
54
+
55
#define STE_CTXPTR(x) \
56
({ \
57
unsigned long addr; \
58
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
59
index XXXXXXX..XXXXXXX 100644
60
--- a/include/hw/arm/smmu-common.h
61
+++ b/include/hw/arm/smmu-common.h
62
@@ -XXX,XX +XXX,XX @@
63
64
/* VMSAv8-64 Translation constants and functions */
65
#define VMSA_LEVELS 4
66
+#define VMSA_MAX_S2_CONCAT 16
67
68
#define VMSA_STRIDE(gran) ((gran) - VMSA_LEVELS + 1)
69
#define VMSA_BIT_LVL(isz, strd, lvl) ((isz) - (strd) * \
70
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/include/hw/arm/smmuv3.h
73
+++ b/include/hw/arm/smmuv3.h
74
@@ -XXX,XX +XXX,XX @@ struct SMMUv3Class {
75
#define TYPE_ARM_SMMUV3 "arm-smmuv3"
76
OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)
77
78
+#define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P)
79
+#define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P)
80
+
81
#endif
82
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/arm/smmuv3.c
85
+++ b/hw/arm/smmuv3.c
86
@@ -XXX,XX +XXX,XX @@
87
#include "smmuv3-internal.h"
88
#include "smmu-internal.h"
89
90
+#define PTW_RECORD_FAULT(cfg) (((cfg)->stage == 1) ? (cfg)->record_faults : \
91
+ (cfg)->s2cfg.record_faults)
92
+
93
/**
94
* smmuv3_trigger_irq - pulse @irq if enabled and update
95
* GERROR register in case of GERROR interrupt
96
@@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
97
return 0;
25
}
98
}
26
99
27
+static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp mop)
100
+/*
101
+ * Max valid value is 39 when SMMU_IDR3.STT == 0.
102
+ * In architectures after SMMUv3.0:
103
+ * - If STE.S2TG selects a 4KB or 16KB granule, the minimum valid value for this
104
+ * field is MAX(16, 64-IAS)
105
+ * - If STE.S2TG selects a 64KB granule, the minimum valid value for this field
106
+ * is (64-IAS).
107
+ * As we only support AA64, IAS = OAS.
108
+ */
109
+static bool s2t0sz_valid(SMMUTransCfg *cfg)
28
+{
110
+{
29
+ long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
111
+ if (cfg->s2cfg.tsz > 39) {
30
+
112
+ return false;
31
+ switch (mop) {
113
+ }
32
+ case MO_UB:
114
+
33
+ tcg_gen_ld8u_i64(var, cpu_env, offset);
115
+ if (cfg->s2cfg.granule_sz == 16) {
116
+ return (cfg->s2cfg.tsz >= 64 - oas2bits(SMMU_IDR5_OAS));
117
+ }
118
+
119
+ return (cfg->s2cfg.tsz >= MAX(64 - oas2bits(SMMU_IDR5_OAS), 16));
120
+}
121
+
122
+/*
123
+ * Return true if s2 page table config is valid.
124
+ * This checks with the configured start level, ias_bits and granularity we can
125
+ * have a valid page table as described in ARM ARM D8.2 Translation process.
126
+ * The idea here is to see for the highest possible number of IPA bits, how
127
+ * many concatenated tables we would need, if it is more than 16, then this is
128
+ * not possible.
129
+ */
130
+static bool s2_pgtable_config_valid(uint8_t sl0, uint8_t t0sz, uint8_t gran)
131
+{
132
+ int level = get_start_level(sl0, gran);
133
+ uint64_t ipa_bits = 64 - t0sz;
134
+ uint64_t max_ipa = (1ULL << ipa_bits) - 1;
135
+ int nr_concat = pgd_concat_idx(level, gran, max_ipa) + 1;
136
+
137
+ return nr_concat <= VMSA_MAX_S2_CONCAT;
138
+}
139
+
140
+static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste)
141
+{
142
+ cfg->stage = 2;
143
+
144
+ if (STE_S2AA64(ste) == 0x0) {
145
+ qemu_log_mask(LOG_UNIMP,
146
+ "SMMUv3 AArch32 tables not supported\n");
147
+ g_assert_not_reached();
148
+ }
149
+
150
+ switch (STE_S2TG(ste)) {
151
+ case 0x0: /* 4KB */
152
+ cfg->s2cfg.granule_sz = 12;
34
+ break;
153
+ break;
35
+ case MO_UW:
154
+ case 0x1: /* 64KB */
36
+ tcg_gen_ld16u_i64(var, cpu_env, offset);
155
+ cfg->s2cfg.granule_sz = 16;
37
+ break;
156
+ break;
38
+ case MO_UL:
157
+ case 0x2: /* 16KB */
39
+ tcg_gen_ld32u_i64(var, cpu_env, offset);
158
+ cfg->s2cfg.granule_sz = 14;
40
+ break;
41
+ case MO_Q:
42
+ tcg_gen_ld_i64(var, cpu_env, offset);
43
+ break;
159
+ break;
44
+ default:
160
+ default:
45
+ g_assert_not_reached();
161
+ qemu_log_mask(LOG_GUEST_ERROR,
46
+ }
162
+ "SMMUv3 bad STE S2TG: %x\n", STE_S2TG(ste));
163
+ goto bad_ste;
164
+ }
165
+
166
+ cfg->s2cfg.vttb = STE_S2TTB(ste);
167
+
168
+ cfg->s2cfg.sl0 = STE_S2SL0(ste);
169
+ /* FEAT_TTST not supported. */
170
+ if (cfg->s2cfg.sl0 == 0x3) {
171
+ qemu_log_mask(LOG_UNIMP, "SMMUv3 S2SL0 = 0x3 has no meaning!\n");
172
+ goto bad_ste;
173
+ }
174
+
175
+ /* For AA64, The effective S2PS size is capped to the OAS. */
176
+ cfg->s2cfg.eff_ps = oas2bits(MIN(STE_S2PS(ste), SMMU_IDR5_OAS));
177
+ /*
178
+ * It is ILLEGAL for the address in S2TTB to be outside the range
179
+ * described by the effective S2PS value.
180
+ */
181
+ if (cfg->s2cfg.vttb & ~(MAKE_64BIT_MASK(0, cfg->s2cfg.eff_ps))) {
182
+ qemu_log_mask(LOG_GUEST_ERROR,
183
+ "SMMUv3 S2TTB too large 0x%lx, effective PS %d bits\n",
184
+ cfg->s2cfg.vttb, cfg->s2cfg.eff_ps);
185
+ goto bad_ste;
186
+ }
187
+
188
+ cfg->s2cfg.tsz = STE_S2T0SZ(ste);
189
+
190
+ if (!s2t0sz_valid(cfg)) {
191
+ qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 bad STE S2T0SZ = %d\n",
192
+ cfg->s2cfg.tsz);
193
+ goto bad_ste;
194
+ }
195
+
196
+ if (!s2_pgtable_config_valid(cfg->s2cfg.sl0, cfg->s2cfg.tsz,
197
+ cfg->s2cfg.granule_sz)) {
198
+ qemu_log_mask(LOG_GUEST_ERROR,
199
+ "SMMUv3 STE stage 2 config not valid!\n");
200
+ goto bad_ste;
201
+ }
202
+
203
+ /* Only LE supported(IDR0.TTENDIAN). */
204
+ if (STE_S2ENDI(ste)) {
205
+ qemu_log_mask(LOG_GUEST_ERROR,
206
+ "SMMUv3 STE_S2ENDI only supports LE!\n");
207
+ goto bad_ste;
208
+ }
209
+
210
+ cfg->s2cfg.affd = STE_S2AFFD(ste);
211
+
212
+ cfg->s2cfg.record_faults = STE_S2R(ste);
213
+ /* As stall is not supported. */
214
+ if (STE_S2S(ste)) {
215
+ qemu_log_mask(LOG_UNIMP, "SMMUv3 Stall not implemented!\n");
216
+ goto bad_ste;
217
+ }
218
+
219
+ /* This is still here as stage 2 has not been fully enabled yet. */
220
+ qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
221
+ goto bad_ste;
222
+
223
+ return 0;
224
+
225
+bad_ste:
226
+ return -EINVAL;
47
+}
227
+}
48
+
228
+
49
static void neon_store_reg(int reg, int pass, TCGv_i32 var)
229
/* Returns < 0 in case of invalid STE, 0 otherwise */
230
static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
231
STE *ste, SMMUEventInfo *event)
50
{
232
{
51
tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
233
uint32_t config;
52
tcg_temp_free_i32(var);
234
+ int ret;
53
}
235
54
236
if (!STE_VALID(ste)) {
55
+static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64 var)
237
if (!event->inval_ste_allowed) {
56
+{
238
@@ -XXX,XX +XXX,XX @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
57
+ long offset = neon_element_offset(reg, ele, size);
239
return 0;
58
+
240
}
59
+ switch (size) {
241
60
+ case MO_8:
242
- if (STE_CFG_S2_ENABLED(config)) {
61
+ tcg_gen_st8_i64(var, cpu_env, offset);
243
- qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
62
+ break;
244
+ /*
63
+ case MO_16:
245
+ * If a stage is enabled in SW while not advertised, throw bad ste
64
+ tcg_gen_st16_i64(var, cpu_env, offset);
246
+ * according to user manual(IHI0070E) "5.2 Stream Table Entry".
65
+ break;
247
+ */
66
+ case MO_32:
248
+ if (!STAGE1_SUPPORTED(s) && STE_CFG_S1_ENABLED(config)) {
67
+ tcg_gen_st32_i64(var, cpu_env, offset);
249
+ qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 S1 used but not supported.\n");
68
+ break;
250
goto bad_ste;
69
+ case MO_64:
251
}
70
+ tcg_gen_st_i64(var, cpu_env, offset);
252
+ if (!STAGE2_SUPPORTED(s) && STE_CFG_S2_ENABLED(config)) {
71
+ break;
253
+ qemu_log_mask(LOG_GUEST_ERROR, "SMMUv3 S2 used but not supported.\n");
72
+ default:
254
+ goto bad_ste;
73
+ g_assert_not_reached();
255
+ }
74
+ }
256
+
75
+}
257
+ if (STAGE2_SUPPORTED(s)) {
76
+
258
+ /* VMID is considered even if s2 is disabled. */
77
static inline void neon_load_reg64(TCGv_i64 var, int reg)
259
+ cfg->s2cfg.vmid = STE_S2VMID(ste);
78
{
260
+ } else {
79
tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
261
+ /* Default to -1 */
80
@@ -XXX,XX +XXX,XX @@ static struct {
262
+ cfg->s2cfg.vmid = -1;
81
int interleave;
263
+ }
82
int spacing;
264
+
83
} const neon_ls_element_type[11] = {
265
+ if (STE_CFG_S2_ENABLED(config)) {
84
- {4, 4, 1},
266
+ /*
85
- {4, 4, 2},
267
+ * Stage-1 OAS defaults to OAS even if not enabled as it would be used
86
+ {1, 4, 1},
268
+ * in input address check for stage-2.
87
+ {1, 4, 2},
269
+ */
88
{4, 1, 1},
270
+ cfg->oas = oas2bits(SMMU_IDR5_OAS);
89
- {4, 2, 1},
271
+ ret = decode_ste_s2_cfg(cfg, ste);
90
- {3, 3, 1},
272
+ if (ret) {
91
- {3, 3, 2},
273
+ goto bad_ste;
92
+ {2, 2, 2},
93
+ {1, 3, 1},
94
+ {1, 3, 2},
95
{3, 1, 1},
96
{1, 1, 1},
97
- {2, 2, 1},
98
- {2, 2, 2},
99
+ {1, 2, 1},
100
+ {1, 2, 2},
101
{2, 1, 1}
102
};
103
104
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
105
int shift;
106
int n;
107
int vec_size;
108
+ int mmu_idx;
109
+ TCGMemOp endian;
110
TCGv_i32 addr;
111
TCGv_i32 tmp;
112
TCGv_i32 tmp2;
113
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
114
rn = (insn >> 16) & 0xf;
115
rm = insn & 0xf;
116
load = (insn & (1 << 21)) != 0;
117
+ endian = s->be_data;
118
+ mmu_idx = get_mem_index(s);
119
if ((insn & (1 << 23)) == 0) {
120
/* Load store all elements. */
121
op = (insn >> 8) & 0xf;
122
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
123
nregs = neon_ls_element_type[op].nregs;
124
interleave = neon_ls_element_type[op].interleave;
125
spacing = neon_ls_element_type[op].spacing;
126
- if (size == 3 && (interleave | spacing) != 1)
127
+ if (size == 3 && (interleave | spacing) != 1) {
128
return 1;
129
+ }
274
+ }
130
+ tmp64 = tcg_temp_new_i64();
275
+ }
131
addr = tcg_temp_new_i32();
276
132
+ tmp2 = tcg_const_i32(1 << size);
277
if (STE_S1CDMAX(ste) != 0) {
133
load_reg_var(s, addr, rn);
278
qemu_log_mask(LOG_UNIMP,
134
- stride = (1 << size) * interleave;
279
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
135
for (reg = 0; reg < nregs; reg++) {
280
if (cached_entry) {
136
- if (interleave > 2 || (interleave == 2 && nregs == 2)) {
281
if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
137
- load_reg_var(s, addr, rn);
282
status = SMMU_TRANS_ERROR;
138
- tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
283
- if (cfg->record_faults) {
139
- } else if (interleave == 2 && nregs == 4 && reg == 2) {
284
+ /*
140
- load_reg_var(s, addr, rn);
285
+ * We know that the TLB only contains either stage-1 or stage-2 as
141
- tcg_gen_addi_i32(addr, addr, 1 << size);
286
+ * nesting is not supported. So it is sufficient to check the
142
- }
287
+ * translation stage to know the TLB stage for now.
143
- if (size == 3) {
288
+ */
144
- tmp64 = tcg_temp_new_i64();
289
+ event.u.f_walk_eabt.s2 = (cfg->stage == 2);
145
- if (load) {
290
+ if (PTW_RECORD_FAULT(cfg)) {
146
- gen_aa32_ld64(s, tmp64, addr, get_mem_index(s));
291
event.type = SMMU_EVT_F_PERMISSION;
147
- neon_store_reg64(tmp64, rd);
292
event.u.f_permission.addr = addr;
148
- } else {
293
event.u.f_permission.rnw = flag & 0x1;
149
- neon_load_reg64(tmp64, rd);
294
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
150
- gen_aa32_st64(s, tmp64, addr, get_mem_index(s));
295
event.u.f_walk_eabt.addr2 = ptw_info.addr;
151
- }
296
break;
152
- tcg_temp_free_i64(tmp64);
297
case SMMU_PTW_ERR_TRANSLATION:
153
- tcg_gen_addi_i32(addr, addr, stride);
298
- if (cfg->record_faults) {
154
- } else {
299
+ if (PTW_RECORD_FAULT(cfg)) {
155
- for (pass = 0; pass < 2; pass++) {
300
event.type = SMMU_EVT_F_TRANSLATION;
156
- if (size == 2) {
301
event.u.f_translation.addr = addr;
157
- if (load) {
302
event.u.f_translation.rnw = flag & 0x1;
158
- tmp = tcg_temp_new_i32();
159
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
160
- neon_store_reg(rd, pass, tmp);
161
- } else {
162
- tmp = neon_load_reg(rd, pass);
163
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
164
- tcg_temp_free_i32(tmp);
165
- }
166
- tcg_gen_addi_i32(addr, addr, stride);
167
- } else if (size == 1) {
168
- if (load) {
169
- tmp = tcg_temp_new_i32();
170
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
171
- tcg_gen_addi_i32(addr, addr, stride);
172
- tmp2 = tcg_temp_new_i32();
173
- gen_aa32_ld16u(s, tmp2, addr, get_mem_index(s));
174
- tcg_gen_addi_i32(addr, addr, stride);
175
- tcg_gen_shli_i32(tmp2, tmp2, 16);
176
- tcg_gen_or_i32(tmp, tmp, tmp2);
177
- tcg_temp_free_i32(tmp2);
178
- neon_store_reg(rd, pass, tmp);
179
- } else {
180
- tmp = neon_load_reg(rd, pass);
181
- tmp2 = tcg_temp_new_i32();
182
- tcg_gen_shri_i32(tmp2, tmp, 16);
183
- gen_aa32_st16(s, tmp, addr, get_mem_index(s));
184
- tcg_temp_free_i32(tmp);
185
- tcg_gen_addi_i32(addr, addr, stride);
186
- gen_aa32_st16(s, tmp2, addr, get_mem_index(s));
187
- tcg_temp_free_i32(tmp2);
188
- tcg_gen_addi_i32(addr, addr, stride);
189
- }
190
- } else /* size == 0 */ {
191
- if (load) {
192
- tmp2 = NULL;
193
- for (n = 0; n < 4; n++) {
194
- tmp = tcg_temp_new_i32();
195
- gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
196
- tcg_gen_addi_i32(addr, addr, stride);
197
- if (n == 0) {
198
- tmp2 = tmp;
199
- } else {
200
- tcg_gen_shli_i32(tmp, tmp, n * 8);
201
- tcg_gen_or_i32(tmp2, tmp2, tmp);
202
- tcg_temp_free_i32(tmp);
203
- }
204
- }
205
- neon_store_reg(rd, pass, tmp2);
206
- } else {
207
- tmp2 = neon_load_reg(rd, pass);
208
- for (n = 0; n < 4; n++) {
209
- tmp = tcg_temp_new_i32();
210
- if (n == 0) {
211
- tcg_gen_mov_i32(tmp, tmp2);
212
- } else {
213
- tcg_gen_shri_i32(tmp, tmp2, n * 8);
214
- }
215
- gen_aa32_st8(s, tmp, addr, get_mem_index(s));
216
- tcg_temp_free_i32(tmp);
217
- tcg_gen_addi_i32(addr, addr, stride);
218
- }
219
- tcg_temp_free_i32(tmp2);
220
- }
221
+ for (n = 0; n < 8 >> size; n++) {
222
+ int xs;
223
+ for (xs = 0; xs < interleave; xs++) {
224
+ int tt = rd + reg + spacing * xs;
225
+
226
+ if (load) {
227
+ gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
228
+ neon_store_element64(tt, n, size, tmp64);
229
+ } else {
230
+ neon_load_element64(tmp64, tt, n, size);
231
+ gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
232
}
233
+ tcg_gen_add_i32(addr, addr, tmp2);
234
}
235
}
303
}
236
- rd += spacing;
304
break;
237
}
305
case SMMU_PTW_ERR_ADDR_SIZE:
238
tcg_temp_free_i32(addr);
306
- if (cfg->record_faults) {
239
- stride = nregs * 8;
307
+ if (PTW_RECORD_FAULT(cfg)) {
240
+ tcg_temp_free_i32(tmp2);
308
event.type = SMMU_EVT_F_ADDR_SIZE;
241
+ tcg_temp_free_i64(tmp64);
309
event.u.f_addr_size.addr = addr;
242
+ stride = nregs * interleave * 8;
310
event.u.f_addr_size.rnw = flag & 0x1;
243
} else {
311
}
244
size = (insn >> 10) & 3;
312
break;
245
if (size == 3) {
313
case SMMU_PTW_ERR_ACCESS:
314
- if (cfg->record_faults) {
315
+ if (PTW_RECORD_FAULT(cfg)) {
316
event.type = SMMU_EVT_F_ACCESS;
317
event.u.f_access.addr = addr;
318
event.u.f_access.rnw = flag & 0x1;
319
}
320
break;
321
case SMMU_PTW_ERR_PERMISSION:
322
- if (cfg->record_faults) {
323
+ if (PTW_RECORD_FAULT(cfg)) {
324
event.type = SMMU_EVT_F_PERMISSION;
325
event.u.f_permission.addr = addr;
326
event.u.f_permission.rnw = flag & 0x1;
246
--
327
--
247
2.19.1
328
2.34.1
248
249
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/45] target/arm: Promote consecutive memory ops for aa64
[PULL 07/21] hw/arm/smmuv3: Make TLB lookup work for stage-2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
For a sequence of loads or stores from a single register,
3
Right now, either stage-1 or stage-2 are supported, this simplifies
4
little-endian operations can be promoted to an 8-byte op.
4
how we can deal with TLBs.
5
This can reduce the number of operations by a factor of 8.
5
This patch makes TLB lookup work if stage-2 is enabled instead of
6
stage-1.
7
TLB lookup is done before a PTW, if a valid entry is found we won't
8
do the PTW.
9
To be able to do TLB lookup, we need the correct tagging info, as
10
granularity and input size, so we get this based on the supported
11
translation stage. The TLB entries are added correctly from each
12
stage PTW.
6
13
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
When nested translation is supported, this would need to change, for
8
Message-id: 20181011205206.3552-5-richard.henderson@linaro.org
15
example if we go with a combined TLB implementation, we would need to
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
use the min of the granularities in TLB.
17
18
As stage-2 shouldn't be tagged by ASID, it will be set to -1 if S1P
19
is not enabled.
20
21
Signed-off-by: Mostafa Saleh <smostafa@google.com>
22
Reviewed-by: Eric Auger <eric.auger@redhat.com>
23
Tested-by: Eric Auger <eric.auger@redhat.com>
24
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
25
Message-id: 20230516203327.2051088-7-smostafa@google.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
27
---
12
target/arm/translate-a64.c | 66 +++++++++++++++++++++++---------------
28
hw/arm/smmuv3.c | 44 +++++++++++++++++++++++++++++++++-----------
13
1 file changed, 40 insertions(+), 26 deletions(-)
29
1 file changed, 33 insertions(+), 11 deletions(-)
14
30
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
31
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
16
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
33
--- a/hw/arm/smmuv3.c
18
+++ b/target/arm/translate-a64.c
34
+++ b/hw/arm/smmuv3.c
19
@@ -XXX,XX +XXX,XX @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
35
@@ -XXX,XX +XXX,XX @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg,
20
36
STE ste;
21
/* Store from vector register to memory */
37
CD cd;
22
static void do_vec_st(DisasContext *s, int srcidx, int element,
38
23
- TCGv_i64 tcg_addr, int size)
39
+ /* ASID defaults to -1 (if s1 is not supported). */
24
+ TCGv_i64 tcg_addr, int size, TCGMemOp endian)
40
+ cfg->asid = -1;
25
{
41
+
26
- TCGMemOp memop = s->be_data + size;
42
ret = smmu_find_ste(s, sid, &ste, event);
27
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
43
if (ret) {
28
44
return ret;
29
read_vec_element(s, tcg_tmp, srcidx, element, size);
45
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
30
- tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
46
.addr_mask = ~(hwaddr)0,
31
+ tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size);
47
.perm = IOMMU_NONE,
32
48
};
33
tcg_temp_free_i64(tcg_tmp);
49
+ /*
34
}
50
+ * Combined attributes used for TLB lookup, as only one stage is supported,
35
51
+ * it will hold attributes based on the enabled stage.
36
/* Load from memory to vector register */
52
+ */
37
static void do_vec_ld(DisasContext *s, int destidx, int element,
53
+ SMMUTransTableInfo tt_combined;
38
- TCGv_i64 tcg_addr, int size)
54
39
+ TCGv_i64 tcg_addr, int size, TCGMemOp endian)
55
qemu_mutex_lock(&s->mutex);
40
{
56
41
- TCGMemOp memop = s->be_data + size;
57
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
42
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
58
goto epilogue;
43
44
- tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
45
+ tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size);
46
write_vec_element(s, tcg_tmp, destidx, element, size);
47
48
tcg_temp_free_i64(tcg_tmp);
49
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
50
bool is_postidx = extract32(insn, 23, 1);
51
bool is_q = extract32(insn, 30, 1);
52
TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
53
+ TCGMemOp endian = s->be_data;
54
55
- int ebytes = 1 << size;
56
- int elements = (is_q ? 128 : 64) / (8 << size);
57
+ int ebytes; /* bytes per element */
58
+ int elements; /* elements per vector */
59
int rpt; /* num iterations */
60
int selem; /* structure elements */
61
int r;
62
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
63
gen_check_sp_alignment(s);
64
}
59
}
65
60
66
+ /* For our purposes, bytes are always little-endian. */
61
- tt = select_tt(cfg, addr);
67
+ if (size == 0) {
62
- if (!tt) {
68
+ endian = MO_LE;
63
- if (cfg->record_faults) {
64
- event.type = SMMU_EVT_F_TRANSLATION;
65
- event.u.f_translation.addr = addr;
66
- event.u.f_translation.rnw = flag & 0x1;
67
+ if (cfg->stage == 1) {
68
+ /* Select stage1 translation table. */
69
+ tt = select_tt(cfg, addr);
70
+ if (!tt) {
71
+ if (cfg->record_faults) {
72
+ event.type = SMMU_EVT_F_TRANSLATION;
73
+ event.u.f_translation.addr = addr;
74
+ event.u.f_translation.rnw = flag & 0x1;
75
+ }
76
+ status = SMMU_TRANS_ERROR;
77
+ goto epilogue;
78
}
79
- status = SMMU_TRANS_ERROR;
80
- goto epilogue;
81
- }
82
+ tt_combined.granule_sz = tt->granule_sz;
83
+ tt_combined.tsz = tt->tsz;
84
85
- page_mask = (1ULL << (tt->granule_sz)) - 1;
86
+ } else {
87
+ /* Stage2. */
88
+ tt_combined.granule_sz = cfg->s2cfg.granule_sz;
89
+ tt_combined.tsz = cfg->s2cfg.tsz;
69
+ }
90
+ }
70
+
91
+ /*
71
+ /* Consecutive little-endian elements from a single register
92
+ * TLB lookup looks for granule and input size for a translation stage,
72
+ * can be promoted to a larger little-endian operation.
93
+ * as only one stage is supported right now, choose the right values
94
+ * from the configuration.
73
+ */
95
+ */
74
+ if (selem == 1 && endian == MO_LE) {
96
+ page_mask = (1ULL << tt_combined.granule_sz) - 1;
75
+ size = 3;
97
aligned_addr = addr & ~page_mask;
76
+ }
98
77
+ ebytes = 1 << size;
99
- cached_entry = smmu_iotlb_lookup(bs, cfg, tt, aligned_addr);
78
+ elements = (is_q ? 16 : 8) / ebytes;
100
+ cached_entry = smmu_iotlb_lookup(bs, cfg, &tt_combined, aligned_addr);
79
+
101
if (cached_entry) {
80
tcg_rn = cpu_reg_sp(s, rn);
102
if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
81
tcg_addr = tcg_temp_new_i64();
103
status = SMMU_TRANS_ERROR;
82
tcg_gen_mov_i64(tcg_addr, tcg_rn);
83
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
84
for (r = 0; r < rpt; r++) {
85
int e;
86
for (e = 0; e < elements; e++) {
87
- int tt = (rt + r) % 32;
88
int xs;
89
for (xs = 0; xs < selem; xs++) {
90
+ int tt = (rt + r + xs) % 32;
91
if (is_store) {
92
- do_vec_st(s, tt, e, tcg_addr, size);
93
+ do_vec_st(s, tt, e, tcg_addr, size, endian);
94
} else {
95
- do_vec_ld(s, tt, e, tcg_addr, size);
96
-
97
- /* For non-quad operations, setting a slice of the low
98
- * 64 bits of the register clears the high 64 bits (in
99
- * the ARM ARM pseudocode this is implicit in the fact
100
- * that 'rval' is a 64 bit wide variable).
101
- * For quad operations, we might still need to zero the
102
- * high bits of SVE. We optimize by noticing that we only
103
- * need to do this the first time we touch a register.
104
- */
105
- if (e == 0 && (r == 0 || xs == selem - 1)) {
106
- clear_vec_high(s, is_q, tt);
107
- }
108
+ do_vec_ld(s, tt, e, tcg_addr, size, endian);
109
}
110
tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes);
111
- tt = (tt + 1) % 32;
112
}
113
}
114
}
115
116
+ if (!is_store) {
117
+ /* For non-quad operations, setting a slice of the low
118
+ * 64 bits of the register clears the high 64 bits (in
119
+ * the ARM ARM pseudocode this is implicit in the fact
120
+ * that 'rval' is a 64 bit wide variable).
121
+ * For quad operations, we might still need to zero the
122
+ * high bits of SVE.
123
+ */
124
+ for (r = 0; r < rpt * selem; r++) {
125
+ int tt = (rt + r) % 32;
126
+ clear_vec_high(s, is_q, tt);
127
+ }
128
+ }
129
+
130
if (is_postidx) {
131
int rm = extract32(insn, 16, 5);
132
if (rm == 31) {
133
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
134
} else {
135
/* Load/store one element per register */
136
if (is_load) {
137
- do_vec_ld(s, rt, index, tcg_addr, scale);
138
+ do_vec_ld(s, rt, index, tcg_addr, scale, s->be_data);
139
} else {
140
- do_vec_st(s, rt, index, tcg_addr, scale);
141
+ do_vec_st(s, rt, index, tcg_addr, scale, s->be_data);
142
}
143
}
144
tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes);
145
--
104
--
146
2.19.1
105
2.34.1
147
148
diff view generated by jsdifflib
[Qemu-devel] [PULL 42/45] net: cadence_gem: Announce availability of priority queues
[PULL 08/21] hw/arm/smmuv3: Add VMID to TLB tagging
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
Announce the availability of the various priority queues.
3
Allow TLB to be tagged with VMID.
4
This fixes an issue where guest kernels would miss to
4
5
configure secondary queues due to inproper feature bits.
5
If stage-1 is only supported, VMID is set to -1 and ignored from STE
6
6
and CMD_TLBI_NH* cmds.
7
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
8
Message-id: 20181017213932.19973-2-edgar.iglesias@gmail.com
8
Update smmu_iotlb_insert trace event to have vmid.
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
10
Signed-off-by: Mostafa Saleh <smostafa@google.com>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Tested-by: Eric Auger <eric.auger@redhat.com>
13
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
14
Message-id: 20230516203327.2051088-8-smostafa@google.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
16
---
12
hw/net/cadence_gem.c | 8 +++++++-
17
hw/arm/smmu-internal.h | 2 ++
13
1 file changed, 7 insertions(+), 1 deletion(-)
18
include/hw/arm/smmu-common.h | 5 +++--
14
19
hw/arm/smmu-common.c | 36 ++++++++++++++++++++++--------------
15
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
20
hw/arm/smmuv3.c | 12 +++++++++---
16
index XXXXXXX..XXXXXXX 100644
21
hw/arm/trace-events | 6 +++---
17
--- a/hw/net/cadence_gem.c
22
5 files changed, 39 insertions(+), 22 deletions(-)
18
+++ b/hw/net/cadence_gem.c
23
19
@@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d)
24
diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
20
int i;
25
index XXXXXXX..XXXXXXX 100644
21
CadenceGEMState *s = CADENCE_GEM(d);
26
--- a/hw/arm/smmu-internal.h
22
const uint8_t *a;
27
+++ b/hw/arm/smmu-internal.h
23
+ uint32_t queues_mask = 0;
28
@@ -XXX,XX +XXX,XX @@ static inline int pgd_concat_idx(int start_level, int granule_sz,
24
29
}
25
DB_PRINT("\n");
30
26
31
#define SMMU_IOTLB_ASID(key) ((key).asid)
27
@@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d)
32
+#define SMMU_IOTLB_VMID(key) ((key).vmid)
28
s->regs[GEM_DESCONF] = 0x02500111;
33
29
s->regs[GEM_DESCONF2] = 0x2ab13fff;
34
typedef struct SMMUIOTLBPageInvInfo {
30
s->regs[GEM_DESCONF5] = 0x002f2045;
35
int asid;
31
- s->regs[GEM_DESCONF6] = 0x00000200;
36
+ int vmid;
32
+ s->regs[GEM_DESCONF6] = 0x0;
37
uint64_t iova;
38
uint64_t mask;
39
} SMMUIOTLBPageInvInfo;
40
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/include/hw/arm/smmu-common.h
43
+++ b/include/hw/arm/smmu-common.h
44
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUPciBus {
45
typedef struct SMMUIOTLBKey {
46
uint64_t iova;
47
uint16_t asid;
48
+ uint16_t vmid;
49
uint8_t tg;
50
uint8_t level;
51
} SMMUIOTLBKey;
52
@@ -XXX,XX +XXX,XX @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
53
SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
54
SMMUTransTableInfo *tt, hwaddr iova);
55
void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
56
-SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
57
+SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova,
58
uint8_t tg, uint8_t level);
59
void smmu_iotlb_inv_all(SMMUState *s);
60
void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
61
-void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
62
+void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
63
uint8_t tg, uint64_t num_pages, uint8_t ttl);
64
65
/* Unmap the range of all the notifiers registered to any IOMMU mr */
66
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/arm/smmu-common.c
69
+++ b/hw/arm/smmu-common.c
70
@@ -XXX,XX +XXX,XX @@ static guint smmu_iotlb_key_hash(gconstpointer v)
71
72
/* Jenkins hash */
73
a = b = c = JHASH_INITVAL + sizeof(*key);
74
- a += key->asid + key->level + key->tg;
75
+ a += key->asid + key->vmid + key->level + key->tg;
76
b += extract64(key->iova, 0, 32);
77
c += extract64(key->iova, 32, 32);
78
79
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2)
80
SMMUIOTLBKey *k1 = (SMMUIOTLBKey *)v1, *k2 = (SMMUIOTLBKey *)v2;
81
82
return (k1->asid == k2->asid) && (k1->iova == k2->iova) &&
83
- (k1->level == k2->level) && (k1->tg == k2->tg);
84
+ (k1->level == k2->level) && (k1->tg == k2->tg) &&
85
+ (k1->vmid == k2->vmid);
86
}
87
88
-SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
89
+SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova,
90
uint8_t tg, uint8_t level)
91
{
92
- SMMUIOTLBKey key = {.asid = asid, .iova = iova, .tg = tg, .level = level};
93
+ SMMUIOTLBKey key = {.asid = asid, .vmid = vmid, .iova = iova,
94
+ .tg = tg, .level = level};
95
96
return key;
97
}
98
@@ -XXX,XX +XXX,XX @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
99
uint64_t mask = subpage_size - 1;
100
SMMUIOTLBKey key;
101
102
- key = smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level);
103
+ key = smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid,
104
+ iova & ~mask, tg, level);
105
entry = g_hash_table_lookup(bs->iotlb, &key);
106
if (entry) {
107
break;
108
@@ -XXX,XX +XXX,XX @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
109
110
if (entry) {
111
cfg->iotlb_hits++;
112
- trace_smmu_iotlb_lookup_hit(cfg->asid, iova,
113
+ trace_smmu_iotlb_lookup_hit(cfg->asid, cfg->s2cfg.vmid, iova,
114
cfg->iotlb_hits, cfg->iotlb_misses,
115
100 * cfg->iotlb_hits /
116
(cfg->iotlb_hits + cfg->iotlb_misses));
117
} else {
118
cfg->iotlb_misses++;
119
- trace_smmu_iotlb_lookup_miss(cfg->asid, iova,
120
+ trace_smmu_iotlb_lookup_miss(cfg->asid, cfg->s2cfg.vmid, iova,
121
cfg->iotlb_hits, cfg->iotlb_misses,
122
100 * cfg->iotlb_hits /
123
(cfg->iotlb_hits + cfg->iotlb_misses));
124
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new)
125
smmu_iotlb_inv_all(bs);
126
}
127
128
- *key = smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level);
129
- trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level);
130
+ *key = smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, new->entry.iova,
131
+ tg, new->level);
132
+ trace_smmu_iotlb_insert(cfg->asid, cfg->s2cfg.vmid, new->entry.iova,
133
+ tg, new->level);
134
g_hash_table_insert(bs->iotlb, key, new);
135
}
136
137
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
138
139
return SMMU_IOTLB_ASID(*iotlb_key) == asid;
140
}
141
-
142
-static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
143
+static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer value,
144
gpointer user_data)
145
{
146
SMMUTLBEntry *iter = (SMMUTLBEntry *)value;
147
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
148
if (info->asid >= 0 && info->asid != SMMU_IOTLB_ASID(iotlb_key)) {
149
return false;
150
}
151
+ if (info->vmid >= 0 && info->vmid != SMMU_IOTLB_VMID(iotlb_key)) {
152
+ return false;
153
+ }
154
return ((info->iova & ~entry->addr_mask) == entry->iova) ||
155
((entry->iova & ~info->mask) == info->iova);
156
}
157
158
-void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
159
+void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
160
uint8_t tg, uint64_t num_pages, uint8_t ttl)
161
{
162
/* if tg is not set we use 4KB range invalidation */
163
uint8_t granule = tg ? tg * 2 + 10 : 12;
164
165
if (ttl && (num_pages == 1) && (asid >= 0)) {
166
- SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova, tg, ttl);
167
+ SMMUIOTLBKey key = smmu_get_iotlb_key(asid, vmid, iova, tg, ttl);
168
169
if (g_hash_table_remove(s->iotlb, &key)) {
170
return;
171
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
172
173
SMMUIOTLBPageInvInfo info = {
174
.asid = asid, .iova = iova,
175
+ .vmid = vmid,
176
.mask = (num_pages * 1 << granule) - 1};
177
178
g_hash_table_foreach_remove(s->iotlb,
179
- smmu_hash_remove_by_asid_iova,
180
+ smmu_hash_remove_by_asid_vmid_iova,
181
&info);
182
}
183
184
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
185
index XXXXXXX..XXXXXXX 100644
186
--- a/hw/arm/smmuv3.c
187
+++ b/hw/arm/smmuv3.c
188
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
189
{
190
dma_addr_t end, addr = CMD_ADDR(cmd);
191
uint8_t type = CMD_TYPE(cmd);
192
- uint16_t vmid = CMD_VMID(cmd);
193
+ int vmid = -1;
194
uint8_t scale = CMD_SCALE(cmd);
195
uint8_t num = CMD_NUM(cmd);
196
uint8_t ttl = CMD_TTL(cmd);
197
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
198
uint64_t num_pages;
199
uint8_t granule;
200
int asid = -1;
201
+ SMMUv3State *smmuv3 = ARM_SMMUV3(s);
33
+
202
+
34
+ if (s->num_priority_queues > 1) {
203
+ /* Only consider VMID if stage-2 is supported. */
35
+ queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
204
+ if (STAGE2_SUPPORTED(smmuv3)) {
36
+ s->regs[GEM_DESCONF6] |= queues_mask;
205
+ vmid = CMD_VMID(cmd);
37
+ }
206
+ }
38
207
39
/* Set MAC address */
208
if (type == SMMU_CMD_TLBI_NH_VA) {
40
a = &s->conf.macaddr.a[0];
209
asid = CMD_ASID(cmd);
210
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
211
if (!tg) {
212
trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
213
smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1);
214
- smmu_iotlb_inv_iova(s, asid, addr, tg, 1, ttl);
215
+ smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl);
216
return;
217
}
218
219
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
220
num_pages = (mask + 1) >> granule;
221
trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
222
smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
223
- smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl);
224
+ smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl);
225
addr += mask + 1;
226
}
227
}
228
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
229
index XXXXXXX..XXXXXXX 100644
230
--- a/hw/arm/trace-events
231
+++ b/hw/arm/trace-events
232
@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all"
233
smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"
234
smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
235
smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
236
-smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
237
-smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
238
-smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d addr=0x%"PRIx64" tg=%d level=%d"
239
+smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
240
+smmu_iotlb_lookup_miss(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
241
+smmu_iotlb_insert(uint16_t asid, uint16_t vmid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d vmid=%d addr=0x%"PRIx64" tg=%d level=%d"
242
243
# smmuv3.c
244
smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
41
--
245
--
42
2.19.1
246
2.34.1
43
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/45] target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test
[PULL 09/21] hw/arm/smmuv3: Add CMDs related to stage-2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
same as CMD_TLBI_NH_VAA.
5
Message-id: 20181016223115.24100-9-richard.henderson@linaro.org
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID.
7
8
For stage-1 only commands, add a check to throw CERROR_ILL if used
9
when stage-1 is not supported.
10
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Signed-off-by: Mostafa Saleh <smostafa@google.com>
13
Tested-by: Eric Auger <eric.auger@redhat.com>
14
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
15
Message-id: 20230516203327.2051088-9-smostafa@google.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
17
---
9
target/arm/cpu.h | 17 +++++++++++++++-
18
include/hw/arm/smmu-common.h | 1 +
10
linux-user/elfload.c | 6 +-----
19
hw/arm/smmu-common.c | 16 +++++++++++
11
target/arm/cpu64.c | 16 ++++++++-------
20
hw/arm/smmuv3.c | 55 ++++++++++++++++++++++++++++++------
12
target/arm/helper.c | 2 +-
21
hw/arm/trace-events | 4 ++-
13
target/arm/translate-a64.c | 40 +++++++++++++++++++-------------------
22
4 files changed, 67 insertions(+), 9 deletions(-)
14
target/arm/translate.c | 6 +++---
23
15
6 files changed, 50 insertions(+), 37 deletions(-)
24
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
16
25
index XXXXXXX..XXXXXXX 100644
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
26
--- a/include/hw/arm/smmu-common.h
18
index XXXXXXX..XXXXXXX 100644
27
+++ b/include/hw/arm/smmu-common.h
19
--- a/target/arm/cpu.h
28
@@ -XXX,XX +XXX,XX @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova,
20
+++ b/target/arm/cpu.h
29
uint8_t tg, uint8_t level);
21
@@ -XXX,XX +XXX,XX @@ enum arm_features {
30
void smmu_iotlb_inv_all(SMMUState *s);
22
ARM_FEATURE_PMU, /* has PMU support */
31
void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
23
ARM_FEATURE_VBAR, /* has cp15 VBAR */
32
+void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid);
24
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
33
void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
25
- ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
34
uint8_t tg, uint64_t num_pages, uint8_t ttl);
26
ARM_FEATURE_M_MAIN, /* M profile Main Extension */
35
27
};
36
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
28
37
index XXXXXXX..XXXXXXX 100644
29
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
38
--- a/hw/arm/smmu-common.c
30
return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
39
+++ b/hw/arm/smmu-common.c
40
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
41
42
return SMMU_IOTLB_ASID(*iotlb_key) == asid;
31
}
43
}
32
44
+
33
+static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
45
+static gboolean smmu_hash_remove_by_vmid(gpointer key, gpointer value,
46
+ gpointer user_data)
34
+{
47
+{
35
+ /*
48
+ uint16_t vmid = *(uint16_t *)user_data;
36
+ * This is a placeholder for use by VCMA until the rest of
49
+ SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key;
37
+ * the ARMv8.2-FP16 extension is implemented for aa32 mode.
50
+
38
+ * At which point we can properly set and check MVFR1.FPHP.
51
+ return SMMU_IOTLB_VMID(*iotlb_key) == vmid;
39
+ */
40
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
41
+}
52
+}
42
+
53
+
43
/*
54
static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer value,
44
* 64-bit feature tests via id registers.
55
gpointer user_data)
45
*/
56
{
46
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
57
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
47
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
58
g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
48
}
59
}
49
60
50
+static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
61
+inline void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid)
51
+{
62
+{
52
+ /* We always set the AdvSIMD and FP fields identically wrt FP16. */
63
+ trace_smmu_iotlb_inv_vmid(vmid);
53
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
64
+ g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &vmid);
54
+}
65
+}
55
+
66
+
56
static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
67
/* VMSAv8-64 Translation */
68
69
/**
70
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/smmuv3.c
73
+++ b/hw/arm/smmuv3.c
74
@@ -XXX,XX +XXX,XX @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
75
}
76
}
77
78
-static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
79
+static void smmuv3_range_inval(SMMUState *s, Cmd *cmd)
57
{
80
{
58
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
81
dma_addr_t end, addr = CMD_ADDR(cmd);
59
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
82
uint8_t type = CMD_TYPE(cmd);
60
index XXXXXXX..XXXXXXX 100644
83
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
61
--- a/linux-user/elfload.c
62
+++ b/linux-user/elfload.c
63
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
64
hwcaps |= ARM_HWCAP_A64_ASIMD;
65
66
/* probe for the extra features */
67
-#define GET_FEATURE(feat, hwcap) \
68
- do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
69
#define GET_FEATURE_ID(feat, hwcap) \
70
do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
71
72
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
73
GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3);
74
GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3);
75
GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4);
76
- GET_FEATURE(ARM_FEATURE_V8_FP16,
77
- ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
78
+ GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
79
GET_FEATURE_ID(aa64_atomics, ARM_HWCAP_A64_ATOMICS);
80
GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM);
81
GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP);
82
GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
83
GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
84
85
-#undef GET_FEATURE
86
#undef GET_FEATURE_ID
87
88
return hwcaps;
89
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/cpu64.c
92
+++ b/target/arm/cpu64.c
93
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
94
95
t = cpu->isar.id_aa64pfr0;
96
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
97
+ t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
98
+ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
99
cpu->isar.id_aa64pfr0 = t;
100
101
/* Replicate the same data to the 32-bit id registers. */
102
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
103
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
104
cpu->isar.id_isar6 = u;
105
106
-#ifdef CONFIG_USER_ONLY
107
- /* We don't set these in system emulation mode for the moment,
108
- * since we don't correctly set the ID registers to advertise them,
109
- * and in some cases they're only available in AArch64 and not AArch32,
110
- * whereas the architecture requires them to be present in both if
111
- * present in either.
112
+ /*
113
+ * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
114
+ * so do not set MVFR1.FPHP. Strictly speaking this is not legal,
115
+ * but it is also not legal to enable SVE without support for FP16,
116
+ * and enabling SVE in system mode is more useful in the short term.
117
*/
118
- set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
119
+
120
+#ifdef CONFIG_USER_ONLY
121
/* For usermode -cpu max we can use a larger and more efficient DCZ
122
* blocksize since we don't have to follow what the hardware does.
123
*/
124
diff --git a/target/arm/helper.c b/target/arm/helper.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/target/arm/helper.c
127
+++ b/target/arm/helper.c
128
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
129
uint32_t changed;
130
131
/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
132
- if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
133
+ if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) {
134
val &= ~FPCR_FZ16;
135
}
84
}
136
85
137
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
86
if (!tg) {
138
index XXXXXXX..XXXXXXX 100644
87
- trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
139
--- a/target/arm/translate-a64.c
88
+ trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
140
+++ b/target/arm/translate-a64.c
89
smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1);
141
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
90
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl);
142
break;
91
return;
143
case 3:
92
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
144
size = MO_16;
93
uint64_t mask = dma_aligned_pow2_mask(addr, end, 64);
145
- if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
94
146
+ if (dc_isar_feature(aa64_fp16, s)) {
95
num_pages = (mask + 1) >> granule;
96
- trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
97
+ trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
98
smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
99
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl);
100
addr += mask + 1;
101
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
102
{
103
uint16_t asid = CMD_ASID(&cmd);
104
105
+ if (!STAGE1_SUPPORTED(s)) {
106
+ cmd_error = SMMU_CERROR_ILL;
107
+ break;
108
+ }
109
+
110
trace_smmuv3_cmdq_tlbi_nh_asid(asid);
111
smmu_inv_notifiers_all(&s->smmu_state);
112
smmu_iotlb_inv_asid(bs, asid);
147
break;
113
break;
148
}
114
}
149
/* fallthru */
115
case SMMU_CMD_TLBI_NH_ALL:
150
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
116
+ if (!STAGE1_SUPPORTED(s)) {
151
break;
117
+ cmd_error = SMMU_CERROR_ILL;
152
case 3:
118
+ break;
153
size = MO_16;
119
+ }
154
- if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
120
+ QEMU_FALLTHROUGH;
155
+ if (dc_isar_feature(aa64_fp16, s)) {
121
case SMMU_CMD_TLBI_NSNH_ALL:
122
trace_smmuv3_cmdq_tlbi_nh();
123
smmu_inv_notifiers_all(&s->smmu_state);
124
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
125
break;
126
case SMMU_CMD_TLBI_NH_VAA:
127
case SMMU_CMD_TLBI_NH_VA:
128
- smmuv3_s1_range_inval(bs, &cmd);
129
+ if (!STAGE1_SUPPORTED(s)) {
130
+ cmd_error = SMMU_CERROR_ILL;
131
+ break;
132
+ }
133
+ smmuv3_range_inval(bs, &cmd);
134
+ break;
135
+ case SMMU_CMD_TLBI_S12_VMALL:
136
+ {
137
+ uint16_t vmid = CMD_VMID(&cmd);
138
+
139
+ if (!STAGE2_SUPPORTED(s)) {
140
+ cmd_error = SMMU_CERROR_ILL;
141
+ break;
142
+ }
143
+
144
+ trace_smmuv3_cmdq_tlbi_s12_vmid(vmid);
145
+ smmu_inv_notifiers_all(&s->smmu_state);
146
+ smmu_iotlb_inv_vmid(bs, vmid);
147
+ break;
148
+ }
149
+ case SMMU_CMD_TLBI_S2_IPA:
150
+ if (!STAGE2_SUPPORTED(s)) {
151
+ cmd_error = SMMU_CERROR_ILL;
152
+ break;
153
+ }
154
+ /*
155
+ * As currently only either s1 or s2 are supported
156
+ * we can reuse same function for s2.
157
+ */
158
+ smmuv3_range_inval(bs, &cmd);
159
break;
160
case SMMU_CMD_TLBI_EL3_ALL:
161
case SMMU_CMD_TLBI_EL3_VA:
162
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
163
case SMMU_CMD_TLBI_EL2_ASID:
164
case SMMU_CMD_TLBI_EL2_VA:
165
case SMMU_CMD_TLBI_EL2_VAA:
166
- case SMMU_CMD_TLBI_S12_VMALL:
167
- case SMMU_CMD_TLBI_S2_IPA:
168
case SMMU_CMD_ATC_INV:
169
case SMMU_CMD_PRI_RESP:
170
case SMMU_CMD_RESUME:
171
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
172
break;
173
default:
174
cmd_error = SMMU_CERROR_ILL;
175
- qemu_log_mask(LOG_GUEST_ERROR,
176
- "Illegal command type: %d\n", CMD_TYPE(&cmd));
156
break;
177
break;
157
}
178
}
158
/* fallthru */
179
qemu_mutex_unlock(&s->mutex);
159
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
180
if (cmd_error) {
160
break;
181
+ if (cmd_error == SMMU_CERROR_ILL) {
161
case 3:
182
+ qemu_log_mask(LOG_GUEST_ERROR,
162
sz = MO_16;
183
+ "Illegal command type: %d\n", CMD_TYPE(&cmd));
163
- if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
184
+ }
164
+ if (dc_isar_feature(aa64_fp16, s)) {
165
break;
185
break;
166
}
186
}
167
/* fallthru */
187
/*
168
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
188
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
169
handle_fp_1src_double(s, opcode, rd, rn);
189
index XXXXXXX..XXXXXXX 100644
170
break;
190
--- a/hw/arm/trace-events
171
case 3:
191
+++ b/hw/arm/trace-events
172
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
192
@@ -XXX,XX +XXX,XX @@ smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, ui
173
+ if (!dc_isar_feature(aa64_fp16, s)) {
193
smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
174
unallocated_encoding(s);
194
smmu_iotlb_inv_all(void) "IOTLB invalidate all"
175
return;
195
smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"
176
}
196
+smmu_iotlb_inv_vmid(uint16_t vmid) "IOTLB invalidate vmid=%d"
177
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
197
smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
178
handle_fp_2src_double(s, opcode, rd, rn, rm);
198
smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
179
break;
199
smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
180
case 3:
200
@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
181
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
201
smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x"
182
+ if (!dc_isar_feature(aa64_fp16, s)) {
202
smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
183
unallocated_encoding(s);
203
smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
184
return;
204
-smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
185
}
205
+smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
186
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
206
smmuv3_cmdq_tlbi_nh(void) ""
187
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
207
smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
188
break;
208
+smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=%d"
189
case 3:
209
smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
190
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
210
smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
191
+ if (!dc_isar_feature(aa64_fp16, s)) {
211
smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
192
unallocated_encoding(s);
193
return;
194
}
195
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
196
break;
197
case 3:
198
sz = MO_16;
199
- if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
200
+ if (dc_isar_feature(aa64_fp16, s)) {
201
break;
202
}
203
/* fallthru */
204
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
205
case 1: /* float64 */
206
break;
207
case 3: /* float16 */
208
- if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
209
+ if (dc_isar_feature(aa64_fp16, s)) {
210
break;
211
}
212
/* fallthru */
213
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
214
break;
215
case 0x6: /* 16-bit float, 32-bit int */
216
case 0xe: /* 16-bit float, 64-bit int */
217
- if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
218
+ if (dc_isar_feature(aa64_fp16, s)) {
219
break;
220
}
221
/* fallthru */
222
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
223
case 1: /* float64 */
224
break;
225
case 3: /* float16 */
226
- if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
227
+ if (dc_isar_feature(aa64_fp16, s)) {
228
break;
229
}
230
/* fallthru */
231
@@ -XXX,XX +XXX,XX @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
232
*/
233
is_min = extract32(size, 1, 1);
234
is_fp = true;
235
- if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
236
+ if (!is_u && dc_isar_feature(aa64_fp16, s)) {
237
size = 1;
238
} else if (!is_u || !is_q || extract32(size, 0, 1)) {
239
unallocated_encoding(s);
240
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
241
242
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
243
/* Check for FMOV (vector, immediate) - half-precision */
244
- if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode == 0xf)) {
245
+ if (!(dc_isar_feature(aa64_fp16, s) && o2 && cmode == 0xf)) {
246
unallocated_encoding(s);
247
return;
248
}
249
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
250
case 0x2f: /* FMINP */
251
/* FP op, size[0] is 32 or 64 bit*/
252
if (!u) {
253
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
254
+ if (!dc_isar_feature(aa64_fp16, s)) {
255
unallocated_encoding(s);
256
return;
257
} else {
258
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
259
size = MO_32;
260
} else if (immh & 2) {
261
size = MO_16;
262
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
263
+ if (!dc_isar_feature(aa64_fp16, s)) {
264
unallocated_encoding(s);
265
return;
266
}
267
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
268
size = MO_32;
269
} else if (immh & 0x2) {
270
size = MO_16;
271
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
272
+ if (!dc_isar_feature(aa64_fp16, s)) {
273
unallocated_encoding(s);
274
return;
275
}
276
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
277
return;
278
}
279
280
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
281
+ if (!dc_isar_feature(aa64_fp16, s)) {
282
unallocated_encoding(s);
283
}
284
285
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
286
TCGv_ptr fpst;
287
bool pairwise = false;
288
289
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
290
+ if (!dc_isar_feature(aa64_fp16, s)) {
291
unallocated_encoding(s);
292
return;
293
}
294
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
295
case 0x1c: /* FCADD, #90 */
296
case 0x1e: /* FCADD, #270 */
297
if (size == 0
298
- || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
299
+ || (size == 1 && !dc_isar_feature(aa64_fp16, s))
300
|| (size == 3 && !is_q)) {
301
unallocated_encoding(s);
302
return;
303
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
304
bool need_fpst = true;
305
int rmode;
306
307
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
308
+ if (!dc_isar_feature(aa64_fp16, s)) {
309
unallocated_encoding(s);
310
return;
311
}
312
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
313
}
314
break;
315
}
316
- if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
317
+ if (is_fp16 && !dc_isar_feature(aa64_fp16, s)) {
318
unallocated_encoding(s);
319
return;
320
}
321
diff --git a/target/arm/translate.c b/target/arm/translate.c
322
index XXXXXXX..XXXXXXX 100644
323
--- a/target/arm/translate.c
324
+++ b/target/arm/translate.c
325
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
326
int size = extract32(insn, 20, 1);
327
data = extract32(insn, 23, 2); /* rot */
328
if (!dc_isar_feature(aa32_vcma, s)
329
- || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) {
330
+ || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
331
return 1;
332
}
333
fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
334
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
335
int size = extract32(insn, 20, 1);
336
data = extract32(insn, 24, 1); /* rot */
337
if (!dc_isar_feature(aa32_vcma, s)
338
- || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) {
339
+ || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
340
return 1;
341
}
342
fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
343
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
344
return 1;
345
}
346
if (size == 0) {
347
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
348
+ if (!dc_isar_feature(aa32_fp16_arith, s)) {
349
return 1;
350
}
351
/* For fp16, rm is just Vm, and index is M. */
352
--
212
--
353
2.19.1
213
2.34.1
354
355
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/45] target/arm: Convert v8 extensions from feature bits to isar tests
[PULL 10/21] hw/arm/smmuv3: Add stage-2 support in iova notifier
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
Most of the v8 extensions are self-contained within the ISAR
3
In smmuv3_notify_iova, read the granule based on translation stage
4
registers and are not implied by other feature bits, which
4
and use VMID if valid value is sent.
5
makes them the easiest to convert.
6
5
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Signed-off-by: Mostafa Saleh <smostafa@google.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Message-id: 20181016223115.24100-4-richard.henderson@linaro.org
8
Tested-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Message-id: 20230516203327.2051088-10-smostafa@google.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
target/arm/cpu.h | 131 +++++++++++++++++++++++++++++++++----
13
hw/arm/smmuv3.c | 39 ++++++++++++++++++++++++++-------------
14
target/arm/translate.h | 7 ++
14
hw/arm/trace-events | 2 +-
15
linux-user/elfload.c | 46 ++++++++-----
15
2 files changed, 27 insertions(+), 14 deletions(-)
16
target/arm/cpu.c | 27 +++++---
17
target/arm/cpu64.c | 57 +++++++++-------
18
target/arm/translate-a64.c | 101 ++++++++++++++--------------
19
target/arm/translate.c | 36 +++++-----
20
7 files changed, 273 insertions(+), 132 deletions(-)
21
16
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
23
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
19
--- a/hw/arm/smmuv3.c
25
+++ b/target/arm/cpu.h
20
+++ b/hw/arm/smmuv3.c
26
@@ -XXX,XX +XXX,XX @@ typedef enum ARMPSCIState {
21
@@ -XXX,XX +XXX,XX @@ epilogue:
27
PSCI_ON_PENDING = 2
22
* @mr: IOMMU mr region handle
28
} ARMPSCIState;
23
* @n: notifier to be called
29
24
* @asid: address space ID or negative value if we don't care
30
+typedef struct ARMISARegisters ARMISARegisters;
25
+ * @vmid: virtual machine ID or negative value if we don't care
26
* @iova: iova
27
* @tg: translation granule (if communicated through range invalidation)
28
* @num_pages: number of @granule sized pages (if tg != 0), otherwise 1
29
*/
30
static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
31
IOMMUNotifier *n,
32
- int asid, dma_addr_t iova,
33
- uint8_t tg, uint64_t num_pages)
34
+ int asid, int vmid,
35
+ dma_addr_t iova, uint8_t tg,
36
+ uint64_t num_pages)
37
{
38
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
39
IOMMUTLBEvent event;
40
uint8_t granule;
41
+ SMMUv3State *s = sdev->smmu;
42
43
if (!tg) {
44
SMMUEventInfo event = {.inval_ste_allowed = true};
45
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
46
return;
47
}
48
49
- tt = select_tt(cfg, iova);
50
- if (!tt) {
51
+ if (vmid >= 0 && cfg->s2cfg.vmid != vmid) {
52
return;
53
}
54
- granule = tt->granule_sz;
31
+
55
+
32
/**
56
+ if (STAGE1_SUPPORTED(s)) {
33
* ARMCPU:
57
+ tt = select_tt(cfg, iova);
34
* @env: #CPUARMState
58
+ if (!tt) {
35
@@ -XXX,XX +XXX,XX @@ enum arm_features {
59
+ return;
36
ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
60
+ }
37
ARM_FEATURE_V8,
61
+ granule = tt->granule_sz;
38
ARM_FEATURE_AARCH64, /* supports 64 bit mode */
62
+ } else {
39
- ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
63
+ granule = cfg->s2cfg.granule_sz;
40
ARM_FEATURE_CBAR, /* has cp15 CBAR */
64
+ }
41
ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
42
ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
43
ARM_FEATURE_EL2, /* has EL2 Virtualization support */
44
ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
45
- ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */
46
- ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
47
- ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
48
ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
49
ARM_FEATURE_PMU, /* has PMU support */
50
ARM_FEATURE_VBAR, /* has cp15 VBAR */
51
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
52
ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */
53
ARM_FEATURE_SVE, /* has Scalable Vector Extension */
54
- ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensions */
55
- ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */
56
- ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */
57
- ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */
58
- ARM_FEATURE_V8_ATOMICS, /* ARMv8.1-Atomics feature */
59
- ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */
60
- ARM_FEATURE_V8_DOTPROD, /* implements v8.2 simd dot product */
61
ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
62
- ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */
63
ARM_FEATURE_M_MAIN, /* M profile Main Extension */
64
};
65
66
@@ -XXX,XX +XXX,XX @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
67
/* Shared between translate-sve.c and sve_helper.c. */
68
extern const uint64_t pred_esz_masks[4];
69
70
+/*
71
+ * 32-bit feature tests via id registers.
72
+ */
73
+static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
74
+{
75
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
76
+}
77
+
65
+
78
+static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
66
} else {
79
+{
67
granule = tg * 2 + 10;
80
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
68
}
81
+}
69
@@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
82
+
70
memory_region_notify_iommu_one(n, &event);
83
+static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
84
+{
85
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
86
+}
87
+
88
+static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
89
+{
90
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
91
+}
92
+
93
+static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
94
+{
95
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
96
+}
97
+
98
+static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
99
+{
100
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
101
+}
102
+
103
+static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
104
+{
105
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
106
+}
107
+
108
+static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
109
+{
110
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
111
+}
112
+
113
+/*
114
+ * 64-bit feature tests via id registers.
115
+ */
116
+static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
117
+{
118
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
119
+}
120
+
121
+static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
122
+{
123
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
124
+}
125
+
126
+static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
127
+{
128
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
129
+}
130
+
131
+static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
132
+{
133
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
134
+}
135
+
136
+static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
137
+{
138
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
139
+}
140
+
141
+static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
142
+{
143
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
144
+}
145
+
146
+static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
147
+{
148
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
149
+}
150
+
151
+static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
152
+{
153
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
154
+}
155
+
156
+static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
157
+{
158
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
159
+}
160
+
161
+static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
162
+{
163
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
164
+}
165
+
166
+static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
167
+{
168
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
169
+}
170
+
171
+static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
172
+{
173
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
174
+}
175
+
176
+static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
177
+{
178
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
179
+}
180
+
181
+/*
182
+ * Forward to the above feature tests given an ARMCPU pointer.
183
+ */
184
+#define cpu_isar_feature(name, cpu) \
185
+ ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
186
+
187
#endif
188
diff --git a/target/arm/translate.h b/target/arm/translate.h
189
index XXXXXXX..XXXXXXX 100644
190
--- a/target/arm/translate.h
191
+++ b/target/arm/translate.h
192
@@ -XXX,XX +XXX,XX @@
193
/* internal defines */
194
typedef struct DisasContext {
195
DisasContextBase base;
196
+ const ARMISARegisters *isar;
197
198
target_ulong pc;
199
target_ulong page_start;
200
@@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 get_ahp_flag(void)
201
return ret;
202
}
71
}
203
72
204
+/*
73
-/* invalidate an asid/iova range tuple in all mr's */
205
+ * Forward to the isar_feature_* tests given a DisasContext pointer.
74
-static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
206
+ */
75
- uint8_t tg, uint64_t num_pages)
207
+#define dc_isar_feature(name, ctx) \
76
+/* invalidate an asid/vmid/iova range tuple in all mr's */
208
+ ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
77
+static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, int vmid,
209
+
78
+ dma_addr_t iova, uint8_t tg,
210
#endif /* TARGET_ARM_TRANSLATE_H */
79
+ uint64_t num_pages)
211
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
80
{
212
index XXXXXXX..XXXXXXX 100644
81
SMMUDevice *sdev;
213
--- a/linux-user/elfload.c
82
214
+++ b/linux-user/elfload.c
83
@@ -XXX,XX +XXX,XX @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
215
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
84
IOMMUMemoryRegion *mr = &sdev->iommu;
216
/* probe for the extra features */
85
IOMMUNotifier *n;
217
#define GET_FEATURE(feat, hwcap) \
86
218
do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
87
- trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova,
219
+
88
- tg, num_pages);
220
+#define GET_FEATURE_ID(feat, hwcap) \
89
+ trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, vmid,
221
+ do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
90
+ iova, tg, num_pages);
222
+
91
223
/* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */
92
IOMMU_NOTIFIER_FOREACH(n, mr) {
224
GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
93
- smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages);
225
GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP);
94
+ smmuv3_notify_iova(mr, n, asid, vmid, iova, tg, num_pages);
226
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap2(void)
95
}
227
ARMCPU *cpu = ARM_CPU(thread_cpu);
228
uint32_t hwcaps = 0;
229
230
- GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP2_ARM_AES);
231
- GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP2_ARM_PMULL);
232
- GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP2_ARM_SHA1);
233
- GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP2_ARM_SHA2);
234
- GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP2_ARM_CRC32);
235
+ GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES);
236
+ GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL);
237
+ GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1);
238
+ GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2);
239
+ GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32);
240
return hwcaps;
241
}
242
243
#undef GET_FEATURE
244
+#undef GET_FEATURE_ID
245
246
#else
247
/* 64 bit ARM definitions */
248
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
249
/* probe for the extra features */
250
#define GET_FEATURE(feat, hwcap) \
251
do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
252
- GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP_A64_AES);
253
- GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP_A64_PMULL);
254
- GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1);
255
- GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2);
256
- GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32);
257
- GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3);
258
- GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3);
259
- GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4);
260
- GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512);
261
+#define GET_FEATURE_ID(feat, hwcap) \
262
+ do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
263
+
264
+ GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES);
265
+ GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL);
266
+ GET_FEATURE_ID(aa64_sha1, ARM_HWCAP_A64_SHA1);
267
+ GET_FEATURE_ID(aa64_sha256, ARM_HWCAP_A64_SHA2);
268
+ GET_FEATURE_ID(aa64_sha512, ARM_HWCAP_A64_SHA512);
269
+ GET_FEATURE_ID(aa64_crc32, ARM_HWCAP_A64_CRC32);
270
+ GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3);
271
+ GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3);
272
+ GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4);
273
GET_FEATURE(ARM_FEATURE_V8_FP16,
274
ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP);
275
- GET_FEATURE(ARM_FEATURE_V8_ATOMICS, ARM_HWCAP_A64_ATOMICS);
276
- GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM);
277
- GET_FEATURE(ARM_FEATURE_V8_DOTPROD, ARM_HWCAP_A64_ASIMDDP);
278
- GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA);
279
+ GET_FEATURE_ID(aa64_atomics, ARM_HWCAP_A64_ATOMICS);
280
+ GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM);
281
+ GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP);
282
+ GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
283
GET_FEATURE(ARM_FEATURE_SVE, ARM_HWCAP_A64_SVE);
284
+
285
#undef GET_FEATURE
286
+#undef GET_FEATURE_ID
287
288
return hwcaps;
289
}
290
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
291
index XXXXXXX..XXXXXXX 100644
292
--- a/target/arm/cpu.c
293
+++ b/target/arm/cpu.c
294
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
295
cortex_a15_initfn(obj);
296
#ifdef CONFIG_USER_ONLY
297
/* We don't set these in system emulation mode for the moment,
298
- * since we don't correctly set the ID registers to advertise them,
299
+ * since we don't correctly set (all of) the ID registers to
300
+ * advertise them.
301
*/
302
set_feature(&cpu->env, ARM_FEATURE_V8);
303
- set_feature(&cpu->env, ARM_FEATURE_V8_AES);
304
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
305
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
306
- set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
307
- set_feature(&cpu->env, ARM_FEATURE_CRC);
308
- set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
309
- set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD);
310
- set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
311
+ {
312
+ uint32_t t;
313
+
314
+ t = cpu->isar.id_isar5;
315
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
316
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
317
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
318
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
319
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
320
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
321
+ cpu->isar.id_isar5 = t;
322
+
323
+ t = cpu->isar.id_isar6;
324
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
325
+ cpu->isar.id_isar6 = t;
326
+ }
327
#endif
328
}
96
}
329
}
97
}
330
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
98
@@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd)
331
index XXXXXXX..XXXXXXX 100644
99
332
--- a/target/arm/cpu64.c
100
if (!tg) {
333
+++ b/target/arm/cpu64.c
101
trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
334
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
102
- smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1);
335
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
103
+ smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1);
336
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
104
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl);
337
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
338
- set_feature(&cpu->env, ARM_FEATURE_V8_AES);
339
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
340
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
341
- set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
342
- set_feature(&cpu->env, ARM_FEATURE_CRC);
343
set_feature(&cpu->env, ARM_FEATURE_EL2);
344
set_feature(&cpu->env, ARM_FEATURE_EL3);
345
set_feature(&cpu->env, ARM_FEATURE_PMU);
346
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
347
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
348
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
349
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
350
- set_feature(&cpu->env, ARM_FEATURE_V8_AES);
351
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
352
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
353
- set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
354
- set_feature(&cpu->env, ARM_FEATURE_CRC);
355
set_feature(&cpu->env, ARM_FEATURE_EL2);
356
set_feature(&cpu->env, ARM_FEATURE_EL3);
357
set_feature(&cpu->env, ARM_FEATURE_PMU);
358
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
359
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
360
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
361
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
362
- set_feature(&cpu->env, ARM_FEATURE_V8_AES);
363
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
364
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
365
- set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
366
- set_feature(&cpu->env, ARM_FEATURE_CRC);
367
set_feature(&cpu->env, ARM_FEATURE_EL2);
368
set_feature(&cpu->env, ARM_FEATURE_EL3);
369
set_feature(&cpu->env, ARM_FEATURE_PMU);
370
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
371
if (kvm_enabled()) {
372
kvm_arm_set_cpu_features_from_host(cpu);
373
} else {
374
+ uint64_t t;
375
+ uint32_t u;
376
aarch64_a57_initfn(obj);
377
+
378
+ t = cpu->isar.id_aa64isar0;
379
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
380
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
381
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
382
+ t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
383
+ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
384
+ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
385
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
386
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
387
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
388
+ t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
389
+ cpu->isar.id_aa64isar0 = t;
390
+
391
+ t = cpu->isar.id_aa64isar1;
392
+ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
393
+ cpu->isar.id_aa64isar1 = t;
394
+
395
+ /* Replicate the same data to the 32-bit id registers. */
396
+ u = cpu->isar.id_isar5;
397
+ u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
398
+ u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
399
+ u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
400
+ u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
401
+ u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
402
+ u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
403
+ cpu->isar.id_isar5 = u;
404
+
405
+ u = cpu->isar.id_isar6;
406
+ u = FIELD_DP32(u, ID_ISAR6, DP, 1);
407
+ cpu->isar.id_isar6 = u;
408
+
409
#ifdef CONFIG_USER_ONLY
410
/* We don't set these in system emulation mode for the moment,
411
* since we don't correctly set the ID registers to advertise them,
412
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
413
* whereas the architecture requires them to be present in both if
414
* present in either.
415
*/
416
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
417
- set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
418
- set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
419
- set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
420
- set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS);
421
- set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
422
- set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD);
423
set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
424
- set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
425
set_feature(&cpu->env, ARM_FEATURE_SVE);
426
/* For usermode -cpu max we can use a larger and more efficient DCZ
427
* blocksize since we don't have to follow what the hardware does.
428
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
429
index XXXXXXX..XXXXXXX 100644
430
--- a/target/arm/translate-a64.c
431
+++ b/target/arm/translate-a64.c
432
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
433
}
434
if (rt2 == 31
435
&& ((rt | rs) & 1) == 0
436
- && arm_dc_feature(s, ARM_FEATURE_V8_ATOMICS)) {
437
+ && dc_isar_feature(aa64_atomics, s)) {
438
/* CASP / CASPL */
439
gen_compare_and_swap_pair(s, rs, rt, rn, size | 2);
440
return;
441
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
442
}
443
if (rt2 == 31
444
&& ((rt | rs) & 1) == 0
445
- && arm_dc_feature(s, ARM_FEATURE_V8_ATOMICS)) {
446
+ && dc_isar_feature(aa64_atomics, s)) {
447
/* CASPA / CASPAL */
448
gen_compare_and_swap_pair(s, rs, rt, rn, size | 2);
449
return;
450
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
451
case 0xb: /* CASL */
452
case 0xe: /* CASA */
453
case 0xf: /* CASAL */
454
- if (rt2 == 31 && arm_dc_feature(s, ARM_FEATURE_V8_ATOMICS)) {
455
+ if (rt2 == 31 && dc_isar_feature(aa64_atomics, s)) {
456
gen_compare_and_swap(s, rs, rt, rn, size);
457
return;
458
}
459
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
460
int rs = extract32(insn, 16, 5);
461
int rn = extract32(insn, 5, 5);
462
int o3_opc = extract32(insn, 12, 4);
463
- int feature = ARM_FEATURE_V8_ATOMICS;
464
TCGv_i64 tcg_rn, tcg_rs;
465
AtomicThreeOpFn *fn;
466
467
- if (is_vector) {
468
+ if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
469
unallocated_encoding(s);
470
return;
105
return;
471
}
106
}
472
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
107
@@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd)
473
unallocated_encoding(s);
108
474
return;
109
num_pages = (mask + 1) >> granule;
110
trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
111
- smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
112
+ smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, num_pages);
113
smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl);
114
addr += mask + 1;
475
}
115
}
476
- if (!arm_dc_feature(s, feature)) {
116
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
477
- unallocated_encoding(s);
478
- return;
479
- }
480
481
if (rn == 31) {
482
gen_check_sp_alignment(s);
483
@@ -XXX,XX +XXX,XX @@ static void handle_crc32(DisasContext *s,
484
TCGv_i64 tcg_acc, tcg_val;
485
TCGv_i32 tcg_bytes;
486
487
- if (!arm_dc_feature(s, ARM_FEATURE_CRC)
488
+ if (!dc_isar_feature(aa64_crc32, s)
489
|| (sf == 1 && sz != 3)
490
|| (sf == 0 && sz == 3)) {
491
unallocated_encoding(s);
492
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_extra(DisasContext *s,
493
bool u = extract32(insn, 29, 1);
494
TCGv_i32 ele1, ele2, ele3;
495
TCGv_i64 res;
496
- int feature;
497
+ bool feature;
498
499
switch (u * 16 + opcode) {
500
case 0x10: /* SQRDMLAH (vector) */
501
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_extra(DisasContext *s,
502
unallocated_encoding(s);
503
return;
504
}
505
- feature = ARM_FEATURE_V8_RDM;
506
+ feature = dc_isar_feature(aa64_rdm, s);
507
break;
508
default:
509
unallocated_encoding(s);
510
return;
511
}
512
- if (!arm_dc_feature(s, feature)) {
513
+ if (!feature) {
514
unallocated_encoding(s);
515
return;
516
}
517
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
518
return;
519
}
520
if (size == 3) {
521
- if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) {
522
+ if (!dc_isar_feature(aa64_pmull, s)) {
523
unallocated_encoding(s);
524
return;
525
}
526
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
527
int size = extract32(insn, 22, 2);
528
bool u = extract32(insn, 29, 1);
529
bool is_q = extract32(insn, 30, 1);
530
- int feature, rot;
531
+ bool feature;
532
+ int rot;
533
534
switch (u * 16 + opcode) {
535
case 0x10: /* SQRDMLAH (vector) */
536
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
537
unallocated_encoding(s);
538
return;
539
}
540
- feature = ARM_FEATURE_V8_RDM;
541
+ feature = dc_isar_feature(aa64_rdm, s);
542
break;
543
case 0x02: /* SDOT (vector) */
544
case 0x12: /* UDOT (vector) */
545
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
546
unallocated_encoding(s);
547
return;
548
}
549
- feature = ARM_FEATURE_V8_DOTPROD;
550
+ feature = dc_isar_feature(aa64_dp, s);
551
break;
552
case 0x18: /* FCMLA, #0 */
553
case 0x19: /* FCMLA, #90 */
554
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
555
unallocated_encoding(s);
556
return;
557
}
558
- feature = ARM_FEATURE_V8_FCMA;
559
+ feature = dc_isar_feature(aa64_fcma, s);
560
break;
561
default:
562
unallocated_encoding(s);
563
return;
564
}
565
- if (!arm_dc_feature(s, feature)) {
566
+ if (!feature) {
567
unallocated_encoding(s);
568
return;
569
}
570
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
571
break;
572
case 0x1d: /* SQRDMLAH */
573
case 0x1f: /* SQRDMLSH */
574
- if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
575
+ if (!dc_isar_feature(aa64_rdm, s)) {
576
unallocated_encoding(s);
577
return;
578
}
579
break;
580
case 0x0e: /* SDOT */
581
case 0x1e: /* UDOT */
582
- if (size != MO_32 || !arm_dc_feature(s, ARM_FEATURE_V8_DOTPROD)) {
583
+ if (size != MO_32 || !dc_isar_feature(aa64_dp, s)) {
584
unallocated_encoding(s);
585
return;
586
}
587
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
588
case 0x13: /* FCMLA #90 */
589
case 0x15: /* FCMLA #180 */
590
case 0x17: /* FCMLA #270 */
591
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) {
592
+ if (!dc_isar_feature(aa64_fcma, s)) {
593
unallocated_encoding(s);
594
return;
595
}
596
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn)
597
TCGv_i32 tcg_decrypt;
598
CryptoThreeOpIntFn *genfn;
599
600
- if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)
601
- || size != 0) {
602
+ if (!dc_isar_feature(aa64_aes, s) || size != 0) {
603
unallocated_encoding(s);
604
return;
605
}
606
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
607
int rd = extract32(insn, 0, 5);
608
CryptoThreeOpFn *genfn;
609
TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
610
- int feature = ARM_FEATURE_V8_SHA256;
611
+ bool feature;
612
613
if (size != 0) {
614
unallocated_encoding(s);
615
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
616
case 2: /* SHA1M */
617
case 3: /* SHA1SU0 */
618
genfn = NULL;
619
- feature = ARM_FEATURE_V8_SHA1;
620
+ feature = dc_isar_feature(aa64_sha1, s);
621
break;
622
case 4: /* SHA256H */
623
genfn = gen_helper_crypto_sha256h;
624
+ feature = dc_isar_feature(aa64_sha256, s);
625
break;
626
case 5: /* SHA256H2 */
627
genfn = gen_helper_crypto_sha256h2;
628
+ feature = dc_isar_feature(aa64_sha256, s);
629
break;
630
case 6: /* SHA256SU1 */
631
genfn = gen_helper_crypto_sha256su1;
632
+ feature = dc_isar_feature(aa64_sha256, s);
633
break;
634
default:
635
unallocated_encoding(s);
636
return;
637
}
638
639
- if (!arm_dc_feature(s, feature)) {
640
+ if (!feature) {
641
unallocated_encoding(s);
642
return;
643
}
644
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
645
int rn = extract32(insn, 5, 5);
646
int rd = extract32(insn, 0, 5);
647
CryptoTwoOpFn *genfn;
648
- int feature;
649
+ bool feature;
650
TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
651
652
if (size != 0) {
653
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
654
655
switch (opcode) {
656
case 0: /* SHA1H */
657
- feature = ARM_FEATURE_V8_SHA1;
658
+ feature = dc_isar_feature(aa64_sha1, s);
659
genfn = gen_helper_crypto_sha1h;
660
break;
661
case 1: /* SHA1SU1 */
662
- feature = ARM_FEATURE_V8_SHA1;
663
+ feature = dc_isar_feature(aa64_sha1, s);
664
genfn = gen_helper_crypto_sha1su1;
665
break;
666
case 2: /* SHA256SU0 */
667
- feature = ARM_FEATURE_V8_SHA256;
668
+ feature = dc_isar_feature(aa64_sha256, s);
669
genfn = gen_helper_crypto_sha256su0;
670
break;
671
default:
672
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
673
return;
674
}
675
676
- if (!arm_dc_feature(s, feature)) {
677
+ if (!feature) {
678
unallocated_encoding(s);
679
return;
680
}
681
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
682
int rm = extract32(insn, 16, 5);
683
int rn = extract32(insn, 5, 5);
684
int rd = extract32(insn, 0, 5);
685
- int feature;
686
+ bool feature;
687
CryptoThreeOpFn *genfn;
688
689
if (o == 0) {
690
switch (opcode) {
691
case 0: /* SHA512H */
692
- feature = ARM_FEATURE_V8_SHA512;
693
+ feature = dc_isar_feature(aa64_sha512, s);
694
genfn = gen_helper_crypto_sha512h;
695
break;
696
case 1: /* SHA512H2 */
697
- feature = ARM_FEATURE_V8_SHA512;
698
+ feature = dc_isar_feature(aa64_sha512, s);
699
genfn = gen_helper_crypto_sha512h2;
700
break;
701
case 2: /* SHA512SU1 */
702
- feature = ARM_FEATURE_V8_SHA512;
703
+ feature = dc_isar_feature(aa64_sha512, s);
704
genfn = gen_helper_crypto_sha512su1;
705
break;
706
case 3: /* RAX1 */
707
- feature = ARM_FEATURE_V8_SHA3;
708
+ feature = dc_isar_feature(aa64_sha3, s);
709
genfn = NULL;
710
break;
711
}
712
} else {
713
switch (opcode) {
714
case 0: /* SM3PARTW1 */
715
- feature = ARM_FEATURE_V8_SM3;
716
+ feature = dc_isar_feature(aa64_sm3, s);
717
genfn = gen_helper_crypto_sm3partw1;
718
break;
719
case 1: /* SM3PARTW2 */
720
- feature = ARM_FEATURE_V8_SM3;
721
+ feature = dc_isar_feature(aa64_sm3, s);
722
genfn = gen_helper_crypto_sm3partw2;
723
break;
724
case 2: /* SM4EKEY */
725
- feature = ARM_FEATURE_V8_SM4;
726
+ feature = dc_isar_feature(aa64_sm4, s);
727
genfn = gen_helper_crypto_sm4ekey;
728
break;
729
default:
730
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
731
}
732
}
733
734
- if (!arm_dc_feature(s, feature)) {
735
+ if (!feature) {
736
unallocated_encoding(s);
737
return;
738
}
739
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
740
int rn = extract32(insn, 5, 5);
741
int rd = extract32(insn, 0, 5);
742
TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
743
- int feature;
744
+ bool feature;
745
CryptoTwoOpFn *genfn;
746
747
switch (opcode) {
748
case 0: /* SHA512SU0 */
749
- feature = ARM_FEATURE_V8_SHA512;
750
+ feature = dc_isar_feature(aa64_sha512, s);
751
genfn = gen_helper_crypto_sha512su0;
752
break;
753
case 1: /* SM4E */
754
- feature = ARM_FEATURE_V8_SM4;
755
+ feature = dc_isar_feature(aa64_sm4, s);
756
genfn = gen_helper_crypto_sm4e;
757
break;
758
default:
759
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
760
return;
761
}
762
763
- if (!arm_dc_feature(s, feature)) {
764
+ if (!feature) {
765
unallocated_encoding(s);
766
return;
767
}
768
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
769
int ra = extract32(insn, 10, 5);
770
int rn = extract32(insn, 5, 5);
771
int rd = extract32(insn, 0, 5);
772
- int feature;
773
+ bool feature;
774
775
switch (op0) {
776
case 0: /* EOR3 */
777
case 1: /* BCAX */
778
- feature = ARM_FEATURE_V8_SHA3;
779
+ feature = dc_isar_feature(aa64_sha3, s);
780
break;
781
case 2: /* SM3SS1 */
782
- feature = ARM_FEATURE_V8_SM3;
783
+ feature = dc_isar_feature(aa64_sm3, s);
784
break;
785
default:
786
unallocated_encoding(s);
787
return;
788
}
789
790
- if (!arm_dc_feature(s, feature)) {
791
+ if (!feature) {
792
unallocated_encoding(s);
793
return;
794
}
795
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_xar(DisasContext *s, uint32_t insn)
796
TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
797
int pass;
798
799
- if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA3)) {
800
+ if (!dc_isar_feature(aa64_sha3, s)) {
801
unallocated_encoding(s);
802
return;
803
}
804
@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
805
TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
806
TCGv_i32 tcg_imm2, tcg_opcode;
807
808
- if (!arm_dc_feature(s, ARM_FEATURE_V8_SM3)) {
809
+ if (!dc_isar_feature(aa64_sm3, s)) {
810
unallocated_encoding(s);
811
return;
812
}
813
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
814
ARMCPU *arm_cpu = arm_env_get_cpu(env);
815
int bound;
816
817
+ dc->isar = &arm_cpu->isar;
818
dc->pc = dc->base.pc_first;
819
dc->condjmp = 0;
820
821
diff --git a/target/arm/translate.c b/target/arm/translate.c
822
index XXXXXXX..XXXXXXX 100644
117
index XXXXXXX..XXXXXXX 100644
823
--- a/target/arm/translate.c
118
--- a/hw/arm/trace-events
824
+++ b/target/arm/translate.c
119
+++ b/hw/arm/trace-events
825
@@ -XXX,XX +XXX,XX @@ static const uint8_t neon_2rm_sizes[] = {
120
@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=%d"
826
static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
121
smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
827
int q, int rd, int rn, int rm)
122
smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
828
{
123
smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
829
- if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
124
-smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64
830
+ if (dc_isar_feature(aa32_rdm, s)) {
125
+smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint16_t vmid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64
831
int opr_sz = (1 + q) * 8;
832
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
833
vfp_reg_offset(1, rn),
834
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
835
return 1;
836
}
837
if (!u) { /* SHA-1 */
838
- if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) {
839
+ if (!dc_isar_feature(aa32_sha1, s)) {
840
return 1;
841
}
842
ptr1 = vfp_reg_ptr(true, rd);
843
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
844
gen_helper_crypto_sha1_3reg(ptr1, ptr2, ptr3, tmp4);
845
tcg_temp_free_i32(tmp4);
846
} else { /* SHA-256 */
847
- if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256) || size == 3) {
848
+ if (!dc_isar_feature(aa32_sha2, s) || size == 3) {
849
return 1;
850
}
851
ptr1 = vfp_reg_ptr(true, rd);
852
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
853
if (op == 14 && size == 2) {
854
TCGv_i64 tcg_rn, tcg_rm, tcg_rd;
855
856
- if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) {
857
+ if (!dc_isar_feature(aa32_pmull, s)) {
858
return 1;
859
}
860
tcg_rn = tcg_temp_new_i64();
861
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
862
{
863
NeonGenThreeOpEnvFn *fn;
864
865
- if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
866
+ if (!dc_isar_feature(aa32_rdm, s)) {
867
return 1;
868
}
869
if (u && ((rd | rn) & 1)) {
870
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
871
break;
872
}
873
case NEON_2RM_AESE: case NEON_2RM_AESMC:
874
- if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)
875
- || ((rm | rd) & 1)) {
876
+ if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) {
877
return 1;
878
}
879
ptr1 = vfp_reg_ptr(true, rd);
880
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
881
tcg_temp_free_i32(tmp3);
882
break;
883
case NEON_2RM_SHA1H:
884
- if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)
885
- || ((rm | rd) & 1)) {
886
+ if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) {
887
return 1;
888
}
889
ptr1 = vfp_reg_ptr(true, rd);
890
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
891
}
892
/* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
893
if (q) {
894
- if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256)) {
895
+ if (!dc_isar_feature(aa32_sha2, s)) {
896
return 1;
897
}
898
- } else if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) {
899
+ } else if (!dc_isar_feature(aa32_sha1, s)) {
900
return 1;
901
}
902
ptr1 = vfp_reg_ptr(true, rd);
903
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
904
/* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
905
int size = extract32(insn, 20, 1);
906
data = extract32(insn, 23, 2); /* rot */
907
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)
908
+ if (!dc_isar_feature(aa32_vcma, s)
909
|| (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) {
910
return 1;
911
}
912
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
913
/* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
914
int size = extract32(insn, 20, 1);
915
data = extract32(insn, 24, 1); /* rot */
916
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)
917
+ if (!dc_isar_feature(aa32_vcma, s)
918
|| (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) {
919
return 1;
920
}
921
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
922
} else if ((insn & 0xfeb00f00) == 0xfc200d00) {
923
/* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
924
bool u = extract32(insn, 4, 1);
925
- if (!arm_dc_feature(s, ARM_FEATURE_V8_DOTPROD)) {
926
+ if (!dc_isar_feature(aa32_dp, s)) {
927
return 1;
928
}
929
fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
930
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
931
int size = extract32(insn, 23, 1);
932
int index;
933
934
- if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) {
935
+ if (!dc_isar_feature(aa32_vcma, s)) {
936
return 1;
937
}
938
if (size == 0) {
939
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
940
} else if ((insn & 0xffb00f00) == 0xfe200d00) {
941
/* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
942
int u = extract32(insn, 4, 1);
943
- if (!arm_dc_feature(s, ARM_FEATURE_V8_DOTPROD)) {
944
+ if (!dc_isar_feature(aa32_dp, s)) {
945
return 1;
946
}
947
fn_gvec = u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
948
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
949
* op1 == 3 is UNPREDICTABLE but handle as UNDEFINED.
950
* Bits 8, 10 and 11 should be zero.
951
*/
952
- if (!arm_dc_feature(s, ARM_FEATURE_CRC) || op1 == 0x3 ||
953
- (c & 0xd) != 0) {
954
+ if (!dc_isar_feature(aa32_crc32, s) || op1 == 0x3 || (c & 0xd) != 0) {
955
goto illegal_op;
956
}
957
958
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
959
case 0x28:
960
case 0x29:
961
case 0x2a:
962
- if (!arm_dc_feature(s, ARM_FEATURE_CRC)) {
963
+ if (!dc_isar_feature(aa32_crc32, s)) {
964
goto illegal_op;
965
}
966
break;
967
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
968
CPUARMState *env = cs->env_ptr;
969
ARMCPU *cpu = arm_env_get_cpu(env);
970
971
+ dc->isar = &cpu->isar;
972
dc->pc = dc->base.pc_first;
973
dc->condjmp = 0;
974
126
975
--
127
--
976
2.19.1
128
2.34.1
977
978
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/45] target/arm: Add support for VCPU event states
[PULL 11/21] hw/arm/smmuv3: Add knob to choose translation stage and enable stage-2
1
From: Dongjiu Geng <gengdongjiu@huawei.com>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
This patch extends the qemu-kvm state sync logic with support for
3
As everything is in place, we can use a new system property to
4
KVM_GET/SET_VCPU_EVENTS, giving access to yet missing SError exception.
4
advertise which stage is supported and remove bad_ste from STE
5
And also it can support the exception state migration.
5
stage2 config.
6
6
7
The SError exception states include SError pending state and ESR value,
7
The property added arm-smmuv3.stage can have 3 values:
8
the kvm_put/get_vcpu_events() will be called when set or get system
8
- "1": Stage-1 only is advertised.
9
registers. When do migration, if source machine has SError pending,
9
- "2": Stage-2 only is advertised.
10
QEMU will do this migration regardless whether the target machine supports
11
to specify guest ESR value, because if target machine does not support that,
12
it can also inject the SError with zero ESR value.
13
10
14
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
11
If not passed or an unsupported value is passed, it will default to
15
Reviewed-by: Andrew Jones <drjones@redhat.com>
12
stage-1.
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
17
Message-id: 1538067351-23931-3-git-send-email-gengdongjiu@huawei.com
14
Advertise VMID16.
15
16
Don't try to decode CD, if stage-2 is configured.
17
18
Reviewed-by: Eric Auger <eric.auger@redhat.com>
19
Signed-off-by: Mostafa Saleh <smostafa@google.com>
20
Tested-by: Eric Auger <eric.auger@redhat.com>
21
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
22
Message-id: 20230516203327.2051088-11-smostafa@google.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
24
---
20
target/arm/cpu.h | 7 ++++++
25
include/hw/arm/smmuv3.h | 1 +
21
target/arm/kvm_arm.h | 24 ++++++++++++++++++
26
hw/arm/smmuv3.c | 32 ++++++++++++++++++++++----------
22
target/arm/kvm.c | 60 ++++++++++++++++++++++++++++++++++++++++++++
27
2 files changed, 23 insertions(+), 10 deletions(-)
23
target/arm/kvm32.c | 13 ++++++++++
24
target/arm/kvm64.c | 13 ++++++++++
25
target/arm/machine.c | 22 ++++++++++++++++
26
6 files changed, 139 insertions(+)
27
28
28
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
29
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
29
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/cpu.h
31
--- a/include/hw/arm/smmuv3.h
31
+++ b/target/arm/cpu.h
32
+++ b/include/hw/arm/smmuv3.h
32
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
33
@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
33
*/
34
34
} exception;
35
qemu_irq irq[4];
35
36
QemuMutex mutex;
36
+ /* Information associated with an SError */
37
+ char *stage;
37
+ struct {
38
};
38
+ uint8_t pending;
39
39
+ uint8_t has_esr;
40
typedef enum {
40
+ uint64_t esr;
41
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
41
+ } serror;
42
+
43
/* Thumb-2 EE state. */
44
uint32_t teecr;
45
uint32_t teehbr;
46
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
47
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/kvm_arm.h
43
--- a/hw/arm/smmuv3.c
49
+++ b/target/arm/kvm_arm.h
44
+++ b/hw/arm/smmuv3.c
50
@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu);
45
@@ -XXX,XX +XXX,XX @@
51
*/
46
#include "hw/irq.h"
52
void kvm_arm_reset_vcpu(ARMCPU *cpu);
47
#include "hw/sysbus.h"
53
48
#include "migration/vmstate.h"
54
+/**
49
+#include "hw/qdev-properties.h"
55
+ * kvm_arm_init_serror_injection:
50
#include "hw/qdev-core.h"
56
+ * @cs: CPUState
51
#include "hw/pci/pci.h"
57
+ *
52
#include "cpu.h"
58
+ * Check whether KVM can set guest SError syndrome.
53
@@ -XXX,XX +XXX,XX @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *info)
59
+ */
54
60
+void kvm_arm_init_serror_injection(CPUState *cs);
55
static void smmuv3_init_regs(SMMUv3State *s)
61
+
56
{
62
+/**
57
- /**
63
+ * kvm_get_vcpu_events:
58
- * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID,
64
+ * @cpu: ARMCPU
59
- * multi-level stream table
65
+ *
60
- */
66
+ * Get VCPU related state from kvm.
61
- s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supported */
67
+ */
62
+ /* Based on sys property, the stages supported in smmu will be advertised.*/
68
+int kvm_get_vcpu_events(ARMCPU *cpu);
63
+ if (s->stage && !strcmp("2", s->stage)) {
69
+
64
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S2P, 1);
70
+/**
65
+ } else {
71
+ * kvm_put_vcpu_events:
66
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, S1P, 1);
72
+ * @cpu: ARMCPU
73
+ *
74
+ * Put VCPU related state to kvm.
75
+ */
76
+int kvm_put_vcpu_events(ARMCPU *cpu);
77
+
78
#ifdef CONFIG_KVM
79
/**
80
* kvm_arm_create_scratch_host_vcpu:
81
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/kvm.c
84
+++ b/target/arm/kvm.c
85
@@ -XXX,XX +XXX,XX @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
86
};
87
88
static bool cap_has_mp_state;
89
+static bool cap_has_inject_serror_esr;
90
91
static ARMHostCPUFeatures arm_host_cpu_features;
92
93
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vcpu_init(CPUState *cs)
94
return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
95
}
96
97
+void kvm_arm_init_serror_injection(CPUState *cs)
98
+{
99
+ cap_has_inject_serror_esr = kvm_check_extension(cs->kvm_state,
100
+ KVM_CAP_ARM_INJECT_SERROR_ESR);
101
+}
102
+
103
bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
104
int *fdarray,
105
struct kvm_vcpu_init *init)
106
@@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
107
return 0;
108
}
109
110
+int kvm_put_vcpu_events(ARMCPU *cpu)
111
+{
112
+ CPUARMState *env = &cpu->env;
113
+ struct kvm_vcpu_events events;
114
+ int ret;
115
+
116
+ if (!kvm_has_vcpu_events()) {
117
+ return 0;
118
+ }
67
+ }
119
+
68
+
120
+ memset(&events, 0, sizeof(events));
69
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only */
121
+ events.exception.serror_pending = env->serror.pending;
70
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */
122
+
71
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */
123
+ /* Inject SError to guest with specified syndrome if host kernel
72
+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, VMID16, 1); /* 16-bit VMID */
124
+ * supports it, otherwise inject SError without syndrome.
73
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endian */
125
+ */
74
s->idr[0] = FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall */
126
+ if (cap_has_inject_serror_esr) {
75
/* terminated transaction will always be aborted/error returned */
127
+ events.exception.serror_has_esr = env->serror.has_esr;
76
@@ -XXX,XX +XXX,XX @@ static int decode_ste_s2_cfg(SMMUTransCfg *cfg, STE *ste)
128
+ events.exception.serror_esr = env->serror.esr;
77
goto bad_ste;
129
+ }
130
+
131
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
132
+ if (ret) {
133
+ error_report("failed to put vcpu events");
134
+ }
135
+
136
+ return ret;
137
+}
138
+
139
+int kvm_get_vcpu_events(ARMCPU *cpu)
140
+{
141
+ CPUARMState *env = &cpu->env;
142
+ struct kvm_vcpu_events events;
143
+ int ret;
144
+
145
+ if (!kvm_has_vcpu_events()) {
146
+ return 0;
147
+ }
148
+
149
+ memset(&events, 0, sizeof(events));
150
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
151
+ if (ret) {
152
+ error_report("failed to get vcpu events");
153
+ return ret;
154
+ }
155
+
156
+ env->serror.pending = events.exception.serror_pending;
157
+ env->serror.has_esr = events.exception.serror_has_esr;
158
+ env->serror.esr = events.exception.serror_esr;
159
+
160
+ return 0;
161
+}
162
+
163
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
164
{
165
}
166
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
167
index XXXXXXX..XXXXXXX 100644
168
--- a/target/arm/kvm32.c
169
+++ b/target/arm/kvm32.c
170
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
171
}
78
}
172
cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
79
173
80
- /* This is still here as stage 2 has not been fully enabled yet. */
174
+ /* Check whether userspace can specify guest syndrome value */
81
- qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n");
175
+ kvm_arm_init_serror_injection(cs);
82
- goto bad_ste;
176
+
83
-
177
return kvm_arm_init_cpreg_list(cpu);
84
return 0;
178
}
85
179
86
bad_ste:
180
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
87
@@ -XXX,XX +XXX,XX @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg,
181
return ret;
88
return ret;
182
}
89
}
183
90
184
+ ret = kvm_put_vcpu_events(cpu);
91
- if (cfg->aborted || cfg->bypassed) {
185
+ if (ret) {
92
+ if (cfg->aborted || cfg->bypassed || (cfg->stage == 2)) {
186
+ return ret;
93
return 0;
187
+ }
188
+
189
/* Note that we do not call write_cpustate_to_list()
190
* here, so we are only writing the tuple list back to
191
* KVM. This is safe because nothing can change the
192
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
193
}
94
}
194
vfp_set_fpscr(env, fpscr);
95
195
96
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
196
+ ret = kvm_get_vcpu_events(cpu);
197
+ if (ret) {
198
+ return ret;
199
+ }
200
+
201
if (!write_kvmstate_to_list(cpu)) {
202
return EINVAL;
203
}
97
}
204
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/kvm64.c
207
+++ b/target/arm/kvm64.c
208
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
209
210
kvm_arm_init_debug(cs);
211
212
+ /* Check whether user space can specify guest syndrome value */
213
+ kvm_arm_init_serror_injection(cs);
214
+
215
return kvm_arm_init_cpreg_list(cpu);
216
}
217
218
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
219
return ret;
220
}
221
222
+ ret = kvm_put_vcpu_events(cpu);
223
+ if (ret) {
224
+ return ret;
225
+ }
226
+
227
if (!write_list_to_kvmstate(cpu, level)) {
228
return EINVAL;
229
}
230
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
231
}
232
vfp_set_fpcr(env, fpr);
233
234
+ ret = kvm_get_vcpu_events(cpu);
235
+ if (ret) {
236
+ return ret;
237
+ }
238
+
239
if (!write_kvmstate_to_list(cpu)) {
240
return EINVAL;
241
}
242
diff --git a/target/arm/machine.c b/target/arm/machine.c
243
index XXXXXXX..XXXXXXX 100644
244
--- a/target/arm/machine.c
245
+++ b/target/arm/machine.c
246
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_sve = {
247
};
98
};
248
#endif /* AARCH64 */
99
249
100
+static Property smmuv3_properties[] = {
250
+static bool serror_needed(void *opaque)
101
+ /*
251
+{
102
+ * Stages of translation advertised.
252
+ ARMCPU *cpu = opaque;
103
+ * "1": Stage 1
253
+ CPUARMState *env = &cpu->env;
104
+ * "2": Stage 2
254
+
105
+ * Defaults to stage 1
255
+ return env->serror.pending != 0;
106
+ */
256
+}
107
+ DEFINE_PROP_STRING("stage", SMMUv3State, stage),
257
+
108
+ DEFINE_PROP_END_OF_LIST()
258
+static const VMStateDescription vmstate_serror = {
259
+ .name = "cpu/serror",
260
+ .version_id = 1,
261
+ .minimum_version_id = 1,
262
+ .needed = serror_needed,
263
+ .fields = (VMStateField[]) {
264
+ VMSTATE_UINT8(env.serror.pending, ARMCPU),
265
+ VMSTATE_UINT8(env.serror.has_esr, ARMCPU),
266
+ VMSTATE_UINT64(env.serror.esr, ARMCPU),
267
+ VMSTATE_END_OF_LIST()
268
+ }
269
+};
109
+};
270
+
110
+
271
static bool m_needed(void *opaque)
111
static void smmuv3_instance_init(Object *obj)
272
{
112
{
273
ARMCPU *cpu = opaque;
113
/* Nothing much to do here as of now */
274
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_arm_cpu = {
114
@@ -XXX,XX +XXX,XX @@ static void smmuv3_class_init(ObjectClass *klass, void *data)
275
#ifdef TARGET_AARCH64
115
&c->parent_phases);
276
&vmstate_sve,
116
c->parent_realize = dc->realize;
277
#endif
117
dc->realize = smmu_realize;
278
+ &vmstate_serror,
118
+ device_class_set_props(dc, smmuv3_properties);
279
NULL
119
}
280
}
120
281
};
121
static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,
282
--
122
--
283
2.19.1
123
2.34.1
284
285
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/45] target/arm: Move some system registers into a substructure
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Create struct ARMISARegisters, to be accessed during translation.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20181016223115.24100-2-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.h | 32 ++++----
11
hw/intc/armv7m_nvic.c | 12 +--
12
target/arm/cpu.c | 178 +++++++++++++++++++++---------------------
13
target/arm/cpu64.c | 70 ++++++++---------
14
target/arm/helper.c | 28 +++----
15
5 files changed, 162 insertions(+), 158 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
22
* ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
23
* is used for reset values of non-constant registers; no reset_
24
* prefix means a constant register.
25
+ * Some of these registers are split out into a substructure that
26
+ * is shared with the translators to control the ISA.
27
*/
28
+ struct ARMISARegisters {
29
+ uint32_t id_isar0;
30
+ uint32_t id_isar1;
31
+ uint32_t id_isar2;
32
+ uint32_t id_isar3;
33
+ uint32_t id_isar4;
34
+ uint32_t id_isar5;
35
+ uint32_t id_isar6;
36
+ uint32_t mvfr0;
37
+ uint32_t mvfr1;
38
+ uint32_t mvfr2;
39
+ uint64_t id_aa64isar0;
40
+ uint64_t id_aa64isar1;
41
+ uint64_t id_aa64pfr0;
42
+ uint64_t id_aa64pfr1;
43
+ } isar;
44
uint32_t midr;
45
uint32_t revidr;
46
uint32_t reset_fpsid;
47
- uint32_t mvfr0;
48
- uint32_t mvfr1;
49
- uint32_t mvfr2;
50
uint32_t ctr;
51
uint32_t reset_sctlr;
52
uint32_t id_pfr0;
53
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
54
uint32_t id_mmfr2;
55
uint32_t id_mmfr3;
56
uint32_t id_mmfr4;
57
- uint32_t id_isar0;
58
- uint32_t id_isar1;
59
- uint32_t id_isar2;
60
- uint32_t id_isar3;
61
- uint32_t id_isar4;
62
- uint32_t id_isar5;
63
- uint32_t id_isar6;
64
- uint64_t id_aa64pfr0;
65
- uint64_t id_aa64pfr1;
66
uint64_t id_aa64dfr0;
67
uint64_t id_aa64dfr1;
68
uint64_t id_aa64afr0;
69
uint64_t id_aa64afr1;
70
- uint64_t id_aa64isar0;
71
- uint64_t id_aa64isar1;
72
uint64_t id_aa64mmfr0;
73
uint64_t id_aa64mmfr1;
74
uint32_t dbgdidr;
75
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/hw/intc/armv7m_nvic.c
78
+++ b/hw/intc/armv7m_nvic.c
79
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
80
case 0xd5c: /* MMFR3. */
81
return cpu->id_mmfr3;
82
case 0xd60: /* ISAR0. */
83
- return cpu->id_isar0;
84
+ return cpu->isar.id_isar0;
85
case 0xd64: /* ISAR1. */
86
- return cpu->id_isar1;
87
+ return cpu->isar.id_isar1;
88
case 0xd68: /* ISAR2. */
89
- return cpu->id_isar2;
90
+ return cpu->isar.id_isar2;
91
case 0xd6c: /* ISAR3. */
92
- return cpu->id_isar3;
93
+ return cpu->isar.id_isar3;
94
case 0xd70: /* ISAR4. */
95
- return cpu->id_isar4;
96
+ return cpu->isar.id_isar4;
97
case 0xd74: /* ISAR5. */
98
- return cpu->id_isar5;
99
+ return cpu->isar.id_isar5;
100
case 0xd78: /* CLIDR */
101
return cpu->clidr;
102
case 0xd7c: /* CTR */
103
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/cpu.c
106
+++ b/target/arm/cpu.c
107
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
108
g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
109
110
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
111
- env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
112
- env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
113
- env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
114
+ env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
115
+ env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
116
+ env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
117
118
cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
119
s->halted = cpu->start_powered_off;
120
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
121
* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
122
*/
123
cpu->id_pfr1 &= ~0xf0;
124
- cpu->id_aa64pfr0 &= ~0xf000;
125
+ cpu->isar.id_aa64pfr0 &= ~0xf000;
126
}
127
128
if (!cpu->has_el2) {
129
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
130
* registers if we don't have EL2. These are id_pfr1[15:12] and
131
* id_aa64pfr0_el1[11:8].
132
*/
133
- cpu->id_aa64pfr0 &= ~0xf00;
134
+ cpu->isar.id_aa64pfr0 &= ~0xf00;
135
cpu->id_pfr1 &= ~0xf000;
136
}
137
138
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
139
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
140
cpu->midr = 0x4107b362;
141
cpu->reset_fpsid = 0x410120b4;
142
- cpu->mvfr0 = 0x11111111;
143
- cpu->mvfr1 = 0x00000000;
144
+ cpu->isar.mvfr0 = 0x11111111;
145
+ cpu->isar.mvfr1 = 0x00000000;
146
cpu->ctr = 0x1dd20d2;
147
cpu->reset_sctlr = 0x00050078;
148
cpu->id_pfr0 = 0x111;
149
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
150
cpu->id_mmfr0 = 0x01130003;
151
cpu->id_mmfr1 = 0x10030302;
152
cpu->id_mmfr2 = 0x01222110;
153
- cpu->id_isar0 = 0x00140011;
154
- cpu->id_isar1 = 0x12002111;
155
- cpu->id_isar2 = 0x11231111;
156
- cpu->id_isar3 = 0x01102131;
157
- cpu->id_isar4 = 0x141;
158
+ cpu->isar.id_isar0 = 0x00140011;
159
+ cpu->isar.id_isar1 = 0x12002111;
160
+ cpu->isar.id_isar2 = 0x11231111;
161
+ cpu->isar.id_isar3 = 0x01102131;
162
+ cpu->isar.id_isar4 = 0x141;
163
cpu->reset_auxcr = 7;
164
}
165
166
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
167
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
168
cpu->midr = 0x4117b363;
169
cpu->reset_fpsid = 0x410120b4;
170
- cpu->mvfr0 = 0x11111111;
171
- cpu->mvfr1 = 0x00000000;
172
+ cpu->isar.mvfr0 = 0x11111111;
173
+ cpu->isar.mvfr1 = 0x00000000;
174
cpu->ctr = 0x1dd20d2;
175
cpu->reset_sctlr = 0x00050078;
176
cpu->id_pfr0 = 0x111;
177
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
178
cpu->id_mmfr0 = 0x01130003;
179
cpu->id_mmfr1 = 0x10030302;
180
cpu->id_mmfr2 = 0x01222110;
181
- cpu->id_isar0 = 0x00140011;
182
- cpu->id_isar1 = 0x12002111;
183
- cpu->id_isar2 = 0x11231111;
184
- cpu->id_isar3 = 0x01102131;
185
- cpu->id_isar4 = 0x141;
186
+ cpu->isar.id_isar0 = 0x00140011;
187
+ cpu->isar.id_isar1 = 0x12002111;
188
+ cpu->isar.id_isar2 = 0x11231111;
189
+ cpu->isar.id_isar3 = 0x01102131;
190
+ cpu->isar.id_isar4 = 0x141;
191
cpu->reset_auxcr = 7;
192
}
193
194
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
195
set_feature(&cpu->env, ARM_FEATURE_EL3);
196
cpu->midr = 0x410fb767;
197
cpu->reset_fpsid = 0x410120b5;
198
- cpu->mvfr0 = 0x11111111;
199
- cpu->mvfr1 = 0x00000000;
200
+ cpu->isar.mvfr0 = 0x11111111;
201
+ cpu->isar.mvfr1 = 0x00000000;
202
cpu->ctr = 0x1dd20d2;
203
cpu->reset_sctlr = 0x00050078;
204
cpu->id_pfr0 = 0x111;
205
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
206
cpu->id_mmfr0 = 0x01130003;
207
cpu->id_mmfr1 = 0x10030302;
208
cpu->id_mmfr2 = 0x01222100;
209
- cpu->id_isar0 = 0x0140011;
210
- cpu->id_isar1 = 0x12002111;
211
- cpu->id_isar2 = 0x11231121;
212
- cpu->id_isar3 = 0x01102131;
213
- cpu->id_isar4 = 0x01141;
214
+ cpu->isar.id_isar0 = 0x0140011;
215
+ cpu->isar.id_isar1 = 0x12002111;
216
+ cpu->isar.id_isar2 = 0x11231121;
217
+ cpu->isar.id_isar3 = 0x01102131;
218
+ cpu->isar.id_isar4 = 0x01141;
219
cpu->reset_auxcr = 7;
220
}
221
222
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
223
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
224
cpu->midr = 0x410fb022;
225
cpu->reset_fpsid = 0x410120b4;
226
- cpu->mvfr0 = 0x11111111;
227
- cpu->mvfr1 = 0x00000000;
228
+ cpu->isar.mvfr0 = 0x11111111;
229
+ cpu->isar.mvfr1 = 0x00000000;
230
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
231
cpu->id_pfr0 = 0x111;
232
cpu->id_pfr1 = 0x1;
233
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
234
cpu->id_mmfr0 = 0x01100103;
235
cpu->id_mmfr1 = 0x10020302;
236
cpu->id_mmfr2 = 0x01222000;
237
- cpu->id_isar0 = 0x00100011;
238
- cpu->id_isar1 = 0x12002111;
239
- cpu->id_isar2 = 0x11221011;
240
- cpu->id_isar3 = 0x01102131;
241
- cpu->id_isar4 = 0x141;
242
+ cpu->isar.id_isar0 = 0x00100011;
243
+ cpu->isar.id_isar1 = 0x12002111;
244
+ cpu->isar.id_isar2 = 0x11221011;
245
+ cpu->isar.id_isar3 = 0x01102131;
246
+ cpu->isar.id_isar4 = 0x141;
247
cpu->reset_auxcr = 1;
248
}
249
250
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
251
cpu->id_mmfr1 = 0x00000000;
252
cpu->id_mmfr2 = 0x00000000;
253
cpu->id_mmfr3 = 0x00000000;
254
- cpu->id_isar0 = 0x01141110;
255
- cpu->id_isar1 = 0x02111000;
256
- cpu->id_isar2 = 0x21112231;
257
- cpu->id_isar3 = 0x01111110;
258
- cpu->id_isar4 = 0x01310102;
259
- cpu->id_isar5 = 0x00000000;
260
- cpu->id_isar6 = 0x00000000;
261
+ cpu->isar.id_isar0 = 0x01141110;
262
+ cpu->isar.id_isar1 = 0x02111000;
263
+ cpu->isar.id_isar2 = 0x21112231;
264
+ cpu->isar.id_isar3 = 0x01111110;
265
+ cpu->isar.id_isar4 = 0x01310102;
266
+ cpu->isar.id_isar5 = 0x00000000;
267
+ cpu->isar.id_isar6 = 0x00000000;
268
}
269
270
static void cortex_m4_initfn(Object *obj)
271
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
272
cpu->id_mmfr1 = 0x00000000;
273
cpu->id_mmfr2 = 0x00000000;
274
cpu->id_mmfr3 = 0x00000000;
275
- cpu->id_isar0 = 0x01141110;
276
- cpu->id_isar1 = 0x02111000;
277
- cpu->id_isar2 = 0x21112231;
278
- cpu->id_isar3 = 0x01111110;
279
- cpu->id_isar4 = 0x01310102;
280
- cpu->id_isar5 = 0x00000000;
281
- cpu->id_isar6 = 0x00000000;
282
+ cpu->isar.id_isar0 = 0x01141110;
283
+ cpu->isar.id_isar1 = 0x02111000;
284
+ cpu->isar.id_isar2 = 0x21112231;
285
+ cpu->isar.id_isar3 = 0x01111110;
286
+ cpu->isar.id_isar4 = 0x01310102;
287
+ cpu->isar.id_isar5 = 0x00000000;
288
+ cpu->isar.id_isar6 = 0x00000000;
289
}
290
291
static void cortex_m33_initfn(Object *obj)
292
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
293
cpu->id_mmfr1 = 0x00000000;
294
cpu->id_mmfr2 = 0x01000000;
295
cpu->id_mmfr3 = 0x00000000;
296
- cpu->id_isar0 = 0x01101110;
297
- cpu->id_isar1 = 0x02212000;
298
- cpu->id_isar2 = 0x20232232;
299
- cpu->id_isar3 = 0x01111131;
300
- cpu->id_isar4 = 0x01310132;
301
- cpu->id_isar5 = 0x00000000;
302
- cpu->id_isar6 = 0x00000000;
303
+ cpu->isar.id_isar0 = 0x01101110;
304
+ cpu->isar.id_isar1 = 0x02212000;
305
+ cpu->isar.id_isar2 = 0x20232232;
306
+ cpu->isar.id_isar3 = 0x01111131;
307
+ cpu->isar.id_isar4 = 0x01310132;
308
+ cpu->isar.id_isar5 = 0x00000000;
309
+ cpu->isar.id_isar6 = 0x00000000;
310
cpu->clidr = 0x00000000;
311
cpu->ctr = 0x8000c000;
312
}
313
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
314
cpu->id_mmfr1 = 0x00000000;
315
cpu->id_mmfr2 = 0x01200000;
316
cpu->id_mmfr3 = 0x0211;
317
- cpu->id_isar0 = 0x02101111;
318
- cpu->id_isar1 = 0x13112111;
319
- cpu->id_isar2 = 0x21232141;
320
- cpu->id_isar3 = 0x01112131;
321
- cpu->id_isar4 = 0x0010142;
322
- cpu->id_isar5 = 0x0;
323
- cpu->id_isar6 = 0x0;
324
+ cpu->isar.id_isar0 = 0x02101111;
325
+ cpu->isar.id_isar1 = 0x13112111;
326
+ cpu->isar.id_isar2 = 0x21232141;
327
+ cpu->isar.id_isar3 = 0x01112131;
328
+ cpu->isar.id_isar4 = 0x0010142;
329
+ cpu->isar.id_isar5 = 0x0;
330
+ cpu->isar.id_isar6 = 0x0;
331
cpu->mp_is_up = true;
332
cpu->pmsav7_dregion = 16;
333
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
334
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
335
set_feature(&cpu->env, ARM_FEATURE_EL3);
336
cpu->midr = 0x410fc080;
337
cpu->reset_fpsid = 0x410330c0;
338
- cpu->mvfr0 = 0x11110222;
339
- cpu->mvfr1 = 0x00011111;
340
+ cpu->isar.mvfr0 = 0x11110222;
341
+ cpu->isar.mvfr1 = 0x00011111;
342
cpu->ctr = 0x82048004;
343
cpu->reset_sctlr = 0x00c50078;
344
cpu->id_pfr0 = 0x1031;
345
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
346
cpu->id_mmfr1 = 0x20000000;
347
cpu->id_mmfr2 = 0x01202000;
348
cpu->id_mmfr3 = 0x11;
349
- cpu->id_isar0 = 0x00101111;
350
- cpu->id_isar1 = 0x12112111;
351
- cpu->id_isar2 = 0x21232031;
352
- cpu->id_isar3 = 0x11112131;
353
- cpu->id_isar4 = 0x00111142;
354
+ cpu->isar.id_isar0 = 0x00101111;
355
+ cpu->isar.id_isar1 = 0x12112111;
356
+ cpu->isar.id_isar2 = 0x21232031;
357
+ cpu->isar.id_isar3 = 0x11112131;
358
+ cpu->isar.id_isar4 = 0x00111142;
359
cpu->dbgdidr = 0x15141000;
360
cpu->clidr = (1 << 27) | (2 << 24) | 3;
361
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
362
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
363
set_feature(&cpu->env, ARM_FEATURE_CBAR);
364
cpu->midr = 0x410fc090;
365
cpu->reset_fpsid = 0x41033090;
366
- cpu->mvfr0 = 0x11110222;
367
- cpu->mvfr1 = 0x01111111;
368
+ cpu->isar.mvfr0 = 0x11110222;
369
+ cpu->isar.mvfr1 = 0x01111111;
370
cpu->ctr = 0x80038003;
371
cpu->reset_sctlr = 0x00c50078;
372
cpu->id_pfr0 = 0x1031;
373
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
374
cpu->id_mmfr1 = 0x20000000;
375
cpu->id_mmfr2 = 0x01230000;
376
cpu->id_mmfr3 = 0x00002111;
377
- cpu->id_isar0 = 0x00101111;
378
- cpu->id_isar1 = 0x13112111;
379
- cpu->id_isar2 = 0x21232041;
380
- cpu->id_isar3 = 0x11112131;
381
- cpu->id_isar4 = 0x00111142;
382
+ cpu->isar.id_isar0 = 0x00101111;
383
+ cpu->isar.id_isar1 = 0x13112111;
384
+ cpu->isar.id_isar2 = 0x21232041;
385
+ cpu->isar.id_isar3 = 0x11112131;
386
+ cpu->isar.id_isar4 = 0x00111142;
387
cpu->dbgdidr = 0x35141000;
388
cpu->clidr = (1 << 27) | (1 << 24) | 3;
389
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
390
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
391
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
392
cpu->midr = 0x410fc075;
393
cpu->reset_fpsid = 0x41023075;
394
- cpu->mvfr0 = 0x10110222;
395
- cpu->mvfr1 = 0x11111111;
396
+ cpu->isar.mvfr0 = 0x10110222;
397
+ cpu->isar.mvfr1 = 0x11111111;
398
cpu->ctr = 0x84448003;
399
cpu->reset_sctlr = 0x00c50078;
400
cpu->id_pfr0 = 0x00001131;
401
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
402
/* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
403
* table 4-41 gives 0x02101110, which includes the arm div insns.
404
*/
405
- cpu->id_isar0 = 0x02101110;
406
- cpu->id_isar1 = 0x13112111;
407
- cpu->id_isar2 = 0x21232041;
408
- cpu->id_isar3 = 0x11112131;
409
- cpu->id_isar4 = 0x10011142;
410
+ cpu->isar.id_isar0 = 0x02101110;
411
+ cpu->isar.id_isar1 = 0x13112111;
412
+ cpu->isar.id_isar2 = 0x21232041;
413
+ cpu->isar.id_isar3 = 0x11112131;
414
+ cpu->isar.id_isar4 = 0x10011142;
415
cpu->dbgdidr = 0x3515f005;
416
cpu->clidr = 0x0a200023;
417
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
418
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
419
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
420
cpu->midr = 0x412fc0f1;
421
cpu->reset_fpsid = 0x410430f0;
422
- cpu->mvfr0 = 0x10110222;
423
- cpu->mvfr1 = 0x11111111;
424
+ cpu->isar.mvfr0 = 0x10110222;
425
+ cpu->isar.mvfr1 = 0x11111111;
426
cpu->ctr = 0x8444c004;
427
cpu->reset_sctlr = 0x00c50078;
428
cpu->id_pfr0 = 0x00001131;
429
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
430
cpu->id_mmfr1 = 0x20000000;
431
cpu->id_mmfr2 = 0x01240000;
432
cpu->id_mmfr3 = 0x02102211;
433
- cpu->id_isar0 = 0x02101110;
434
- cpu->id_isar1 = 0x13112111;
435
- cpu->id_isar2 = 0x21232041;
436
- cpu->id_isar3 = 0x11112131;
437
- cpu->id_isar4 = 0x10011142;
438
+ cpu->isar.id_isar0 = 0x02101110;
439
+ cpu->isar.id_isar1 = 0x13112111;
440
+ cpu->isar.id_isar2 = 0x21232041;
441
+ cpu->isar.id_isar3 = 0x11112131;
442
+ cpu->isar.id_isar4 = 0x10011142;
443
cpu->dbgdidr = 0x3515f021;
444
cpu->clidr = 0x0a200023;
445
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
446
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
447
index XXXXXXX..XXXXXXX 100644
448
--- a/target/arm/cpu64.c
449
+++ b/target/arm/cpu64.c
450
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
451
cpu->midr = 0x411fd070;
452
cpu->revidr = 0x00000000;
453
cpu->reset_fpsid = 0x41034070;
454
- cpu->mvfr0 = 0x10110222;
455
- cpu->mvfr1 = 0x12111111;
456
- cpu->mvfr2 = 0x00000043;
457
+ cpu->isar.mvfr0 = 0x10110222;
458
+ cpu->isar.mvfr1 = 0x12111111;
459
+ cpu->isar.mvfr2 = 0x00000043;
460
cpu->ctr = 0x8444c004;
461
cpu->reset_sctlr = 0x00c50838;
462
cpu->id_pfr0 = 0x00000131;
463
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
464
cpu->id_mmfr1 = 0x40000000;
465
cpu->id_mmfr2 = 0x01260000;
466
cpu->id_mmfr3 = 0x02102211;
467
- cpu->id_isar0 = 0x02101110;
468
- cpu->id_isar1 = 0x13112111;
469
- cpu->id_isar2 = 0x21232042;
470
- cpu->id_isar3 = 0x01112131;
471
- cpu->id_isar4 = 0x00011142;
472
- cpu->id_isar5 = 0x00011121;
473
- cpu->id_isar6 = 0;
474
- cpu->id_aa64pfr0 = 0x00002222;
475
+ cpu->isar.id_isar0 = 0x02101110;
476
+ cpu->isar.id_isar1 = 0x13112111;
477
+ cpu->isar.id_isar2 = 0x21232042;
478
+ cpu->isar.id_isar3 = 0x01112131;
479
+ cpu->isar.id_isar4 = 0x00011142;
480
+ cpu->isar.id_isar5 = 0x00011121;
481
+ cpu->isar.id_isar6 = 0;
482
+ cpu->isar.id_aa64pfr0 = 0x00002222;
483
cpu->id_aa64dfr0 = 0x10305106;
484
cpu->pmceid0 = 0x00000000;
485
cpu->pmceid1 = 0x00000000;
486
- cpu->id_aa64isar0 = 0x00011120;
487
+ cpu->isar.id_aa64isar0 = 0x00011120;
488
cpu->id_aa64mmfr0 = 0x00001124;
489
cpu->dbgdidr = 0x3516d000;
490
cpu->clidr = 0x0a200023;
491
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
492
cpu->midr = 0x410fd034;
493
cpu->revidr = 0x00000000;
494
cpu->reset_fpsid = 0x41034070;
495
- cpu->mvfr0 = 0x10110222;
496
- cpu->mvfr1 = 0x12111111;
497
- cpu->mvfr2 = 0x00000043;
498
+ cpu->isar.mvfr0 = 0x10110222;
499
+ cpu->isar.mvfr1 = 0x12111111;
500
+ cpu->isar.mvfr2 = 0x00000043;
501
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
502
cpu->reset_sctlr = 0x00c50838;
503
cpu->id_pfr0 = 0x00000131;
504
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
505
cpu->id_mmfr1 = 0x40000000;
506
cpu->id_mmfr2 = 0x01260000;
507
cpu->id_mmfr3 = 0x02102211;
508
- cpu->id_isar0 = 0x02101110;
509
- cpu->id_isar1 = 0x13112111;
510
- cpu->id_isar2 = 0x21232042;
511
- cpu->id_isar3 = 0x01112131;
512
- cpu->id_isar4 = 0x00011142;
513
- cpu->id_isar5 = 0x00011121;
514
- cpu->id_isar6 = 0;
515
- cpu->id_aa64pfr0 = 0x00002222;
516
+ cpu->isar.id_isar0 = 0x02101110;
517
+ cpu->isar.id_isar1 = 0x13112111;
518
+ cpu->isar.id_isar2 = 0x21232042;
519
+ cpu->isar.id_isar3 = 0x01112131;
520
+ cpu->isar.id_isar4 = 0x00011142;
521
+ cpu->isar.id_isar5 = 0x00011121;
522
+ cpu->isar.id_isar6 = 0;
523
+ cpu->isar.id_aa64pfr0 = 0x00002222;
524
cpu->id_aa64dfr0 = 0x10305106;
525
- cpu->id_aa64isar0 = 0x00011120;
526
+ cpu->isar.id_aa64isar0 = 0x00011120;
527
cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
528
cpu->dbgdidr = 0x3516d000;
529
cpu->clidr = 0x0a200023;
530
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
531
cpu->midr = 0x410fd083;
532
cpu->revidr = 0x00000000;
533
cpu->reset_fpsid = 0x41034080;
534
- cpu->mvfr0 = 0x10110222;
535
- cpu->mvfr1 = 0x12111111;
536
- cpu->mvfr2 = 0x00000043;
537
+ cpu->isar.mvfr0 = 0x10110222;
538
+ cpu->isar.mvfr1 = 0x12111111;
539
+ cpu->isar.mvfr2 = 0x00000043;
540
cpu->ctr = 0x8444c004;
541
cpu->reset_sctlr = 0x00c50838;
542
cpu->id_pfr0 = 0x00000131;
543
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
544
cpu->id_mmfr1 = 0x40000000;
545
cpu->id_mmfr2 = 0x01260000;
546
cpu->id_mmfr3 = 0x02102211;
547
- cpu->id_isar0 = 0x02101110;
548
- cpu->id_isar1 = 0x13112111;
549
- cpu->id_isar2 = 0x21232042;
550
- cpu->id_isar3 = 0x01112131;
551
- cpu->id_isar4 = 0x00011142;
552
- cpu->id_isar5 = 0x00011121;
553
- cpu->id_aa64pfr0 = 0x00002222;
554
+ cpu->isar.id_isar0 = 0x02101110;
555
+ cpu->isar.id_isar1 = 0x13112111;
556
+ cpu->isar.id_isar2 = 0x21232042;
557
+ cpu->isar.id_isar3 = 0x01112131;
558
+ cpu->isar.id_isar4 = 0x00011142;
559
+ cpu->isar.id_isar5 = 0x00011121;
560
+ cpu->isar.id_aa64pfr0 = 0x00002222;
561
cpu->id_aa64dfr0 = 0x10305106;
562
cpu->pmceid0 = 0x00000000;
563
cpu->pmceid1 = 0x00000000;
564
- cpu->id_aa64isar0 = 0x00011120;
565
+ cpu->isar.id_aa64isar0 = 0x00011120;
566
cpu->id_aa64mmfr0 = 0x00001124;
567
cpu->dbgdidr = 0x3516d000;
568
cpu->clidr = 0x0a200023;
569
diff --git a/target/arm/helper.c b/target/arm/helper.c
570
index XXXXXXX..XXXXXXX 100644
571
--- a/target/arm/helper.c
572
+++ b/target/arm/helper.c
573
@@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
574
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
575
{
576
ARMCPU *cpu = arm_env_get_cpu(env);
577
- uint64_t pfr0 = cpu->id_aa64pfr0;
578
+ uint64_t pfr0 = cpu->isar.id_aa64pfr0;
579
580
if (env->gicv3state) {
581
pfr0 |= 1 << 24;
582
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
583
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
584
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
585
.access = PL1_R, .type = ARM_CP_CONST,
586
- .resetvalue = cpu->id_isar0 },
587
+ .resetvalue = cpu->isar.id_isar0 },
588
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
589
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
590
.access = PL1_R, .type = ARM_CP_CONST,
591
- .resetvalue = cpu->id_isar1 },
592
+ .resetvalue = cpu->isar.id_isar1 },
593
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
594
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
595
.access = PL1_R, .type = ARM_CP_CONST,
596
- .resetvalue = cpu->id_isar2 },
597
+ .resetvalue = cpu->isar.id_isar2 },
598
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
599
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
600
.access = PL1_R, .type = ARM_CP_CONST,
601
- .resetvalue = cpu->id_isar3 },
602
+ .resetvalue = cpu->isar.id_isar3 },
603
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
604
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
605
.access = PL1_R, .type = ARM_CP_CONST,
606
- .resetvalue = cpu->id_isar4 },
607
+ .resetvalue = cpu->isar.id_isar4 },
608
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
609
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
610
.access = PL1_R, .type = ARM_CP_CONST,
611
- .resetvalue = cpu->id_isar5 },
612
+ .resetvalue = cpu->isar.id_isar5 },
613
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
614
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
615
.access = PL1_R, .type = ARM_CP_CONST,
616
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
617
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
618
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
619
.access = PL1_R, .type = ARM_CP_CONST,
620
- .resetvalue = cpu->id_isar6 },
621
+ .resetvalue = cpu->isar.id_isar6 },
622
REGINFO_SENTINEL
623
};
624
define_arm_cp_regs(cpu, v6_idregs);
625
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
626
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
627
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
628
.access = PL1_R, .type = ARM_CP_CONST,
629
- .resetvalue = cpu->id_aa64pfr1},
630
+ .resetvalue = cpu->isar.id_aa64pfr1},
631
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
632
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
633
.access = PL1_R, .type = ARM_CP_CONST,
634
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
635
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
636
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
637
.access = PL1_R, .type = ARM_CP_CONST,
638
- .resetvalue = cpu->id_aa64isar0 },
639
+ .resetvalue = cpu->isar.id_aa64isar0 },
640
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
641
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
642
.access = PL1_R, .type = ARM_CP_CONST,
643
- .resetvalue = cpu->id_aa64isar1 },
644
+ .resetvalue = cpu->isar.id_aa64isar1 },
645
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
646
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
647
.access = PL1_R, .type = ARM_CP_CONST,
648
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
649
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
650
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
651
.access = PL1_R, .type = ARM_CP_CONST,
652
- .resetvalue = cpu->mvfr0 },
653
+ .resetvalue = cpu->isar.mvfr0 },
654
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
655
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
656
.access = PL1_R, .type = ARM_CP_CONST,
657
- .resetvalue = cpu->mvfr1 },
658
+ .resetvalue = cpu->isar.mvfr1 },
659
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
660
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
661
.access = PL1_R, .type = ARM_CP_CONST,
662
- .resetvalue = cpu->mvfr2 },
663
+ .resetvalue = cpu->isar.mvfr2 },
664
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
665
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
666
.access = PL1_R, .type = ARM_CP_CONST,
667
--
668
2.19.1
669
670
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/45] target/arm: V8M should not imply V7VE
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Instantiating mps2-an505 (cortex-m33) will fail make check when
4
V7VE asserts that ID_ISAR0.Divide includes ARM division. It is
5
also wrong to include ARM_FEATURE_LPAE.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20181016223115.24100-3-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu.c | 6 +++++-
13
1 file changed, 5 insertions(+), 1 deletion(-)
14
15
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.c
18
+++ b/target/arm/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
20
21
/* Some features automatically imply others: */
22
if (arm_feature(env, ARM_FEATURE_V8)) {
23
- set_feature(env, ARM_FEATURE_V7VE);
24
+ if (arm_feature(env, ARM_FEATURE_M)) {
25
+ set_feature(env, ARM_FEATURE_V7);
26
+ } else {
27
+ set_feature(env, ARM_FEATURE_V7VE);
28
+ }
29
}
30
if (arm_feature(env, ARM_FEATURE_V7VE)) {
31
/* v7 Virtualization Extensions. In real hardware this implies
32
--
33
2.19.1
34
35
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/45] target/arm: Convert division from feature bits to isar0 tests
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Both arm and thumb2 division are controlled by the same ISAR field,
4
which takes care of the arm implies thumb case. Having M imply
5
thumb2 division was wrong for cortex-m0, which is v6m and does not
6
have thumb2 at all, much less thumb2 division.
7
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20181016223115.24100-5-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.h | 12 ++++++++++--
15
linux-user/elfload.c | 4 ++--
16
target/arm/cpu.c | 10 +---------
17
target/arm/translate.c | 4 ++--
18
4 files changed, 15 insertions(+), 15 deletions(-)
19
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
23
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@ enum arm_features {
25
ARM_FEATURE_VFP3,
26
ARM_FEATURE_VFP_FP16,
27
ARM_FEATURE_NEON,
28
- ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
29
ARM_FEATURE_M, /* Microcontroller profile. */
30
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
31
ARM_FEATURE_THUMB2EE,
32
@@ -XXX,XX +XXX,XX @@ enum arm_features {
33
ARM_FEATURE_V5,
34
ARM_FEATURE_STRONGARM,
35
ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
36
- ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
37
ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
38
ARM_FEATURE_GENERIC_TIMER,
39
ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
40
@@ -XXX,XX +XXX,XX @@ extern const uint64_t pred_esz_masks[4];
41
/*
42
* 32-bit feature tests via id registers.
43
*/
44
+static inline bool isar_feature_thumb_div(const ARMISARegisters *id)
45
+{
46
+ return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
47
+}
48
+
49
+static inline bool isar_feature_arm_div(const ARMISARegisters *id)
50
+{
51
+ return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
52
+}
53
+
54
static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
55
{
56
return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
57
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/linux-user/elfload.c
60
+++ b/linux-user/elfload.c
61
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
62
GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3);
63
GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
64
GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4);
65
- GET_FEATURE(ARM_FEATURE_ARM_DIV, ARM_HWCAP_ARM_IDIVA);
66
- GET_FEATURE(ARM_FEATURE_THUMB_DIV, ARM_HWCAP_ARM_IDIVT);
67
+ GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA);
68
+ GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT);
69
/* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c.
70
* Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of
71
* ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated
72
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/arm/cpu.c
75
+++ b/target/arm/cpu.c
76
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
77
* Presence of EL2 itself is ARM_FEATURE_EL2, and of the
78
* Security Extensions is ARM_FEATURE_EL3.
79
*/
80
- set_feature(env, ARM_FEATURE_ARM_DIV);
81
+ assert(cpu_isar_feature(arm_div, cpu));
82
set_feature(env, ARM_FEATURE_LPAE);
83
set_feature(env, ARM_FEATURE_V7);
84
}
85
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
86
if (arm_feature(env, ARM_FEATURE_V5)) {
87
set_feature(env, ARM_FEATURE_V4T);
88
}
89
- if (arm_feature(env, ARM_FEATURE_M)) {
90
- set_feature(env, ARM_FEATURE_THUMB_DIV);
91
- }
92
- if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
93
- set_feature(env, ARM_FEATURE_THUMB_DIV);
94
- }
95
if (arm_feature(env, ARM_FEATURE_VFP4)) {
96
set_feature(env, ARM_FEATURE_VFP3);
97
set_feature(env, ARM_FEATURE_VFP_FP16);
98
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
99
ARMCPU *cpu = ARM_CPU(obj);
100
101
set_feature(&cpu->env, ARM_FEATURE_V7);
102
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
103
- set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
104
set_feature(&cpu->env, ARM_FEATURE_V7MP);
105
set_feature(&cpu->env, ARM_FEATURE_PMSA);
106
cpu->midr = 0x411fc153; /* r1p3 */
107
diff --git a/target/arm/translate.c b/target/arm/translate.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/translate.c
110
+++ b/target/arm/translate.c
111
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
112
case 1:
113
case 3:
114
/* SDIV, UDIV */
115
- if (!arm_dc_feature(s, ARM_FEATURE_ARM_DIV)) {
116
+ if (!dc_isar_feature(arm_div, s)) {
117
goto illegal_op;
118
}
119
if (((insn >> 5) & 7) || (rd != 15)) {
120
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
121
tmp2 = load_reg(s, rm);
122
if ((op & 0x50) == 0x10) {
123
/* sdiv, udiv */
124
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DIV)) {
125
+ if (!dc_isar_feature(thumb_div, s)) {
126
goto illegal_op;
127
}
128
if (op & 0x20)
129
--
130
2.19.1
131
132
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/45] target/arm: Convert jazelle from feature bit to isar1 test
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Having V6 alone imply jazelle was wrong for cortex-m0.
4
Change to an assertion for V6 & !M.
5
6
This was harmless, because the only place we tested ARM_FEATURE_JAZELLE
7
was for 'bxj' in disas_arm(), which is unreachable for M-profile cores.
8
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20181016223115.24100-6-richard.henderson@linaro.org
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/cpu.h | 6 +++++-
16
target/arm/cpu.c | 17 ++++++++++++++---
17
target/arm/translate.c | 2 +-
18
3 files changed, 20 insertions(+), 5 deletions(-)
19
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
23
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@ enum arm_features {
25
ARM_FEATURE_PMU, /* has PMU support */
26
ARM_FEATURE_VBAR, /* has cp15 VBAR */
27
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
28
- ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */
29
ARM_FEATURE_SVE, /* has Scalable Vector Extension */
30
ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
31
ARM_FEATURE_M_MAIN, /* M profile Main Extension */
32
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_arm_div(const ARMISARegisters *id)
33
return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
34
}
35
36
+static inline bool isar_feature_jazelle(const ARMISARegisters *id)
37
+{
38
+ return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
39
+}
40
+
41
static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
42
{
43
return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
44
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu.c
47
+++ b/target/arm/cpu.c
48
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
49
}
50
if (arm_feature(env, ARM_FEATURE_V6)) {
51
set_feature(env, ARM_FEATURE_V5);
52
- set_feature(env, ARM_FEATURE_JAZELLE);
53
if (!arm_feature(env, ARM_FEATURE_M)) {
54
+ assert(cpu_isar_feature(jazelle, cpu));
55
set_feature(env, ARM_FEATURE_AUXCR);
56
}
57
}
58
@@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj)
59
set_feature(&cpu->env, ARM_FEATURE_VFP);
60
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
61
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
62
- set_feature(&cpu->env, ARM_FEATURE_JAZELLE);
63
cpu->midr = 0x41069265;
64
cpu->reset_fpsid = 0x41011090;
65
cpu->ctr = 0x1dd20d2;
66
cpu->reset_sctlr = 0x00090078;
67
+
68
+ /*
69
+ * ARMv5 does not have the ID_ISAR registers, but we can still
70
+ * set the field to indicate Jazelle support within QEMU.
71
+ */
72
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
73
}
74
75
static void arm946_initfn(Object *obj)
76
@@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj)
77
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
78
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
79
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
80
- set_feature(&cpu->env, ARM_FEATURE_JAZELLE);
81
cpu->midr = 0x4106a262;
82
cpu->reset_fpsid = 0x410110a0;
83
cpu->ctr = 0x1dd20d2;
84
cpu->reset_sctlr = 0x00090078;
85
cpu->reset_auxcr = 1;
86
+
87
+ /*
88
+ * ARMv5 does not have the ID_ISAR registers, but we can still
89
+ * set the field to indicate Jazelle support within QEMU.
90
+ */
91
+ cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
92
+
93
{
94
/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
95
ARMCPRegInfo ifar = {
96
diff --git a/target/arm/translate.c b/target/arm/translate.c
97
index XXXXXXX..XXXXXXX 100644
98
--- a/target/arm/translate.c
99
+++ b/target/arm/translate.c
100
@@ -XXX,XX +XXX,XX @@
101
#define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
102
/* currently all emulated v5 cores are also v5TE, so don't bother */
103
#define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
104
-#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE)
105
+#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s)
106
#define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
107
#define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
108
#define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
109
--
110
2.19.1
111
112
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/45] target/arm: Convert sve from feature bit to aa64pfr0 test
[PULL 12/21] hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tommy Wu <tommy.wu@sifive.com>
2
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
When we receive a packet from the xilinx_axienet and then try to s2mem
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
through the xilinx_axidma, if the descriptor ring buffer is full in the
5
Message-id: 20181016223115.24100-8-richard.henderson@linaro.org
5
xilinx axidma driver, we’ll assert the DMASR.HALTED in the
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
function : stream_process_s2mem and return 0. In the end, we’ll be stuck in
7
an infinite loop in axienet_eth_rx_notify.
8
9
This patch checks the DMASR.HALTED state when we try to push data
10
from xilinx axi-enet to xilinx axi-dma. When the DMASR.HALTED is asserted,
11
we will not keep pushing the data and then prevent the infinte loop.
12
13
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
14
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
15
Reviewed-by: Frank Chang <frank.chang@sifive.com>
16
Message-id: 20230519062137.1251741-1-tommy.wu@sifive.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
18
---
9
target/arm/cpu.h | 16 +++++++++++++++-
19
hw/dma/xilinx_axidma.c | 11 ++++++++---
10
linux-user/aarch64/signal.c | 4 ++--
20
1 file changed, 8 insertions(+), 3 deletions(-)
11
linux-user/elfload.c | 2 +-
12
linux-user/syscall.c | 10 ++++++----
13
target/arm/cpu64.c | 5 ++++-
14
target/arm/helper.c | 9 ++++++---
15
target/arm/machine.c | 3 +--
16
target/arm/translate-a64.c | 4 ++--
17
8 files changed, 37 insertions(+), 16 deletions(-)
18
21
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
20
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
24
--- a/hw/dma/xilinx_axidma.c
22
+++ b/target/arm/cpu.h
25
+++ b/hw/dma/xilinx_axidma.c
23
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
26
@@ -XXX,XX +XXX,XX @@ static inline int stream_idle(struct Stream *s)
24
FIELD(ID_AA64ISAR1, SB, 36, 4)
27
return !!(s->regs[R_DMASR] & DMASR_IDLE);
25
FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
26
27
+FIELD(ID_AA64PFR0, EL0, 0, 4)
28
+FIELD(ID_AA64PFR0, EL1, 4, 4)
29
+FIELD(ID_AA64PFR0, EL2, 8, 4)
30
+FIELD(ID_AA64PFR0, EL3, 12, 4)
31
+FIELD(ID_AA64PFR0, FP, 16, 4)
32
+FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
33
+FIELD(ID_AA64PFR0, GIC, 24, 4)
34
+FIELD(ID_AA64PFR0, RAS, 28, 4)
35
+FIELD(ID_AA64PFR0, SVE, 32, 4)
36
+
37
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
38
39
/* If adding a feature bit which corresponds to a Linux ELF
40
@@ -XXX,XX +XXX,XX @@ enum arm_features {
41
ARM_FEATURE_PMU, /* has PMU support */
42
ARM_FEATURE_VBAR, /* has cp15 VBAR */
43
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
44
- ARM_FEATURE_SVE, /* has Scalable Vector Extension */
45
ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
46
ARM_FEATURE_M_MAIN, /* M profile Main Extension */
47
};
48
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
49
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
50
}
28
}
51
29
52
+static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
30
+static inline int stream_halted(struct Stream *s)
53
+{
31
+{
54
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
32
+ return !!(s->regs[R_DMASR] & DMASR_HALTED);
55
+}
33
+}
56
+
34
+
57
/*
35
static void stream_reset(struct Stream *s)
58
* Forward to the above feature tests given an ARMCPU pointer.
59
*/
60
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/linux-user/aarch64/signal.c
63
+++ b/linux-user/aarch64/signal.c
64
@@ -XXX,XX +XXX,XX @@ static int target_restore_sigframe(CPUARMState *env,
65
break;
66
67
case TARGET_SVE_MAGIC:
68
- if (arm_feature(env, ARM_FEATURE_SVE)) {
69
+ if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) {
70
vq = (env->vfp.zcr_el[1] & 0xf) + 1;
71
sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
72
if (!sve && size == sve_size) {
73
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
74
&layout);
75
76
/* SVE state needs saving only if it exists. */
77
- if (arm_feature(env, ARM_FEATURE_SVE)) {
78
+ if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) {
79
vq = (env->vfp.zcr_el[1] & 0xf) + 1;
80
sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16);
81
sve_ofs = alloc_sigframe_space(sve_size, &layout);
82
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/linux-user/elfload.c
85
+++ b/linux-user/elfload.c
86
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
87
GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM);
88
GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP);
89
GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
90
- GET_FEATURE(ARM_FEATURE_SVE, ARM_HWCAP_A64_SVE);
91
+ GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
92
93
#undef GET_FEATURE
94
#undef GET_FEATURE_ID
95
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/linux-user/syscall.c
98
+++ b/linux-user/syscall.c
99
@@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
100
* even though the current architectural maximum is VQ=16.
101
*/
102
ret = -TARGET_EINVAL;
103
- if (arm_feature(cpu_env, ARM_FEATURE_SVE)
104
+ if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(cpu_env))
105
&& arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
106
CPUARMState *env = cpu_env;
107
ARMCPU *cpu = arm_env_get_cpu(env);
108
@@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
109
return ret;
110
case TARGET_PR_SVE_GET_VL:
111
ret = -TARGET_EINVAL;
112
- if (arm_feature(cpu_env, ARM_FEATURE_SVE)) {
113
- CPUARMState *env = cpu_env;
114
- ret = ((env->vfp.zcr_el[1] & 0xf) + 1) * 16;
115
+ {
116
+ ARMCPU *cpu = arm_env_get_cpu(cpu_env);
117
+ if (cpu_isar_feature(aa64_sve, cpu)) {
118
+ ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
119
+ }
120
}
121
return ret;
122
#endif /* AARCH64 */
123
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/target/arm/cpu64.c
126
+++ b/target/arm/cpu64.c
127
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
128
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
129
cpu->isar.id_aa64isar1 = t;
130
131
+ t = cpu->isar.id_aa64pfr0;
132
+ t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
133
+ cpu->isar.id_aa64pfr0 = t;
134
+
135
/* Replicate the same data to the 32-bit id registers. */
136
u = cpu->isar.id_isar5;
137
u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
138
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
139
* present in either.
140
*/
141
set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
142
- set_feature(&cpu->env, ARM_FEATURE_SVE);
143
/* For usermode -cpu max we can use a larger and more efficient DCZ
144
* blocksize since we don't have to follow what the hardware does.
145
*/
146
diff --git a/target/arm/helper.c b/target/arm/helper.c
147
index XXXXXXX..XXXXXXX 100644
148
--- a/target/arm/helper.c
149
+++ b/target/arm/helper.c
150
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
151
define_one_arm_cp_reg(cpu, &sctlr);
152
}
153
154
- if (arm_feature(env, ARM_FEATURE_SVE)) {
155
+ if (cpu_isar_feature(aa64_sve, cpu)) {
156
define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
157
if (arm_feature(env, ARM_FEATURE_EL2)) {
158
define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
159
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
160
uint32_t flags;
161
162
if (is_a64(env)) {
163
+ ARMCPU *cpu = arm_env_get_cpu(env);
164
+
165
*pc = env->pc;
166
flags = ARM_TBFLAG_AARCH64_STATE_MASK;
167
/* Get control bits for tagged addresses */
168
flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);
169
flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);
170
171
- if (arm_feature(env, ARM_FEATURE_SVE)) {
172
+ if (cpu_isar_feature(aa64_sve, cpu)) {
173
int sve_el = sve_exception_el(env, current_el);
174
uint32_t zcr_len;
175
176
@@ -XXX,XX +XXX,XX @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
177
void aarch64_sve_change_el(CPUARMState *env, int old_el,
178
int new_el, bool el0_a64)
179
{
36
{
180
+ ARMCPU *cpu = arm_env_get_cpu(env);
37
s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
181
int old_len, new_len;
38
@@ -XXX,XX +XXX,XX @@ static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
182
bool old_a64, new_a64;
39
uint64_t addr;
183
40
bool eop;
184
/* Nothing to do if no SVE. */
41
185
- if (!arm_feature(env, ARM_FEATURE_SVE)) {
42
- if (!stream_running(s) || stream_idle(s)) {
186
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
43
+ if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
187
return;
44
return;
188
}
45
}
189
46
190
diff --git a/target/arm/machine.c b/target/arm/machine.c
47
@@ -XXX,XX +XXX,XX @@ static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
191
index XXXXXXX..XXXXXXX 100644
48
unsigned int rxlen;
192
--- a/target/arm/machine.c
49
size_t pos = 0;
193
+++ b/target/arm/machine.c
50
194
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_iwmmxt = {
51
- if (!stream_running(s) || stream_idle(s)) {
195
static bool sve_needed(void *opaque)
52
+ if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
196
{
53
return 0;
197
ARMCPU *cpu = opaque;
54
}
198
- CPUARMState *env = &cpu->env;
55
199
56
@@ -XXX,XX +XXX,XX @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
200
- return arm_feature(env, ARM_FEATURE_SVE);
57
XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
201
+ return cpu_isar_feature(aa64_sve, cpu);
58
struct Stream *s = &ds->dma->streams[1];
202
}
59
203
60
- if (!stream_running(s) || stream_idle(s)) {
204
/* The first two words of each Zreg is stored in VFP state. */
61
+ if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
205
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
62
ds->dma->notify = notify;
206
index XXXXXXX..XXXXXXX 100644
63
ds->dma->notify_opaque = notify_opaque;
207
--- a/target/arm/translate-a64.c
64
return false;
208
+++ b/target/arm/translate-a64.c
209
@@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
210
cpu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
211
vfp_get_fpcr(env), vfp_get_fpsr(env));
212
213
- if (arm_feature(env, ARM_FEATURE_SVE) && sve_exception_el(env, el) == 0) {
214
+ if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
215
int j, zcr_len = sve_zcr_len_for_el(env, el);
216
217
for (i = 0; i <= FFR_PRED_NUM; i++) {
218
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
219
unallocated_encoding(s);
220
break;
221
case 0x2:
222
- if (!arm_dc_feature(s, ARM_FEATURE_SVE) || !disas_sve(s, insn)) {
223
+ if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) {
224
unallocated_encoding(s);
225
}
226
break;
227
--
65
--
228
2.19.1
66
2.34.1
229
67
230
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 44/45] target/arm: Remove writefn from TTBR0_EL3
[PULL 13/21] hw/arm/xlnx-zynqmp: fix unsigned error when checking the RPUs number
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Clément Chigot <chigot@adacore.com>
2
2
3
The EL3 version of this register does not include an ASID,
3
When passing --smp with a number lower than XLNX_ZYNQMP_NUM_APU_CPUS,
4
and so the tlb_flush performed by vmsa_ttbr_write is not needed.
4
the expression (ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS) will result
5
in a positive number as ms->smp.cpus is a unsigned int.
6
This will raise the following error afterwards, as Qemu will try to
7
instantiate some additional RPUs.
8
| $ qemu-system-aarch64 --smp 1 -M xlnx-zcu102
9
| **
10
| ERROR:../src/tcg/tcg.c:777:tcg_register_thread:
11
| assertion failed: (n < tcg_max_ctxs)
5
12
6
Reviewed-by: Aaron Lindsay <aaron@os.amperecomputing.com>
13
Signed-off-by: Clément Chigot <chigot@adacore.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Message-id: 20181019015617.22583-2-richard.henderson@linaro.org
16
Message-id: 20230524143714.565792-1-chigot@adacore.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
18
---
12
target/arm/helper.c | 2 +-
19
hw/arm/xlnx-zynqmp.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
20
1 file changed, 1 insertion(+), 1 deletion(-)
14
21
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
22
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
16
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
24
--- a/hw/arm/xlnx-zynqmp.c
18
+++ b/target/arm/helper.c
25
+++ b/hw/arm/xlnx-zynqmp.c
19
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
26
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
20
.fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
27
const char *boot_cpu, Error **errp)
21
{ .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
28
{
22
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
29
int i;
23
- .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
30
- int num_rpus = MIN(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS,
24
+ .access = PL3_RW, .resetvalue = 0,
31
+ int num_rpus = MIN((int)(ms->smp.cpus - XLNX_ZYNQMP_NUM_APU_CPUS),
25
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
32
XLNX_ZYNQMP_NUM_RPU_CPUS);
26
{ .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
33
27
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
34
if (num_rpus <= 0) {
28
--
35
--
29
2.19.1
36
2.34.1
30
37
31
38
diff view generated by jsdifflib
[Qemu-devel] [PULL 45/45] target/arm: Only flush tlb if ASID changes
[PULL 14/21] tests/qtest: Run arm-specific tests only if the required machine is available
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
Since QEMU does not implement ASIDs, changes to the ASID must flush the
3
pflash-cfi02-test.c always uses the "musicpal" machine for testing,
4
tlb. However, if the ASID does not change there is no reason to flush.
4
test-arm-mptimer.c always uses the "vexpress-a9" machine, and
5
microbit-test.c requires the "microbit" machine, so we should only
6
run these tests if the machines have been enabled in the configuration.
5
7
6
In testing a boot of the Ubuntu installer to the first menu, this reduces
8
Signed-off-by: Thomas Huth <thuth@redhat.com>
7
the number of flushes by 30%, or nearly 600k instances.
9
Reviewed-by: Fabiano Rosas <farosas@suse.de>
8
10
Message-id: 20230524080600.1618137-1-thuth@redhat.com
9
Reviewed-by: Aaron Lindsay <aaron@os.amperecomputing.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20181019015617.22583-3-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
target/arm/helper.c | 8 +++-----
13
tests/qtest/meson.build | 7 ++++---
17
1 file changed, 3 insertions(+), 5 deletions(-)
14
1 file changed, 4 insertions(+), 3 deletions(-)
18
15
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
18
--- a/tests/qtest/meson.build
22
+++ b/target/arm/helper.c
19
+++ b/tests/qtest/meson.build
23
@@ -XXX,XX +XXX,XX @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
20
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
24
static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
21
(config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
25
uint64_t value)
22
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
26
{
23
(config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
27
- /* 64 bit accesses to the TTBRs can change the ASID and so we
24
- (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
28
- * must flush the TLB.
25
+ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') and
29
- */
26
+ config_all_devices.has_key('CONFIG_MUSICPAL') ? ['pflash-cfi02-test'] : []) + \
30
- if (cpreg_field_is_64bit(ri)) {
27
(config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) + \
31
+ /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
28
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
32
+ if (cpreg_field_is_64bit(ri) &&
29
(config_all_devices.has_key('CONFIG_GENERIC_LOADER') ? ['hexloader-test'] : []) + \
33
+ extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
30
(config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
34
ARMCPU *cpu = arm_env_get_cpu(env);
31
+ (config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : []) + \
35
-
32
+ (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
36
tlb_flush(CPU(cpu));
33
['arm-cpu-features',
37
}
34
- 'microbit-test',
38
raw_write(env, ri, value);
35
- 'test-arm-mptimer',
36
'boot-serial-test']
37
38
# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
39
--
39
--
40
2.19.1
40
2.34.1
41
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/45] target/arm: Improve debug logging of AArch32 exception return
[PULL 15/21] target/arm: Explicitly select short-format FSR for M-profile
1
For AArch32, exception return happens through certain kinds
1
For M-profile, there is no guest-facing A-profile format FSR, but we
2
of CPSR write. We don't currently have any CPU_LOG_INT logging
2
still use the env->exception.fsr field to pass fault information from
3
of these events (unlike AArch64, where we log in the ERET
3
the point where a fault is raised to the code in
4
instruction). Add some suitable logging.
4
arm_v7m_cpu_do_interrupt() which interprets it and sets the M-profile
5
specific fault status registers. So it doesn't matter whether we
6
fill in env->exception.fsr in the short format or the LPAE format, as
7
long as both sides agree. As it happens arm_v7m_cpu_do_interrupt()
8
assumes short-form.
5
9
6
This will log exception returns like this:
10
In compute_fsr_fsc() we weren't explicitly choosing short-form for
7
Exception return from AArch32 hyp to usr PC 0x80100374
11
M-profile, but instead relied on it falling out in the wash because
12
arm_s1_regime_using_lpae_format() would be false. This was broken in
13
commit 452c67a4 when we added v8R support, because we said "PMSAv8 is
14
always LPAE format" (as it is for v8R), forgetting that we were
15
implicitly using this code path on M-profile. At that point we would
16
hit a g_assert_not_reached():
17
ERROR:../../target/arm/internals.h:549:arm_fi_to_lfsc: code should not be reached
8
18
9
paralleling the existing logging in the exception_return
19
#7 0x0000555555e055f7 in arm_fi_to_lfsc (fi=0x7fffecff9a90) at ../../target/arm/internals.h:549
10
helper for AArch64 exception returns:
20
#8 0x0000555555e05a27 in compute_fsr_fsc (env=0x555557356670, fi=0x7fffecff9a90, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff9a1c)
11
Exception return from AArch64 EL2 to AArch64 EL0 PC 0x8003045c
21
at ../../target/arm/tlb_helper.c:95
12
Exception return from AArch64 EL2 to AArch32 EL0 PC 0x8003045c
22
#9 0x0000555555e05b62 in arm_deliver_fault (cpu=0x555557354800, addr=268961344, access_type=MMU_INST_FETCH, mmu_idx=1, fi=0x7fffecff9a90)
23
at ../../target/arm/tlb_helper.c:132
24
#10 0x0000555555e06095 in arm_cpu_tlb_fill (cs=0x555557354800, address=268961344, size=1, access_type=MMU_INST_FETCH, mmu_idx=1, probe=false, retaddr=0)
25
at ../../target/arm/tlb_helper.c:260
13
26
14
(Note that an AArch32 exception return can only be
27
The specific assertion changed when commit fcc7404eff24b4c added
15
AArch32->AArch32, never to AArch64.)
28
"assert not M-profile" to arm_is_secure_below_el3(), because the
29
conditions being checked in compute_fsr_fsc() include
30
arm_el_is_aa64(), which will end up calling arm_is_secure_below_el3()
31
and asserting before we try to call arm_fi_to_lfsc():
16
32
33
#7 0x0000555555efaf43 in arm_is_secure_below_el3 (env=0x5555574665a0) at ../../target/arm/cpu.h:2396
34
#8 0x0000555555efb103 in arm_is_el2_enabled (env=0x5555574665a0) at ../../target/arm/cpu.h:2448
35
#9 0x0000555555efb204 in arm_el_is_aa64 (env=0x5555574665a0, el=1) at ../../target/arm/cpu.h:2509
36
#10 0x0000555555efbdfd in compute_fsr_fsc (env=0x5555574665a0, fi=0x7fffecff99e0, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff996c)
37
38
Avoid the assertion and the incorrect FSR format selection by
39
explicitly making M-profile use the short-format in this function.
40
41
Fixes: 452c67a42704 ("target/arm: Enable TTBCR_EAE for ARMv8-R AArch32")a
42
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1658
43
Cc: qemu-stable@nongnu.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
44
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
45
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20181012144235.19646-2-peter.maydell@linaro.org
46
Message-id: 20230523131726.866635-1-peter.maydell@linaro.org
20
---
47
---
21
target/arm/internals.h | 18 ++++++++++++++++++
48
target/arm/tcg/tlb_helper.c | 13 +++++++++++--
22
target/arm/helper.c | 10 ++++++++++
49
1 file changed, 11 insertions(+), 2 deletions(-)
23
target/arm/translate.c | 7 +------
24
3 files changed, 29 insertions(+), 6 deletions(-)
25
50
26
diff --git a/target/arm/internals.h b/target/arm/internals.h
51
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
27
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/internals.h
53
--- a/target/arm/tcg/tlb_helper.c
29
+++ b/target/arm/internals.h
54
+++ b/target/arm/tcg/tlb_helper.c
30
@@ -XXX,XX +XXX,XX @@ static inline uint32_t v7m_sp_limit(CPUARMState *env)
55
@@ -XXX,XX +XXX,XX @@ static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
31
}
56
ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
32
}
57
uint32_t fsr, fsc;
33
58
34
+/**
59
- if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
35
+ * aarch32_mode_name(): Return name of the AArch32 CPU mode
60
- arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
36
+ * @psr: Program Status Register indicating CPU mode
61
+ /*
37
+ *
62
+ * For M-profile there is no guest-facing FSR. We compute a
38
+ * Returns, for debug logging purposes, a printable representation
63
+ * short-form value for env->exception.fsr which we will then
39
+ * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by
64
+ * examine in arm_v7m_cpu_do_interrupt(). In theory we could
40
+ * the low bits of the specified PSR.
65
+ * use the LPAE format instead as long as both bits of code agree
41
+ */
66
+ * (and arm_fi_to_lfsc() handled the M-profile specific
42
+static inline const char *aarch32_mode_name(uint32_t psr)
67
+ * ARMFault_QEMU_NSCExec and ARMFault_QEMU_SFault cases).
43
+{
68
+ */
44
+ static const char cpu_mode_names[16][4] = {
69
+ if (!arm_feature(env, ARM_FEATURE_M) &&
45
+ "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
70
+ (target_el == 2 || arm_el_is_aa64(env, target_el) ||
46
+ "???", "???", "hyp", "und", "???", "???", "???", "sys"
71
+ arm_s1_regime_using_lpae_format(env, arm_mmu_idx))) {
47
+ };
72
/*
48
+
73
* LPAE format fault status register : bottom 6 bits are
49
+ return cpu_mode_names[psr & 0xf];
74
* status code in the same form as needed for syndrome
50
+}
51
+
52
#endif
53
diff --git a/target/arm/helper.c b/target/arm/helper.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/arm/helper.c
56
+++ b/target/arm/helper.c
57
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
58
mask |= CPSR_IL;
59
val |= CPSR_IL;
60
}
61
+ qemu_log_mask(LOG_GUEST_ERROR,
62
+ "Illegal AArch32 mode switch attempt from %s to %s\n",
63
+ aarch32_mode_name(env->uncached_cpsr),
64
+ aarch32_mode_name(val));
65
} else {
66
+ qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n",
67
+ write_type == CPSRWriteExceptionReturn ?
68
+ "Exception return from AArch32" :
69
+ "AArch32 mode switch from",
70
+ aarch32_mode_name(env->uncached_cpsr),
71
+ aarch32_mode_name(val), env->regs[15]);
72
switch_mode(env, val & CPSR_M);
73
}
74
}
75
diff --git a/target/arm/translate.c b/target/arm/translate.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/translate.c
78
+++ b/target/arm/translate.c
79
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
80
translator_loop(ops, &dc.base, cpu, tb);
81
}
82
83
-static const char *cpu_mode_names[16] = {
84
- "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
85
- "???", "???", "hyp", "und", "???", "???", "???", "sys"
86
-};
87
-
88
void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
89
int flags)
90
{
91
@@ -XXX,XX +XXX,XX @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
92
psr & CPSR_V ? 'V' : '-',
93
psr & CPSR_T ? 'T' : 'A',
94
ns_status,
95
- cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
96
+ aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
97
}
98
99
if (flags & CPU_DUMP_FPU) {
100
--
75
--
101
2.19.1
76
2.34.1
102
103
diff view generated by jsdifflib
[Qemu-devel] [PULL 40/45] target/arm: Promote consecutive memory ops for aa32
[PULL 16/21] target/arm: Explain why we need to select ARM_V7M
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
For a sequence of loads or stores from a single register,
3
We currently need to select ARM_V7M unconditionally when TCG is
4
little-endian operations can be promoted to an 8-byte op.
4
present in the build because some translate.c helpers and the whole of
5
This can reduce the number of operations by a factor of 8.
5
m_helpers.c are not yet under CONFIG_ARM_V7M.
6
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20181011205206.3552-20-richard.henderson@linaro.org
8
Signed-off-by: Fabiano Rosas <farosas@suse.de>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20230523180525.29994-2-farosas@suse.de
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
target/arm/translate.c | 10 ++++++++++
13
target/arm/Kconfig | 3 +++
14
1 file changed, 10 insertions(+)
14
1 file changed, 3 insertions(+)
15
15
16
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate.c
18
--- a/target/arm/Kconfig
19
+++ b/target/arm/translate.c
19
+++ b/target/arm/Kconfig
20
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
20
@@ -XXX,XX +XXX,XX @@
21
if (size == 3 && (interleave | spacing) != 1) {
21
config ARM
22
return 1;
22
bool
23
}
23
select ARM_COMPATIBLE_SEMIHOSTING if TCG
24
+ /* For our purposes, bytes are always little-endian. */
24
+
25
+ if (size == 0) {
25
+ # We need to select this until we move m_helper.c and the
26
+ endian = MO_LE;
26
+ # translate.c v7m helpers under ARM_V7M.
27
+ }
27
select ARM_V7M if TCG
28
+ /* Consecutive little-endian elements from a single register
28
29
+ * can be promoted to a larger little-endian operation.
29
config AARCH64
30
+ */
31
+ if (interleave == 1 && endian == MO_LE) {
32
+ size = 3;
33
+ }
34
tmp64 = tcg_temp_new_i64();
35
addr = tcg_temp_new_i32();
36
tmp2 = tcg_const_i32(1 << size);
37
--
30
--
38
2.19.1
31
2.34.1
39
32
40
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 37/45] target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE
[PULL 17/21] arm/Kconfig: Keep Kconfig default entries in default.mak as documentation
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Move cmtst_op expanders from translate-a64.c.
3
When we moved the arm default CONFIGs into Kconfig and removed them
4
from default.mak, we made it harder to identify which CONFIGs are
5
selected by default in case users want to disable them.
4
6
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Bring back the default entries into default.mak, but keep them
6
Message-id: 20181011205206.3552-17-richard.henderson@linaro.org
8
commented out. This way users can keep their workflows of editing
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
default.mak to remove build options without needing to search through
10
Kconfig.
11
12
Reported-by: Thomas Huth <thuth@redhat.com>
13
Signed-off-by: Fabiano Rosas <farosas@suse.de>
14
Reviewed-by: Thomas Huth <thuth@redhat.com>
15
Message-id: 20230523180525.29994-3-farosas@suse.de
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
17
---
10
target/arm/translate.h | 2 +
18
configs/devices/aarch64-softmmu/default.mak | 6 ++++
11
target/arm/translate-a64.c | 38 ------------------
19
configs/devices/arm-softmmu/default.mak | 40 +++++++++++++++++++++
12
target/arm/translate.c | 81 +++++++++++++++++++++++++++-----------
20
2 files changed, 46 insertions(+)
13
3 files changed, 60 insertions(+), 61 deletions(-)
14
21
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
22
diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/aarch64-softmmu/default.mak
16
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
24
--- a/configs/devices/aarch64-softmmu/default.mak
18
+++ b/target/arm/translate.h
25
+++ b/configs/devices/aarch64-softmmu/default.mak
19
@@ -XXX,XX +XXX,XX @@ extern const GVecGen3 bit_op;
26
@@ -XXX,XX +XXX,XX @@
20
extern const GVecGen3 bif_op;
27
21
extern const GVecGen3 mla_op[4];
28
# We support all the 32 bit boards so need all their config
22
extern const GVecGen3 mls_op[4];
29
include ../arm-softmmu/default.mak
23
+extern const GVecGen3 cmtst_op[4];
30
+
24
extern const GVecGen2i ssra_op[4];
31
+# These are selected by default when TCG is enabled, uncomment them to
25
extern const GVecGen2i usra_op[4];
32
+# keep out of the build.
26
extern const GVecGen2i sri_op[4];
33
+# CONFIG_XLNX_ZYNQMP_ARM=n
27
extern const GVecGen2i sli_op[4];
34
+# CONFIG_XLNX_VERSAL=n
28
+void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
35
+# CONFIG_SBSA_REF=n
29
36
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
30
/*
31
* Forward to the isar_feature_* tests given a DisasContext pointer.
32
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
33
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/translate-a64.c
38
--- a/configs/devices/arm-softmmu/default.mak
35
+++ b/target/arm/translate-a64.c
39
+++ b/configs/devices/arm-softmmu/default.mak
36
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
40
@@ -XXX,XX +XXX,XX @@
37
}
41
# CONFIG_TEST_DEVICES=n
38
}
42
39
43
CONFIG_ARM_VIRT=y
40
-/* CMTST : test is "if (X & Y != 0)". */
41
-static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
42
-{
43
- tcg_gen_and_i32(d, a, b);
44
- tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0);
45
- tcg_gen_neg_i32(d, d);
46
-}
47
-
48
-static void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
49
-{
50
- tcg_gen_and_i64(d, a, b);
51
- tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0);
52
- tcg_gen_neg_i64(d, d);
53
-}
54
-
55
-static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
56
-{
57
- tcg_gen_and_vec(vece, d, a, b);
58
- tcg_gen_dupi_vec(vece, a, 0);
59
- tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a);
60
-}
61
-
62
static void handle_3same_64(DisasContext *s, int opcode, bool u,
63
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm)
64
{
65
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
66
/* Integer op subgroup of C3.6.16. */
67
static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
68
{
69
- static const GVecGen3 cmtst_op[4] = {
70
- { .fni4 = gen_helper_neon_tst_u8,
71
- .fniv = gen_cmtst_vec,
72
- .vece = MO_8 },
73
- { .fni4 = gen_helper_neon_tst_u16,
74
- .fniv = gen_cmtst_vec,
75
- .vece = MO_16 },
76
- { .fni4 = gen_cmtst_i32,
77
- .fniv = gen_cmtst_vec,
78
- .vece = MO_32 },
79
- { .fni8 = gen_cmtst_i64,
80
- .fniv = gen_cmtst_vec,
81
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
82
- .vece = MO_64 },
83
- };
84
-
85
int is_q = extract32(insn, 30, 1);
86
int u = extract32(insn, 29, 1);
87
int size = extract32(insn, 22, 2);
88
diff --git a/target/arm/translate.c b/target/arm/translate.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/translate.c
91
+++ b/target/arm/translate.c
92
@@ -XXX,XX +XXX,XX @@ const GVecGen3 mls_op[4] = {
93
.vece = MO_64 },
94
};
95
96
+/* CMTST : test is "if (X & Y != 0)". */
97
+static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
98
+{
99
+ tcg_gen_and_i32(d, a, b);
100
+ tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0);
101
+ tcg_gen_neg_i32(d, d);
102
+}
103
+
44
+
104
+void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
45
+# These are selected by default when TCG is enabled, uncomment them to
105
+{
46
+# keep out of the build.
106
+ tcg_gen_and_i64(d, a, b);
47
+# CONFIG_CUBIEBOARD=n
107
+ tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0);
48
+# CONFIG_EXYNOS4=n
108
+ tcg_gen_neg_i64(d, d);
49
+# CONFIG_HIGHBANK=n
109
+}
50
+# CONFIG_INTEGRATOR=n
110
+
51
+# CONFIG_FSL_IMX31=n
111
+static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
52
+# CONFIG_MUSICPAL=n
112
+{
53
+# CONFIG_MUSCA=n
113
+ tcg_gen_and_vec(vece, d, a, b);
54
+# CONFIG_CHEETAH=n
114
+ tcg_gen_dupi_vec(vece, a, 0);
55
+# CONFIG_SX1=n
115
+ tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a);
56
+# CONFIG_NSERIES=n
116
+}
57
+# CONFIG_STELLARIS=n
117
+
58
+# CONFIG_STM32VLDISCOVERY=n
118
+const GVecGen3 cmtst_op[4] = {
59
+# CONFIG_REALVIEW=n
119
+ { .fni4 = gen_helper_neon_tst_u8,
60
+# CONFIG_VERSATILE=n
120
+ .fniv = gen_cmtst_vec,
61
+# CONFIG_VEXPRESS=n
121
+ .vece = MO_8 },
62
+# CONFIG_ZYNQ=n
122
+ { .fni4 = gen_helper_neon_tst_u16,
63
+# CONFIG_MAINSTONE=n
123
+ .fniv = gen_cmtst_vec,
64
+# CONFIG_GUMSTIX=n
124
+ .vece = MO_16 },
65
+# CONFIG_SPITZ=n
125
+ { .fni4 = gen_cmtst_i32,
66
+# CONFIG_TOSA=n
126
+ .fniv = gen_cmtst_vec,
67
+# CONFIG_Z2=n
127
+ .vece = MO_32 },
68
+# CONFIG_NPCM7XX=n
128
+ { .fni8 = gen_cmtst_i64,
69
+# CONFIG_COLLIE=n
129
+ .fniv = gen_cmtst_vec,
70
+# CONFIG_ASPEED_SOC=n
130
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
71
+# CONFIG_NETDUINO2=n
131
+ .vece = MO_64 },
72
+# CONFIG_NETDUINOPLUS2=n
132
+};
73
+# CONFIG_OLIMEX_STM32_H405=n
133
+
74
+# CONFIG_MPS2=n
134
/* Translate a NEON data processing instruction. Return nonzero if the
75
+# CONFIG_RASPI=n
135
instruction is invalid.
76
+# CONFIG_DIGIC=n
136
We process data in a mixture of 32-bit and 64-bit chunks.
77
+# CONFIG_SABRELITE=n
137
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
78
+# CONFIG_EMCRAFT_SF2=n
138
tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
79
+# CONFIG_MICROBIT=n
139
u ? &mls_op[size] : &mla_op[size]);
80
+# CONFIG_FSL_IMX25=n
140
return 0;
81
+# CONFIG_FSL_IMX7=n
141
+
82
+# CONFIG_FSL_IMX6UL=n
142
+ case NEON_3R_VTST_VCEQ:
83
+# CONFIG_ALLWINNER_H3=n
143
+ if (u) { /* VCEQ */
144
+ tcg_gen_gvec_cmp(TCG_COND_EQ, size, rd_ofs, rn_ofs, rm_ofs,
145
+ vec_size, vec_size);
146
+ } else { /* VTST */
147
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
148
+ vec_size, vec_size, &cmtst_op[size]);
149
+ }
150
+ return 0;
151
+
152
+ case NEON_3R_VCGT:
153
+ tcg_gen_gvec_cmp(u ? TCG_COND_GTU : TCG_COND_GT, size,
154
+ rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
155
+ return 0;
156
+
157
+ case NEON_3R_VCGE:
158
+ tcg_gen_gvec_cmp(u ? TCG_COND_GEU : TCG_COND_GE, size,
159
+ rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
160
+ return 0;
161
}
162
163
if (size == 3) {
164
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
165
case NEON_3R_VQSUB:
166
GEN_NEON_INTEGER_OP_ENV(qsub);
167
break;
168
- case NEON_3R_VCGT:
169
- GEN_NEON_INTEGER_OP(cgt);
170
- break;
171
- case NEON_3R_VCGE:
172
- GEN_NEON_INTEGER_OP(cge);
173
- break;
174
case NEON_3R_VSHL:
175
GEN_NEON_INTEGER_OP(shl);
176
break;
177
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
178
tmp2 = neon_load_reg(rd, pass);
179
gen_neon_add(size, tmp, tmp2);
180
break;
181
- case NEON_3R_VTST_VCEQ:
182
- if (!u) { /* VTST */
183
- switch (size) {
184
- case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
185
- case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
186
- case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
187
- default: abort();
188
- }
189
- } else { /* VCEQ */
190
- switch (size) {
191
- case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
192
- case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
193
- case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
194
- default: abort();
195
- }
196
- }
197
- break;
198
case NEON_3R_VMUL:
199
/* VMUL.P8; other cases already eliminated. */
200
gen_helper_neon_mul_p8(tmp, tmp, tmp2);
201
--
84
--
202
2.19.1
85
2.34.1
203
204
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/45] hw/arm/boot: Increase compliance with kernel arm64 boot protocol
[PULL 18/21] arm/Kconfig: Make TCG dependence explicit
1
From: Stewart Hildebrand <Stewart.Hildebrand@dornerworks.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
"The Image must be placed text_offset bytes from a 2MB aligned base
3
Replace the 'default y if TCG' pattern with 'default y; depends on
4
address anywhere in usable system RAM and called there."
4
TCG'.
5
5
6
For the virt board, we write our startup bootloader at the very
6
That makes explict that there is a dependence on TCG and enabling
7
bottom of RAM, so that bit can't be used for the image. To avoid
7
these CONFIGs via .mak files without TCG present will fail earlier.
8
overlap in case the image requests to be loaded at an offset
8
9
smaller than our bootloader, we increment the load offset to the
9
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
10
next 2MB.
10
Signed-off-by: Fabiano Rosas <farosas@suse.de>
11
11
Reviewed-by: Thomas Huth <thuth@redhat.com>
12
This fixes a boot failure for Xen AArch64.
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
13
Message-id: 20230523180525.29994-4-farosas@suse.de
14
Signed-off-by: Stewart Hildebrand <stewart.hildebrand@dornerworks.com>
15
Tested-by: Andre Przywara <andre.przywara@arm.com>
16
Message-id: b8a89518794b4436af0c151ed10de4fa@dornerworks.com
17
[PMM: Rephrased a comment a bit]
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
15
---
21
hw/arm/boot.c | 18 ++++++++++++++++++
16
hw/arm/Kconfig | 123 ++++++++++++++++++++++++++++++++-----------------
22
1 file changed, 18 insertions(+)
17
1 file changed, 82 insertions(+), 41 deletions(-)
23
18
24
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
19
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
25
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/boot.c
21
--- a/hw/arm/Kconfig
27
+++ b/hw/arm/boot.c
22
+++ b/hw/arm/Kconfig
28
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
29
#include "qemu/config-file.h"
24
30
#include "qemu/option.h"
25
config CHEETAH
31
#include "exec/address-spaces.h"
26
bool
32
+#include "qemu/units.h"
27
- default y if TCG && ARM
33
28
+ default y
34
/* Kernel boot protocol is specified in the kernel docs
29
+ depends on TCG && ARM
35
* Documentation/arm/Booting and Documentation/arm64/booting.txt
30
select OMAP
36
@@ -XXX,XX +XXX,XX @@
31
select TSC210X
37
#define ARM64_TEXT_OFFSET_OFFSET 8
32
38
#define ARM64_MAGIC_OFFSET 56
33
config CUBIEBOARD
39
34
bool
40
+#define BOOTLOADER_MAX_SIZE (4 * KiB)
35
- default y if TCG && ARM
41
+
36
+ default y
42
AddressSpace *arm_boot_address_space(ARMCPU *cpu,
37
+ depends on TCG && ARM
43
const struct arm_boot_info *info)
38
select ALLWINNER_A10
44
{
39
45
@@ -XXX,XX +XXX,XX @@ static void write_bootloader(const char *name, hwaddr addr,
40
config DIGIC
46
code[i] = tswap32(insn);
41
bool
47
}
42
- default y if TCG && ARM
48
43
+ default y
49
+ assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE);
44
+ depends on TCG && ARM
50
+
45
select PTIMER
51
rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as);
46
select PFLASH_CFI02
52
47
53
g_free(code);
48
config EXYNOS4
54
@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
49
bool
55
memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
50
- default y if TCG && ARM
56
if (hdrvals[1] != 0) {
51
+ default y
57
kernel_load_offset = le64_to_cpu(hdrvals[0]);
52
+ depends on TCG && ARM
58
+
53
imply I2C_DEVICES
59
+ /*
54
select A9MPCORE
60
+ * We write our startup "bootloader" at the very bottom of RAM,
55
select I2C
61
+ * so that bit can't be used for the image. Luckily the Image
56
@@ -XXX,XX +XXX,XX @@ config EXYNOS4
62
+ * format specification is that the image requests only an offset
57
63
+ * from a 2MB boundary, not an absolute load address. So if the
58
config HIGHBANK
64
+ * image requests an offset that might mean it overlaps with the
59
bool
65
+ * bootloader, we can just load it starting at 2MB+offset rather
60
- default y if TCG && ARM
66
+ * than 0MB + offset.
61
+ default y
67
+ */
62
+ depends on TCG && ARM
68
+ if (kernel_load_offset < BOOTLOADER_MAX_SIZE) {
63
select A9MPCORE
69
+ kernel_load_offset += 2 * MiB;
64
select A15MPCORE
70
+ }
65
select AHCI
71
}
66
@@ -XXX,XX +XXX,XX @@ config HIGHBANK
72
}
67
68
config INTEGRATOR
69
bool
70
- default y if TCG && ARM
71
+ default y
72
+ depends on TCG && ARM
73
select ARM_TIMER
74
select INTEGRATOR_DEBUG
75
select PL011 # UART
76
@@ -XXX,XX +XXX,XX @@ config INTEGRATOR
77
78
config MAINSTONE
79
bool
80
- default y if TCG && ARM
81
+ default y
82
+ depends on TCG && ARM
83
select PXA2XX
84
select PFLASH_CFI01
85
select SMC91C111
86
87
config MUSCA
88
bool
89
- default y if TCG && ARM
90
+ default y
91
+ depends on TCG && ARM
92
select ARMSSE
93
select PL011
94
select PL031
95
@@ -XXX,XX +XXX,XX @@ config MARVELL_88W8618
96
97
config MUSICPAL
98
bool
99
- default y if TCG && ARM
100
+ default y
101
+ depends on TCG && ARM
102
select OR_IRQ
103
select BITBANG_I2C
104
select MARVELL_88W8618
105
@@ -XXX,XX +XXX,XX @@ config MUSICPAL
106
107
config NETDUINO2
108
bool
109
- default y if TCG && ARM
110
+ default y
111
+ depends on TCG && ARM
112
select STM32F205_SOC
113
114
config NETDUINOPLUS2
115
bool
116
- default y if TCG && ARM
117
+ default y
118
+ depends on TCG && ARM
119
select STM32F405_SOC
120
121
config OLIMEX_STM32_H405
122
bool
123
- default y if TCG && ARM
124
+ default y
125
+ depends on TCG && ARM
126
select STM32F405_SOC
127
128
config NSERIES
129
bool
130
- default y if TCG && ARM
131
+ default y
132
+ depends on TCG && ARM
133
select OMAP
134
select TMP105 # temperature sensor
135
select BLIZZARD # LCD/TV controller
136
@@ -XXX,XX +XXX,XX @@ config PXA2XX
137
138
config GUMSTIX
139
bool
140
- default y if TCG && ARM
141
+ default y
142
+ depends on TCG && ARM
143
select PFLASH_CFI01
144
select SMC91C111
145
select PXA2XX
146
147
config TOSA
148
bool
149
- default y if TCG && ARM
150
+ default y
151
+ depends on TCG && ARM
152
select ZAURUS # scoop
153
select MICRODRIVE
154
select PXA2XX
155
@@ -XXX,XX +XXX,XX @@ config TOSA
156
157
config SPITZ
158
bool
159
- default y if TCG && ARM
160
+ default y
161
+ depends on TCG && ARM
162
select ADS7846 # touch-screen controller
163
select MAX111X # A/D converter
164
select WM8750 # audio codec
165
@@ -XXX,XX +XXX,XX @@ config SPITZ
166
167
config Z2
168
bool
169
- default y if TCG && ARM
170
+ default y
171
+ depends on TCG && ARM
172
select PFLASH_CFI01
173
select WM8750
174
select PL011 # UART
175
@@ -XXX,XX +XXX,XX @@ config Z2
176
177
config REALVIEW
178
bool
179
- default y if TCG && ARM
180
+ default y
181
+ depends on TCG && ARM
182
imply PCI_DEVICES
183
imply PCI_TESTDEV
184
imply I2C_DEVICES
185
@@ -XXX,XX +XXX,XX @@ config REALVIEW
186
187
config SBSA_REF
188
bool
189
- default y if TCG && AARCH64
190
+ default y
191
+ depends on TCG && AARCH64
192
imply PCI_DEVICES
193
select AHCI
194
select ARM_SMMUV3
195
@@ -XXX,XX +XXX,XX @@ config SBSA_REF
196
197
config SABRELITE
198
bool
199
- default y if TCG && ARM
200
+ default y
201
+ depends on TCG && ARM
202
select FSL_IMX6
203
select SSI_M25P80
204
205
config STELLARIS
206
bool
207
- default y if TCG && ARM
208
+ default y
209
+ depends on TCG && ARM
210
imply I2C_DEVICES
211
select ARM_V7M
212
select CMSDK_APB_WATCHDOG
213
@@ -XXX,XX +XXX,XX @@ config STELLARIS
214
215
config STM32VLDISCOVERY
216
bool
217
- default y if TCG && ARM
218
+ default y
219
+ depends on TCG && ARM
220
select STM32F100_SOC
221
222
config STRONGARM
223
@@ -XXX,XX +XXX,XX @@ config STRONGARM
224
225
config COLLIE
226
bool
227
- default y if TCG && ARM
228
+ default y
229
+ depends on TCG && ARM
230
select PFLASH_CFI01
231
select ZAURUS # scoop
232
select STRONGARM
233
234
config SX1
235
bool
236
- default y if TCG && ARM
237
+ default y
238
+ depends on TCG && ARM
239
select OMAP
240
241
config VERSATILE
242
bool
243
- default y if TCG && ARM
244
+ default y
245
+ depends on TCG && ARM
246
select ARM_TIMER # sp804
247
select PFLASH_CFI01
248
select LSI_SCSI_PCI
249
@@ -XXX,XX +XXX,XX @@ config VERSATILE
250
251
config VEXPRESS
252
bool
253
- default y if TCG && ARM
254
+ default y
255
+ depends on TCG && ARM
256
select A9MPCORE
257
select A15MPCORE
258
select ARM_MPTIMER
259
@@ -XXX,XX +XXX,XX @@ config VEXPRESS
260
261
config ZYNQ
262
bool
263
- default y if TCG && ARM
264
+ default y
265
+ depends on TCG && ARM
266
select A9MPCORE
267
select CADENCE # UART
268
select PFLASH_CFI02
269
@@ -XXX,XX +XXX,XX @@ config ZYNQ
270
config ARM_V7M
271
bool
272
# currently v7M must be included in a TCG build due to translate.c
273
- default y if TCG && ARM
274
+ default y
275
+ depends on TCG && ARM
276
select PTIMER
277
278
config ALLWINNER_A10
279
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
280
281
config ALLWINNER_H3
282
bool
283
- default y if TCG && ARM
284
+ default y
285
+ depends on TCG && ARM
286
select ALLWINNER_A10_PIT
287
select ALLWINNER_SUN8I_EMAC
288
select ALLWINNER_I2C
289
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
290
291
config RASPI
292
bool
293
- default y if TCG && ARM
294
+ default y
295
+ depends on TCG && ARM
296
select FRAMEBUFFER
297
select PL011 # UART
298
select SDHCI
299
@@ -XXX,XX +XXX,XX @@ config STM32F405_SOC
300
301
config XLNX_ZYNQMP_ARM
302
bool
303
- default y if TCG && AARCH64
304
+ default y
305
+ depends on TCG && AARCH64
306
select AHCI
307
select ARM_GIC
308
select CADENCE
309
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM
310
311
config XLNX_VERSAL
312
bool
313
- default y if TCG && AARCH64
314
+ default y
315
+ depends on TCG && AARCH64
316
select ARM_GIC
317
select PL011
318
select CADENCE
319
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
320
321
config NPCM7XX
322
bool
323
- default y if TCG && ARM
324
+ default y
325
+ depends on TCG && ARM
326
select A9MPCORE
327
select ADM1272
328
select ARM_GIC
329
@@ -XXX,XX +XXX,XX @@ config NPCM7XX
330
331
config FSL_IMX25
332
bool
333
- default y if TCG && ARM
334
+ default y
335
+ depends on TCG && ARM
336
imply I2C_DEVICES
337
select IMX
338
select IMX_FEC
339
@@ -XXX,XX +XXX,XX @@ config FSL_IMX25
340
341
config FSL_IMX31
342
bool
343
- default y if TCG && ARM
344
+ default y
345
+ depends on TCG && ARM
346
imply I2C_DEVICES
347
select SERIAL
348
select IMX
349
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
350
351
config ASPEED_SOC
352
bool
353
- default y if TCG && ARM
354
+ default y
355
+ depends on TCG && ARM
356
select DS1338
357
select FTGMAC100
358
select I2C
359
@@ -XXX,XX +XXX,XX @@ config ASPEED_SOC
360
361
config MPS2
362
bool
363
- default y if TCG && ARM
364
+ default y
365
+ depends on TCG && ARM
366
imply I2C_DEVICES
367
select ARMSSE
368
select LAN9118
369
@@ -XXX,XX +XXX,XX @@ config MPS2
370
371
config FSL_IMX7
372
bool
373
- default y if TCG && ARM
374
+ default y
375
+ depends on TCG && ARM
376
imply PCI_DEVICES
377
imply TEST_DEVICES
378
imply I2C_DEVICES
379
@@ -XXX,XX +XXX,XX @@ config ARM_SMMUV3
380
381
config FSL_IMX6UL
382
bool
383
- default y if TCG && ARM
384
+ default y
385
+ depends on TCG && ARM
386
imply I2C_DEVICES
387
select A15MPCORE
388
select IMX
389
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6UL
390
391
config MICROBIT
392
bool
393
- default y if TCG && ARM
394
+ default y
395
+ depends on TCG && ARM
396
select NRF51_SOC
397
398
config NRF51_SOC
399
@@ -XXX,XX +XXX,XX @@ config NRF51_SOC
400
401
config EMCRAFT_SF2
402
bool
403
- default y if TCG && ARM
404
+ default y
405
+ depends on TCG && ARM
406
select MSF2
407
select SSI_M25P80
73
408
74
--
409
--
75
2.19.1
410
2.34.1
76
411
77
412
diff view generated by jsdifflib
[Qemu-devel] [PULL 36/45] target/arm: Use gvec for NEON_3R_VML
[PULL 19/21] Update copyright dates to 2023
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Enze Li <lienze@kylinos.cn>
2
2
3
Move mla_op and mls_op expanders from translate-a64.c.
3
I noticed that in the latest version, the copyright string is still
4
2022, even though 2023 is halfway through. This patch fixes that and
5
fixes the documentation along with it.
4
6
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Enze Li <lienze@kylinos.cn>
6
Message-id: 20181011205206.3552-16-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20230525064345.1152801-1-lienze@kylinos.cn
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/translate.h | 2 +
12
docs/conf.py | 2 +-
11
target/arm/translate-a64.c | 106 -----------------------------
13
include/qemu/help-texts.h | 2 +-
12
target/arm/translate.c | 134 ++++++++++++++++++++++++++++++++-----
14
2 files changed, 2 insertions(+), 2 deletions(-)
13
3 files changed, 120 insertions(+), 122 deletions(-)
14
15
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
16
diff --git a/docs/conf.py b/docs/conf.py
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
18
--- a/docs/conf.py
18
+++ b/target/arm/translate.h
19
+++ b/docs/conf.py
19
@@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 get_ahp_flag(void)
20
@@ -XXX,XX +XXX,XX @@
20
extern const GVecGen3 bsl_op;
21
21
extern const GVecGen3 bit_op;
22
# General information about the project.
22
extern const GVecGen3 bif_op;
23
project = u'QEMU'
23
+extern const GVecGen3 mla_op[4];
24
-copyright = u'2022, The QEMU Project Developers'
24
+extern const GVecGen3 mls_op[4];
25
+copyright = u'2023, The QEMU Project Developers'
25
extern const GVecGen2i ssra_op[4];
26
author = u'The QEMU Project Developers'
26
extern const GVecGen2i usra_op[4];
27
27
extern const GVecGen2i sri_op[4];
28
# The version info for the project you're documenting, acts as replacement for
28
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
diff --git a/include/qemu/help-texts.h b/include/qemu/help-texts.h
29
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/translate-a64.c
31
--- a/include/qemu/help-texts.h
31
+++ b/target/arm/translate-a64.c
32
+++ b/include/qemu/help-texts.h
32
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
33
@@ -XXX,XX +XXX,XX @@
33
}
34
#define QEMU_HELP_TEXTS_H
34
}
35
35
36
/* Copyright string for -version arguments, About dialogs, etc */
36
-static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
37
-#define QEMU_COPYRIGHT "Copyright (c) 2003-2022 " \
37
-{
38
+#define QEMU_COPYRIGHT "Copyright (c) 2003-2023 " \
38
- gen_helper_neon_mul_u8(a, a, b);
39
"Fabrice Bellard and the QEMU Project developers"
39
- gen_helper_neon_add_u8(d, d, a);
40
40
-}
41
/* Bug reporting information for --help arguments, About dialogs, etc */
41
-
42
-static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
43
-{
44
- gen_helper_neon_mul_u16(a, a, b);
45
- gen_helper_neon_add_u16(d, d, a);
46
-}
47
-
48
-static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
49
-{
50
- tcg_gen_mul_i32(a, a, b);
51
- tcg_gen_add_i32(d, d, a);
52
-}
53
-
54
-static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
55
-{
56
- tcg_gen_mul_i64(a, a, b);
57
- tcg_gen_add_i64(d, d, a);
58
-}
59
-
60
-static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
61
-{
62
- tcg_gen_mul_vec(vece, a, a, b);
63
- tcg_gen_add_vec(vece, d, d, a);
64
-}
65
-
66
-static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
67
-{
68
- gen_helper_neon_mul_u8(a, a, b);
69
- gen_helper_neon_sub_u8(d, d, a);
70
-}
71
-
72
-static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
73
-{
74
- gen_helper_neon_mul_u16(a, a, b);
75
- gen_helper_neon_sub_u16(d, d, a);
76
-}
77
-
78
-static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
79
-{
80
- tcg_gen_mul_i32(a, a, b);
81
- tcg_gen_sub_i32(d, d, a);
82
-}
83
-
84
-static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
85
-{
86
- tcg_gen_mul_i64(a, a, b);
87
- tcg_gen_sub_i64(d, d, a);
88
-}
89
-
90
-static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
91
-{
92
- tcg_gen_mul_vec(vece, a, a, b);
93
- tcg_gen_sub_vec(vece, d, d, a);
94
-}
95
-
96
/* Integer op subgroup of C3.6.16. */
97
static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
98
{
99
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
100
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
101
.vece = MO_64 },
102
};
103
- static const GVecGen3 mla_op[4] = {
104
- { .fni4 = gen_mla8_i32,
105
- .fniv = gen_mla_vec,
106
- .opc = INDEX_op_mul_vec,
107
- .load_dest = true,
108
- .vece = MO_8 },
109
- { .fni4 = gen_mla16_i32,
110
- .fniv = gen_mla_vec,
111
- .opc = INDEX_op_mul_vec,
112
- .load_dest = true,
113
- .vece = MO_16 },
114
- { .fni4 = gen_mla32_i32,
115
- .fniv = gen_mla_vec,
116
- .opc = INDEX_op_mul_vec,
117
- .load_dest = true,
118
- .vece = MO_32 },
119
- { .fni8 = gen_mla64_i64,
120
- .fniv = gen_mla_vec,
121
- .opc = INDEX_op_mul_vec,
122
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
123
- .load_dest = true,
124
- .vece = MO_64 },
125
- };
126
- static const GVecGen3 mls_op[4] = {
127
- { .fni4 = gen_mls8_i32,
128
- .fniv = gen_mls_vec,
129
- .opc = INDEX_op_mul_vec,
130
- .load_dest = true,
131
- .vece = MO_8 },
132
- { .fni4 = gen_mls16_i32,
133
- .fniv = gen_mls_vec,
134
- .opc = INDEX_op_mul_vec,
135
- .load_dest = true,
136
- .vece = MO_16 },
137
- { .fni4 = gen_mls32_i32,
138
- .fniv = gen_mls_vec,
139
- .opc = INDEX_op_mul_vec,
140
- .load_dest = true,
141
- .vece = MO_32 },
142
- { .fni8 = gen_mls64_i64,
143
- .fniv = gen_mls_vec,
144
- .opc = INDEX_op_mul_vec,
145
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
146
- .load_dest = true,
147
- .vece = MO_64 },
148
- };
149
150
int is_q = extract32(insn, 30, 1);
151
int u = extract32(insn, 29, 1);
152
diff --git a/target/arm/translate.c b/target/arm/translate.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/target/arm/translate.c
155
+++ b/target/arm/translate.c
156
@@ -XXX,XX +XXX,XX @@ static void gen_neon_narrow_op(int op, int u, int size,
157
#define NEON_3R_VABA 15
158
#define NEON_3R_VADD_VSUB 16
159
#define NEON_3R_VTST_VCEQ 17
160
-#define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */
161
+#define NEON_3R_VML 18 /* VMLA, VMLS */
162
#define NEON_3R_VMUL 19
163
#define NEON_3R_VPMAX 20
164
#define NEON_3R_VPMIN 21
165
@@ -XXX,XX +XXX,XX @@ const GVecGen2i sli_op[4] = {
166
.vece = MO_64 },
167
};
168
169
+static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
170
+{
171
+ gen_helper_neon_mul_u8(a, a, b);
172
+ gen_helper_neon_add_u8(d, d, a);
173
+}
174
+
175
+static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
176
+{
177
+ gen_helper_neon_mul_u8(a, a, b);
178
+ gen_helper_neon_sub_u8(d, d, a);
179
+}
180
+
181
+static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
182
+{
183
+ gen_helper_neon_mul_u16(a, a, b);
184
+ gen_helper_neon_add_u16(d, d, a);
185
+}
186
+
187
+static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
188
+{
189
+ gen_helper_neon_mul_u16(a, a, b);
190
+ gen_helper_neon_sub_u16(d, d, a);
191
+}
192
+
193
+static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
194
+{
195
+ tcg_gen_mul_i32(a, a, b);
196
+ tcg_gen_add_i32(d, d, a);
197
+}
198
+
199
+static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
200
+{
201
+ tcg_gen_mul_i32(a, a, b);
202
+ tcg_gen_sub_i32(d, d, a);
203
+}
204
+
205
+static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
206
+{
207
+ tcg_gen_mul_i64(a, a, b);
208
+ tcg_gen_add_i64(d, d, a);
209
+}
210
+
211
+static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
212
+{
213
+ tcg_gen_mul_i64(a, a, b);
214
+ tcg_gen_sub_i64(d, d, a);
215
+}
216
+
217
+static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
218
+{
219
+ tcg_gen_mul_vec(vece, a, a, b);
220
+ tcg_gen_add_vec(vece, d, d, a);
221
+}
222
+
223
+static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
224
+{
225
+ tcg_gen_mul_vec(vece, a, a, b);
226
+ tcg_gen_sub_vec(vece, d, d, a);
227
+}
228
+
229
+/* Note that while NEON does not support VMLA and VMLS as 64-bit ops,
230
+ * these tables are shared with AArch64 which does support them.
231
+ */
232
+const GVecGen3 mla_op[4] = {
233
+ { .fni4 = gen_mla8_i32,
234
+ .fniv = gen_mla_vec,
235
+ .opc = INDEX_op_mul_vec,
236
+ .load_dest = true,
237
+ .vece = MO_8 },
238
+ { .fni4 = gen_mla16_i32,
239
+ .fniv = gen_mla_vec,
240
+ .opc = INDEX_op_mul_vec,
241
+ .load_dest = true,
242
+ .vece = MO_16 },
243
+ { .fni4 = gen_mla32_i32,
244
+ .fniv = gen_mla_vec,
245
+ .opc = INDEX_op_mul_vec,
246
+ .load_dest = true,
247
+ .vece = MO_32 },
248
+ { .fni8 = gen_mla64_i64,
249
+ .fniv = gen_mla_vec,
250
+ .opc = INDEX_op_mul_vec,
251
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
252
+ .load_dest = true,
253
+ .vece = MO_64 },
254
+};
255
+
256
+const GVecGen3 mls_op[4] = {
257
+ { .fni4 = gen_mls8_i32,
258
+ .fniv = gen_mls_vec,
259
+ .opc = INDEX_op_mul_vec,
260
+ .load_dest = true,
261
+ .vece = MO_8 },
262
+ { .fni4 = gen_mls16_i32,
263
+ .fniv = gen_mls_vec,
264
+ .opc = INDEX_op_mul_vec,
265
+ .load_dest = true,
266
+ .vece = MO_16 },
267
+ { .fni4 = gen_mls32_i32,
268
+ .fniv = gen_mls_vec,
269
+ .opc = INDEX_op_mul_vec,
270
+ .load_dest = true,
271
+ .vece = MO_32 },
272
+ { .fni8 = gen_mls64_i64,
273
+ .fniv = gen_mls_vec,
274
+ .opc = INDEX_op_mul_vec,
275
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
276
+ .load_dest = true,
277
+ .vece = MO_64 },
278
+};
279
+
280
/* Translate a NEON data processing instruction. Return nonzero if the
281
instruction is invalid.
282
We process data in a mixture of 32-bit and 64-bit chunks.
283
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
284
return 0;
285
}
286
break;
287
+
288
+ case NEON_3R_VML: /* VMLA, VMLS */
289
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
290
+ u ? &mls_op[size] : &mla_op[size]);
291
+ return 0;
292
}
293
+
294
if (size == 3) {
295
/* 64-bit element instructions. */
296
for (pass = 0; pass < (q ? 2 : 1); pass++) {
297
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
298
}
299
}
300
break;
301
- case NEON_3R_VML: /* VMLA, VMLAL, VMLS,VMLSL */
302
- switch (size) {
303
- case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
304
- case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
305
- case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
306
- default: abort();
307
- }
308
- tcg_temp_free_i32(tmp2);
309
- tmp2 = neon_load_reg(rd, pass);
310
- if (u) { /* VMLS */
311
- gen_neon_rsb(size, tmp, tmp2);
312
- } else { /* VMLA */
313
- gen_neon_add(size, tmp, tmp2);
314
- }
315
- break;
316
case NEON_3R_VMUL:
317
/* VMUL.P8; other cases already eliminated. */
318
gen_helper_neon_mul_p8(tmp, tmp, tmp2);
319
--
42
--
320
2.19.1
43
2.34.1
321
322
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/45] target/arm: Convert t32ee from feature bit to isar3 test
[PULL 20/21] hw/arm/sbsa-ref: add GIC node into DT
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
Let add GIC information into DeviceTree as part of SBSA-REF versioning.
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
5
Message-id: 20181016223115.24100-7-richard.henderson@linaro.org
5
Trusted Firmware will read it and provide to next firmware level.
6
7
Bumps platform version to 0.1 one so we can check is node is present.
8
9
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
12
---
9
target/arm/cpu.h | 6 +++++-
13
hw/arm/sbsa-ref.c | 19 ++++++++++++++++++-
10
linux-user/elfload.c | 2 +-
14
1 file changed, 18 insertions(+), 1 deletion(-)
11
target/arm/cpu.c | 4 ----
12
target/arm/helper.c | 2 +-
13
target/arm/machine.c | 3 +--
14
5 files changed, 8 insertions(+), 9 deletions(-)
15
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
18
--- a/hw/arm/sbsa-ref.c
19
+++ b/target/arm/cpu.h
19
+++ b/hw/arm/sbsa-ref.c
20
@@ -XXX,XX +XXX,XX @@ enum arm_features {
20
@@ -XXX,XX +XXX,XX @@
21
ARM_FEATURE_NEON,
21
#include "exec/hwaddr.h"
22
ARM_FEATURE_M, /* Microcontroller profile. */
22
#include "kvm_arm.h"
23
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
23
#include "hw/arm/boot.h"
24
- ARM_FEATURE_THUMB2EE,
24
+#include "hw/arm/fdt.h"
25
ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
25
#include "hw/arm/smmuv3.h"
26
ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
26
#include "hw/block/flash.h"
27
ARM_FEATURE_V4T,
27
#include "hw/boards.h"
28
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_jazelle(const ARMISARegisters *id)
28
@@ -XXX,XX +XXX,XX @@ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
29
return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
29
return arm_cpu_mp_affinity(idx, clustersz);
30
}
30
}
31
31
32
+static inline bool isar_feature_t32ee(const ARMISARegisters *id)
32
+static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)
33
+{
33
+{
34
+ return FIELD_EX32(id->id_isar3, ID_ISAR3, T32EE) != 0;
34
+ char *nodename;
35
+
36
+ nodename = g_strdup_printf("/intc");
37
+ qemu_fdt_add_subnode(sms->fdt, nodename);
38
+ qemu_fdt_setprop_sized_cells(sms->fdt, nodename, "reg",
39
+ 2, sbsa_ref_memmap[SBSA_GIC_DIST].base,
40
+ 2, sbsa_ref_memmap[SBSA_GIC_DIST].size,
41
+ 2, sbsa_ref_memmap[SBSA_GIC_REDIST].base,
42
+ 2, sbsa_ref_memmap[SBSA_GIC_REDIST].size);
43
+
44
+ g_free(nodename);
35
+}
45
+}
46
/*
47
* Firmware on this machine only uses ACPI table to load OS, these limited
48
* device tree nodes are just to let firmware know the info which varies from
49
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
50
* fw compatibility.
51
*/
52
qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
53
- qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
54
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 1);
55
56
if (ms->numa_state->have_numa_distance) {
57
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
58
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
59
60
g_free(nodename);
61
}
36
+
62
+
37
static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
63
+ sbsa_fdt_add_gic_node(sms);
38
{
39
return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
40
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/linux-user/elfload.c
43
+++ b/linux-user/elfload.c
44
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
45
GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
46
GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP);
47
GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
48
- GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
49
+ GET_FEATURE_ID(t32ee, ARM_HWCAP_ARM_THUMBEE);
50
GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
51
GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3);
52
GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
53
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/arm/cpu.c
56
+++ b/target/arm/cpu.c
57
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
58
set_feature(&cpu->env, ARM_FEATURE_V7);
59
set_feature(&cpu->env, ARM_FEATURE_VFP3);
60
set_feature(&cpu->env, ARM_FEATURE_NEON);
61
- set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
62
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
63
set_feature(&cpu->env, ARM_FEATURE_EL3);
64
cpu->midr = 0x410fc080;
65
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
66
set_feature(&cpu->env, ARM_FEATURE_VFP3);
67
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
68
set_feature(&cpu->env, ARM_FEATURE_NEON);
69
- set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
70
set_feature(&cpu->env, ARM_FEATURE_EL3);
71
/* Note that A9 supports the MP extensions even for
72
* A9UP and single-core A9MP (which are both different
73
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
74
set_feature(&cpu->env, ARM_FEATURE_V7VE);
75
set_feature(&cpu->env, ARM_FEATURE_VFP4);
76
set_feature(&cpu->env, ARM_FEATURE_NEON);
77
- set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
78
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
79
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
80
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
81
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
82
set_feature(&cpu->env, ARM_FEATURE_V7VE);
83
set_feature(&cpu->env, ARM_FEATURE_VFP4);
84
set_feature(&cpu->env, ARM_FEATURE_NEON);
85
- set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
86
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
87
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
88
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
89
diff --git a/target/arm/helper.c b/target/arm/helper.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/helper.c
92
+++ b/target/arm/helper.c
93
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
94
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
95
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
96
}
97
- if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
98
+ if (cpu_isar_feature(t32ee, cpu)) {
99
define_arm_cp_regs(cpu, t2ee_cp_reginfo);
100
}
101
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
102
diff --git a/target/arm/machine.c b/target/arm/machine.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/machine.c
105
+++ b/target/arm/machine.c
106
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = {
107
static bool thumb2ee_needed(void *opaque)
108
{
109
ARMCPU *cpu = opaque;
110
- CPUARMState *env = &cpu->env;
111
112
- return arm_feature(env, ARM_FEATURE_THUMB2EE);
113
+ return cpu_isar_feature(t32ee, cpu);
114
}
64
}
115
65
116
static const VMStateDescription vmstate_thumb2ee = {
66
#define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
117
--
67
--
118
2.19.1
68
2.34.1
119
120
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/45] target/arm: Make switch_mode() file-local
Deleted patch
1
The switch_mode() function is defined in target/arm/helper.c and used
2
only in that file and nowhere else, so we can make it file-local
3
rather than global.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20181012144235.19646-3-peter.maydell@linaro.org
8
---
9
target/arm/internals.h | 1 -
10
target/arm/helper.c | 6 ++++--
11
2 files changed, 4 insertions(+), 3 deletions(-)
12
13
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/internals.h
16
+++ b/target/arm/internals.h
17
@@ -XXX,XX +XXX,XX @@ static inline int bank_number(int mode)
18
g_assert_not_reached();
19
}
20
21
-void switch_mode(CPUARMState *, int);
22
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
23
void arm_translate_init(void);
24
25
diff --git a/target/arm/helper.c b/target/arm/helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/helper.c
28
+++ b/target/arm/helper.c
29
@@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address,
30
V8M_SAttributes *sattrs);
31
#endif
32
33
+static void switch_mode(CPUARMState *env, int mode);
34
+
35
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
36
{
37
int nregs;
38
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
39
return 0;
40
}
41
42
-void switch_mode(CPUARMState *env, int mode)
43
+static void switch_mode(CPUARMState *env, int mode)
44
{
45
ARMCPU *cpu = arm_env_get_cpu(env);
46
47
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
48
49
#else
50
51
-void switch_mode(CPUARMState *env, int mode)
52
+static void switch_mode(CPUARMState *env, int mode)
53
{
54
int old_mode;
55
int i;
56
--
57
2.19.1
58
59
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/45] target/arm: Implement HCR.FB
Deleted patch
1
The HCR.FB virtualization configuration register bit requests that
2
TLB maintenance, branch predictor invalidate-all and icache
3
invalidate-all operations performed in NS EL1 should be upgraded
4
from "local CPU only to "broadcast within Inner Shareable domain".
5
For QEMU we NOP the branch predictor and icache operations, so
6
we only need to upgrade the TLB invalidates:
7
AArch32 TLBIALL, TLBIMVA, TLBIASID, DTLBIALL, DTLBIMVA, DTLBIASID,
8
ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA, TLBIMVAL, TLBIMVAAL
9
AArch64 TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
10
TLBI VALE1, TLBI VAALE1
11
1
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20181012144235.19646-4-peter.maydell@linaro.org
15
---
16
target/arm/helper.c | 191 +++++++++++++++++++++++++++-----------------
17
1 file changed, 116 insertions(+), 75 deletions(-)
18
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
22
+++ b/target/arm/helper.c
23
@@ -XXX,XX +XXX,XX @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
24
raw_write(env, ri, value);
25
}
26
27
-static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
28
- uint64_t value)
29
-{
30
- /* Invalidate all (TLBIALL) */
31
- ARMCPU *cpu = arm_env_get_cpu(env);
32
-
33
- tlb_flush(CPU(cpu));
34
-}
35
-
36
-static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
37
- uint64_t value)
38
-{
39
- /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
40
- ARMCPU *cpu = arm_env_get_cpu(env);
41
-
42
- tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
43
-}
44
-
45
-static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
46
- uint64_t value)
47
-{
48
- /* Invalidate by ASID (TLBIASID) */
49
- ARMCPU *cpu = arm_env_get_cpu(env);
50
-
51
- tlb_flush(CPU(cpu));
52
-}
53
-
54
-static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
55
- uint64_t value)
56
-{
57
- /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
58
- ARMCPU *cpu = arm_env_get_cpu(env);
59
-
60
- tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
61
-}
62
-
63
/* IS variants of TLB operations must affect all cores */
64
static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
65
uint64_t value)
66
@@ -XXX,XX +XXX,XX @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
67
tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
68
}
69
70
+/*
71
+ * Non-IS variants of TLB operations are upgraded to
72
+ * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
73
+ * force broadcast of these operations.
74
+ */
75
+static bool tlb_force_broadcast(CPUARMState *env)
76
+{
77
+ return (env->cp15.hcr_el2 & HCR_FB) &&
78
+ arm_current_el(env) == 1 && arm_is_secure_below_el3(env);
79
+}
80
+
81
+static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
82
+ uint64_t value)
83
+{
84
+ /* Invalidate all (TLBIALL) */
85
+ ARMCPU *cpu = arm_env_get_cpu(env);
86
+
87
+ if (tlb_force_broadcast(env)) {
88
+ tlbiall_is_write(env, NULL, value);
89
+ return;
90
+ }
91
+
92
+ tlb_flush(CPU(cpu));
93
+}
94
+
95
+static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
96
+ uint64_t value)
97
+{
98
+ /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
99
+ ARMCPU *cpu = arm_env_get_cpu(env);
100
+
101
+ if (tlb_force_broadcast(env)) {
102
+ tlbimva_is_write(env, NULL, value);
103
+ return;
104
+ }
105
+
106
+ tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
107
+}
108
+
109
+static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
110
+ uint64_t value)
111
+{
112
+ /* Invalidate by ASID (TLBIASID) */
113
+ ARMCPU *cpu = arm_env_get_cpu(env);
114
+
115
+ if (tlb_force_broadcast(env)) {
116
+ tlbiasid_is_write(env, NULL, value);
117
+ return;
118
+ }
119
+
120
+ tlb_flush(CPU(cpu));
121
+}
122
+
123
+static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
124
+ uint64_t value)
125
+{
126
+ /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
127
+ ARMCPU *cpu = arm_env_get_cpu(env);
128
+
129
+ if (tlb_force_broadcast(env)) {
130
+ tlbimvaa_is_write(env, NULL, value);
131
+ return;
132
+ }
133
+
134
+ tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
135
+}
136
+
137
static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
138
uint64_t value)
139
{
140
@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
141
* Page D4-1736 (DDI0487A.b)
142
*/
143
144
-static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
145
- uint64_t value)
146
-{
147
- CPUState *cs = ENV_GET_CPU(env);
148
-
149
- if (arm_is_secure_below_el3(env)) {
150
- tlb_flush_by_mmuidx(cs,
151
- ARMMMUIdxBit_S1SE1 |
152
- ARMMMUIdxBit_S1SE0);
153
- } else {
154
- tlb_flush_by_mmuidx(cs,
155
- ARMMMUIdxBit_S12NSE1 |
156
- ARMMMUIdxBit_S12NSE0);
157
- }
158
-}
159
-
160
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
161
uint64_t value)
162
{
163
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
164
}
165
}
166
167
+static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
168
+ uint64_t value)
169
+{
170
+ CPUState *cs = ENV_GET_CPU(env);
171
+
172
+ if (tlb_force_broadcast(env)) {
173
+ tlbi_aa64_vmalle1_write(env, NULL, value);
174
+ return;
175
+ }
176
+
177
+ if (arm_is_secure_below_el3(env)) {
178
+ tlb_flush_by_mmuidx(cs,
179
+ ARMMMUIdxBit_S1SE1 |
180
+ ARMMMUIdxBit_S1SE0);
181
+ } else {
182
+ tlb_flush_by_mmuidx(cs,
183
+ ARMMMUIdxBit_S12NSE1 |
184
+ ARMMMUIdxBit_S12NSE0);
185
+ }
186
+}
187
+
188
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
189
uint64_t value)
190
{
191
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
192
tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
193
}
194
195
-static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
196
- uint64_t value)
197
-{
198
- /* Invalidate by VA, EL1&0 (AArch64 version).
199
- * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
200
- * since we don't support flush-for-specific-ASID-only or
201
- * flush-last-level-only.
202
- */
203
- ARMCPU *cpu = arm_env_get_cpu(env);
204
- CPUState *cs = CPU(cpu);
205
- uint64_t pageaddr = sextract64(value << 12, 0, 56);
206
-
207
- if (arm_is_secure_below_el3(env)) {
208
- tlb_flush_page_by_mmuidx(cs, pageaddr,
209
- ARMMMUIdxBit_S1SE1 |
210
- ARMMMUIdxBit_S1SE0);
211
- } else {
212
- tlb_flush_page_by_mmuidx(cs, pageaddr,
213
- ARMMMUIdxBit_S12NSE1 |
214
- ARMMMUIdxBit_S12NSE0);
215
- }
216
-}
217
-
218
static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
219
uint64_t value)
220
{
221
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
222
}
223
}
224
225
+static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
226
+ uint64_t value)
227
+{
228
+ /* Invalidate by VA, EL1&0 (AArch64 version).
229
+ * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
230
+ * since we don't support flush-for-specific-ASID-only or
231
+ * flush-last-level-only.
232
+ */
233
+ ARMCPU *cpu = arm_env_get_cpu(env);
234
+ CPUState *cs = CPU(cpu);
235
+ uint64_t pageaddr = sextract64(value << 12, 0, 56);
236
+
237
+ if (tlb_force_broadcast(env)) {
238
+ tlbi_aa64_vae1is_write(env, NULL, value);
239
+ return;
240
+ }
241
+
242
+ if (arm_is_secure_below_el3(env)) {
243
+ tlb_flush_page_by_mmuidx(cs, pageaddr,
244
+ ARMMMUIdxBit_S1SE1 |
245
+ ARMMMUIdxBit_S1SE0);
246
+ } else {
247
+ tlb_flush_page_by_mmuidx(cs, pageaddr,
248
+ ARMMMUIdxBit_S12NSE1 |
249
+ ARMMMUIdxBit_S12NSE0);
250
+ }
251
+}
252
+
253
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
254
uint64_t value)
255
{
256
--
257
2.19.1
258
259
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/45] target/arm: Implement HCR.DC
Deleted patch
1
The HCR.DC virtualization configuration register bit has the
2
following effects:
3
* SCTLR.M behaves as if it is 0 for all purposes except
4
direct reads of the bit
5
* HCR.VM behaves as if it is 1 for all purposes except
6
direct reads of the bit
7
* the memory type produced by the first stage of the EL1&EL0
8
translation regime is Normal Non-Shareable,
9
Inner Write-Back Read-Allocate Write-Allocate,
10
Outer Write-Back Read-Allocate Write-Allocate.
11
1
12
Implement this behaviour.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20181012144235.19646-5-peter.maydell@linaro.org
17
---
18
target/arm/helper.c | 23 +++++++++++++++++++++--
19
1 file changed, 21 insertions(+), 2 deletions(-)
20
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
24
+++ b/target/arm/helper.c
25
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
26
* * The Non-secure TTBCR.EAE bit is set to 1
27
* * The implementation includes EL2, and the value of HCR.VM is 1
28
*
29
+ * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
30
+ *
31
* ATS1Hx always uses the 64bit format (not supported yet).
32
*/
33
format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
34
35
if (arm_feature(env, ARM_FEATURE_EL2)) {
36
if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
37
- format64 |= env->cp15.hcr_el2 & HCR_VM;
38
+ format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
39
} else {
40
format64 |= arm_current_el(env) == 2;
41
}
42
@@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_disabled(CPUARMState *env,
43
}
44
45
if (mmu_idx == ARMMMUIdx_S2NS) {
46
- return (env->cp15.hcr_el2 & HCR_VM) == 0;
47
+ /* HCR.DC means HCR.VM behaves as 1 */
48
+ return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0;
49
}
50
51
if (env->cp15.hcr_el2 & HCR_TGE) {
52
@@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_disabled(CPUARMState *env,
53
}
54
}
55
56
+ if ((env->cp15.hcr_el2 & HCR_DC) &&
57
+ (mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) {
58
+ /* HCR.DC means SCTLR_EL1.M behaves as 0 */
59
+ return true;
60
+ }
61
+
62
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
63
}
64
65
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
66
67
/* Combine the S1 and S2 cache attributes, if needed */
68
if (!ret && cacheattrs != NULL) {
69
+ if (env->cp15.hcr_el2 & HCR_DC) {
70
+ /*
71
+ * HCR.DC forces the first stage attributes to
72
+ * Normal Non-Shareable,
73
+ * Inner Write-Back Read-Allocate Write-Allocate,
74
+ * Outer Write-Back Read-Allocate Write-Allocate.
75
+ */
76
+ cacheattrs->attrs = 0xff;
77
+ cacheattrs->shareability = 0;
78
+ }
79
*cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
80
}
81
82
--
83
2.19.1
84
85
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/45] target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set
Deleted patch
1
The A/I/F bits in ISR_EL1 should track the virtual interrupt
2
status, not the physical interrupt status, if the associated
3
HCR_EL2.AMO/IMO/FMO bit is set. Implement this, rather than
4
always showing the physical interrupt status.
5
1
6
We don't currently implement anything to do with external
7
aborts, so this applies only to the I and F bits (though it
8
ought to be possible for the outer guest to present a virtual
9
external abort to the inner guest, even if QEMU doesn't
10
emulate physical external aborts, so there is missing
11
functionality in this area).
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20181012144235.19646-6-peter.maydell@linaro.org
16
---
17
target/arm/helper.c | 22 ++++++++++++++++++----
18
1 file changed, 18 insertions(+), 4 deletions(-)
19
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
23
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
25
CPUState *cs = ENV_GET_CPU(env);
26
uint64_t ret = 0;
27
28
- if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
29
- ret |= CPSR_I;
30
+ if (arm_hcr_el2_imo(env)) {
31
+ if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
32
+ ret |= CPSR_I;
33
+ }
34
+ } else {
35
+ if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
36
+ ret |= CPSR_I;
37
+ }
38
}
39
- if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
40
- ret |= CPSR_F;
41
+
42
+ if (arm_hcr_el2_fmo(env)) {
43
+ if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
44
+ ret |= CPSR_F;
45
+ }
46
+ } else {
47
+ if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
48
+ ret |= CPSR_F;
49
+ }
50
}
51
+
52
/* External aborts are not possible in QEMU so A bit is always clear */
53
return ret;
54
}
55
--
56
2.19.1
57
58
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/45] target/arm: Implement HCR.VI and VF
Deleted patch
1
The HCR_EL2 VI and VF bits are supposed to track whether there is
2
a pending virtual IRQ or virtual FIQ. For QEMU we store the
3
pending VIRQ/VFIQ status in cs->interrupt_request, so this means:
4
* if the register is read we must get these bit values from
5
cs->interrupt_request
6
* if the register is written then we must write the bit
7
values back into cs->interrupt_request
8
1
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20181012144235.19646-7-peter.maydell@linaro.org
12
---
13
target/arm/helper.c | 47 +++++++++++++++++++++++++++++++++++++++++----
14
1 file changed, 43 insertions(+), 4 deletions(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
21
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
22
{
23
ARMCPU *cpu = arm_env_get_cpu(env);
24
+ CPUState *cs = ENV_GET_CPU(env);
25
uint64_t valid_mask = HCR_MASK;
26
27
if (arm_feature(env, ARM_FEATURE_EL3)) {
28
@@ -XXX,XX +XXX,XX @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
29
/* Clear RES0 bits. */
30
value &= valid_mask;
31
32
+ /*
33
+ * VI and VF are kept in cs->interrupt_request. Modifying that
34
+ * requires that we have the iothread lock, which is done by
35
+ * marking the reginfo structs as ARM_CP_IO.
36
+ * Note that if a write to HCR pends a VIRQ or VFIQ it is never
37
+ * possible for it to be taken immediately, because VIRQ and
38
+ * VFIQ are masked unless running at EL0 or EL1, and HCR
39
+ * can only be written at EL2.
40
+ */
41
+ g_assert(qemu_mutex_iothread_locked());
42
+ if (value & HCR_VI) {
43
+ cs->interrupt_request |= CPU_INTERRUPT_VIRQ;
44
+ } else {
45
+ cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
46
+ }
47
+ if (value & HCR_VF) {
48
+ cs->interrupt_request |= CPU_INTERRUPT_VFIQ;
49
+ } else {
50
+ cs->interrupt_request &= ~CPU_INTERRUPT_VFIQ;
51
+ }
52
+ value &= ~(HCR_VI | HCR_VF);
53
+
54
/* These bits change the MMU setup:
55
* HCR_VM enables stage 2 translation
56
* HCR_PTW forbids certain page-table setups
57
@@ -XXX,XX +XXX,XX @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
58
hcr_write(env, NULL, value);
59
}
60
61
+static uint64_t hcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
62
+{
63
+ /* The VI and VF bits live in cs->interrupt_request */
64
+ uint64_t ret = env->cp15.hcr_el2 & ~(HCR_VI | HCR_VF);
65
+ CPUState *cs = ENV_GET_CPU(env);
66
+
67
+ if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
68
+ ret |= HCR_VI;
69
+ }
70
+ if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
71
+ ret |= HCR_VF;
72
+ }
73
+ return ret;
74
+}
75
+
76
static const ARMCPRegInfo el2_cp_reginfo[] = {
77
{ .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
78
+ .type = ARM_CP_IO,
79
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
80
.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
81
- .writefn = hcr_write },
82
+ .writefn = hcr_write, .readfn = hcr_read },
83
{ .name = "HCR", .state = ARM_CP_STATE_AA32,
84
- .type = ARM_CP_ALIAS,
85
+ .type = ARM_CP_ALIAS | ARM_CP_IO,
86
.cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
87
.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
88
- .writefn = hcr_writelow },
89
+ .writefn = hcr_writelow, .readfn = hcr_read },
90
{ .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
91
.type = ARM_CP_ALIAS,
92
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
93
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
94
95
static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
96
{ .name = "HCR2", .state = ARM_CP_STATE_AA32,
97
- .type = ARM_CP_ALIAS,
98
+ .type = ARM_CP_ALIAS | ARM_CP_IO,
99
.cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
100
.access = PL2_RW,
101
.fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
102
--
103
2.19.1
104
105
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/45] target/arm: Implement HCR.PTW
Deleted patch
1
If the HCR_EL2 PTW virtualizaiton configuration register bit
2
is set, then this means that a stage 2 Permission fault must
3
be generated if a stage 1 translation table access is made
4
to an address that is mapped as Device memory in stage 2.
5
Implement this.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20181012144235.19646-8-peter.maydell@linaro.org
10
---
11
target/arm/helper.c | 21 ++++++++++++++++++++-
12
1 file changed, 20 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
19
hwaddr s2pa;
20
int s2prot;
21
int ret;
22
+ ARMCacheAttrs cacheattrs = {};
23
+ ARMCacheAttrs *pcacheattrs = NULL;
24
+
25
+ if (env->cp15.hcr_el2 & HCR_PTW) {
26
+ /*
27
+ * PTW means we must fault if this S1 walk touches S2 Device
28
+ * memory; otherwise we don't care about the attributes and can
29
+ * save the S2 translation the effort of computing them.
30
+ */
31
+ pcacheattrs = &cacheattrs;
32
+ }
33
34
ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
35
- &txattrs, &s2prot, &s2size, fi, NULL);
36
+ &txattrs, &s2prot, &s2size, fi, pcacheattrs);
37
if (ret) {
38
assert(fi->type != ARMFault_None);
39
fi->s2addr = addr;
40
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
41
fi->s1ptw = true;
42
return ~0;
43
}
44
+ if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) {
45
+ /* Access was to Device memory: generate Permission fault */
46
+ fi->type = ARMFault_Permission;
47
+ fi->s2addr = addr;
48
+ fi->stage2 = true;
49
+ fi->s1ptw = true;
50
+ return ~0;
51
+ }
52
addr = s2pa;
53
}
54
return addr;
55
--
56
2.19.1
57
58
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/45] target/arm: New utility function to extract EC from syndrome
Deleted patch
1
Create and use a utility function to extract the EC field
2
from a syndrome, rather than open-coding the shift.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20181012144235.19646-9-peter.maydell@linaro.org
7
---
8
target/arm/internals.h | 5 +++++
9
target/arm/helper.c | 4 ++--
10
target/arm/kvm64.c | 2 +-
11
target/arm/op_helper.c | 2 +-
12
4 files changed, 9 insertions(+), 4 deletions(-)
13
14
diff --git a/target/arm/internals.h b/target/arm/internals.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/internals.h
17
+++ b/target/arm/internals.h
18
@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
19
#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
20
#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
21
22
+static inline uint32_t syn_get_ec(uint32_t syn)
23
+{
24
+ return syn >> ARM_EL_EC_SHIFT;
25
+}
26
+
27
/* Utility functions for constructing various kinds of syndrome value.
28
* Note that in general we follow the AArch64 syndrome values; in a
29
* few cases the value in HSR for exceptions taken to AArch32 Hyp
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
35
uint32_t moe;
36
37
/* If this is a debug exception we must update the DBGDSCR.MOE bits */
38
- switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
39
+ switch (syn_get_ec(env->exception.syndrome)) {
40
case EC_BREAKPOINT:
41
case EC_BREAKPOINT_SAME_EL:
42
moe = 1;
43
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
44
if (qemu_loglevel_mask(CPU_LOG_INT)
45
&& !excp_is_internal(cs->exception_index)) {
46
qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n",
47
- env->exception.syndrome >> ARM_EL_EC_SHIFT,
48
+ syn_get_ec(env->exception.syndrome),
49
env->exception.syndrome);
50
}
51
52
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/kvm64.c
55
+++ b/target/arm/kvm64.c
56
@@ -XXX,XX +XXX,XX @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
57
58
bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
59
{
60
- int hsr_ec = debug_exit->hsr >> ARM_EL_EC_SHIFT;
61
+ int hsr_ec = syn_get_ec(debug_exit->hsr);
62
ARMCPU *cpu = ARM_CPU(cs);
63
CPUClass *cc = CPU_GET_CLASS(cs);
64
CPUARMState *env = &cpu->env;
65
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/op_helper.c
68
+++ b/target/arm/op_helper.c
69
@@ -XXX,XX +XXX,XX @@ void raise_exception(CPUARMState *env, uint32_t excp,
70
* (see DDI0478C.a D1.10.4)
71
*/
72
target_el = 2;
73
- if (syndrome >> ARM_EL_EC_SHIFT == EC_ADVSIMDFPACCESSTRAP) {
74
+ if (syn_get_ec(syndrome) == EC_ADVSIMDFPACCESSTRAP) {
75
syndrome = syn_uncategorized();
76
}
77
}
78
--
79
2.19.1
80
81
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/45] target/arm: Get IL bit correct for v7 syndrome values
Deleted patch
1
For the v7 version of the Arm architecture, the IL bit in
2
syndrome register values where the field is not valid was
3
defined to be UNK/SBZP. In v8 this is RES1, which is what
4
QEMU currently implements. Handle the desired v7 behaviour
5
by squashing the IL bit for the affected cases:
6
* EC == EC_UNCATEGORIZED
7
* prefetch aborts
8
* data aborts where ISV is 0
9
1
10
(The fourth case listed in the v8 Arm ARM DDI 0487C.a in
11
section G7.2.70, "illegal state exception", can't happen
12
on a v7 CPU.)
13
14
This deals with a corner case noted in a comment.
15
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20181012144235.19646-10-peter.maydell@linaro.org
19
---
20
target/arm/internals.h | 7 ++-----
21
target/arm/helper.c | 13 +++++++++++++
22
2 files changed, 15 insertions(+), 5 deletions(-)
23
24
diff --git a/target/arm/internals.h b/target/arm/internals.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/internals.h
27
+++ b/target/arm/internals.h
28
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_get_ec(uint32_t syn)
29
/* Utility functions for constructing various kinds of syndrome value.
30
* Note that in general we follow the AArch64 syndrome values; in a
31
* few cases the value in HSR for exceptions taken to AArch32 Hyp
32
- * mode differs slightly, so if we ever implemented Hyp mode then the
33
- * syndrome value would need some massaging on exception entry.
34
- * (One example of this is that AArch64 defaults to IL bit set for
35
- * exceptions which don't specifically indicate information about the
36
- * trapping instruction, whereas AArch32 defaults to IL bit clear.)
37
+ * mode differs slightly, and we fix this up when populating HSR in
38
+ * arm_cpu_do_interrupt_aarch32_hyp().
39
*/
40
static inline uint32_t syn_uncategorized(void)
41
{
42
diff --git a/target/arm/helper.c b/target/arm/helper.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/helper.c
45
+++ b/target/arm/helper.c
46
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
47
}
48
49
if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) {
50
+ if (!arm_feature(env, ARM_FEATURE_V8)) {
51
+ /*
52
+ * QEMU syndrome values are v8-style. v7 has the IL bit
53
+ * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
54
+ * If this is a v7 CPU, squash the IL bit in those cases.
55
+ */
56
+ if (cs->exception_index == EXCP_PREFETCH_ABORT ||
57
+ (cs->exception_index == EXCP_DATA_ABORT &&
58
+ !(env->exception.syndrome & ARM_EL_ISV)) ||
59
+ syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) {
60
+ env->exception.syndrome &= ~ARM_EL_IL;
61
+ }
62
+ }
63
env->cp15.esr_el[2] = env->exception.syndrome;
64
}
65
66
--
67
2.19.1
68
69
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/45] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode
Deleted patch
1
For traps of FP/SIMD instructions to AArch32 Hyp mode, the syndrome
2
provided in HSR has more information than is reported to AArch64.
3
Specifically, there are extra fields TA and coproc which indicate
4
whether the trapped instruction was FP or SIMD. Add this extra
5
information to the syndromes we construct, and mask it out when
6
taking the exception to AArch64.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20181012144235.19646-11-peter.maydell@linaro.org
11
---
12
target/arm/internals.h | 14 +++++++++++++-
13
target/arm/helper.c | 9 +++++++++
14
target/arm/translate.c | 8 ++++----
15
3 files changed, 26 insertions(+), 5 deletions(-)
16
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
20
+++ b/target/arm/internals.h
21
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_get_ec(uint32_t syn)
22
* few cases the value in HSR for exceptions taken to AArch32 Hyp
23
* mode differs slightly, and we fix this up when populating HSR in
24
* arm_cpu_do_interrupt_aarch32_hyp().
25
+ * The exception is FP/SIMD access traps -- these report extra information
26
+ * when taking an exception to AArch32. For those we include the extra coproc
27
+ * and TA fields, and mask them out when taking the exception to AArch64.
28
*/
29
static inline uint32_t syn_uncategorized(void)
30
{
31
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
32
33
static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
34
{
35
+ /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */
36
return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
37
| (is_16bit ? 0 : ARM_EL_IL)
38
- | (cv << 24) | (cond << 20);
39
+ | (cv << 24) | (cond << 20) | 0xa;
40
+}
41
+
42
+static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)
43
+{
44
+ /* AArch32 SIMD trap: TA == 1 coproc == 0 */
45
+ return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
46
+ | (is_16bit ? 0 : ARM_EL_IL)
47
+ | (cv << 24) | (cond << 20) | (1 << 5);
48
}
49
50
static inline uint32_t syn_sve_access_trap(void)
51
diff --git a/target/arm/helper.c b/target/arm/helper.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/helper.c
54
+++ b/target/arm/helper.c
55
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
56
case EXCP_HVC:
57
case EXCP_HYP_TRAP:
58
case EXCP_SMC:
59
+ if (syn_get_ec(env->exception.syndrome) == EC_ADVSIMDFPACCESSTRAP) {
60
+ /*
61
+ * QEMU internal FP/SIMD syndromes from AArch32 include the
62
+ * TA and coproc fields which are only exposed if the exception
63
+ * is taken to AArch32 Hyp mode. Mask them out to get a valid
64
+ * AArch64 format syndrome.
65
+ */
66
+ env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20);
67
+ }
68
env->cp15.esr_el[new_el] = env->exception.syndrome;
69
break;
70
case EXCP_IRQ:
71
diff --git a/target/arm/translate.c b/target/arm/translate.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/translate.c
74
+++ b/target/arm/translate.c
75
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
76
*/
77
if (s->fp_excp_el) {
78
gen_exception_insn(s, 4, EXCP_UDEF,
79
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
80
+ syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
81
return 0;
82
}
83
84
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
85
*/
86
if (s->fp_excp_el) {
87
gen_exception_insn(s, 4, EXCP_UDEF,
88
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
89
+ syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
90
return 0;
91
}
92
93
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
94
95
if (s->fp_excp_el) {
96
gen_exception_insn(s, 4, EXCP_UDEF,
97
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
98
+ syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
99
return 0;
100
}
101
if (!s->vfp_enabled) {
102
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
103
104
if (s->fp_excp_el) {
105
gen_exception_insn(s, 4, EXCP_UDEF,
106
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
107
+ syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
108
return 0;
109
}
110
if (!s->vfp_enabled) {
111
--
112
2.19.1
113
114
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/45] target/arm: Hoist address increment for vector memory ops
Deleted patch
1
From: Richard Henderson <rth@twiddle.net>
2
1
3
This can reduce the number of opcodes required for certain
4
complex forms of load-multiple (e.g. ld4.16b).
5
6
Signed-off-by: Richard Henderson <rth@twiddle.net>
7
Message-id: 20181011205206.3552-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-a64.c | 12 ++++++++----
12
1 file changed, 8 insertions(+), 4 deletions(-)
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
19
bool is_store = !extract32(insn, 22, 1);
20
bool is_postidx = extract32(insn, 23, 1);
21
bool is_q = extract32(insn, 30, 1);
22
- TCGv_i64 tcg_addr, tcg_rn;
23
+ TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
24
25
int ebytes = 1 << size;
26
int elements = (is_q ? 128 : 64) / (8 << size);
27
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
28
tcg_rn = cpu_reg_sp(s, rn);
29
tcg_addr = tcg_temp_new_i64();
30
tcg_gen_mov_i64(tcg_addr, tcg_rn);
31
+ tcg_ebytes = tcg_const_i64(ebytes);
32
33
for (r = 0; r < rpt; r++) {
34
int e;
35
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
36
clear_vec_high(s, is_q, tt);
37
}
38
}
39
- tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
40
+ tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes);
41
tt = (tt + 1) % 32;
42
}
43
}
44
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
45
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
46
}
47
}
48
+ tcg_temp_free_i64(tcg_ebytes);
49
tcg_temp_free_i64(tcg_addr);
50
}
51
52
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
53
bool replicate = false;
54
int index = is_q << 3 | S << 2 | size;
55
int ebytes, xs;
56
- TCGv_i64 tcg_addr, tcg_rn;
57
+ TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
58
59
switch (scale) {
60
case 3:
61
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
62
tcg_rn = cpu_reg_sp(s, rn);
63
tcg_addr = tcg_temp_new_i64();
64
tcg_gen_mov_i64(tcg_addr, tcg_rn);
65
+ tcg_ebytes = tcg_const_i64(ebytes);
66
67
for (xs = 0; xs < selem; xs++) {
68
if (replicate) {
69
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
70
do_vec_st(s, rt, index, tcg_addr, scale);
71
}
72
}
73
- tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
74
+ tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes);
75
rt = (rt + 1) % 32;
76
}
77
78
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
79
tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
80
}
81
}
82
+ tcg_temp_free_i64(tcg_ebytes);
83
tcg_temp_free_i64(tcg_addr);
84
}
85
86
--
87
2.19.1
88
89
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/45] target/arm: Don't call tcg_clear_temp_count
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This is done generically in translator_loop.
4
5
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Message-id: 20181011205206.3552-3-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 1 -
13
target/arm/translate.c | 1 -
14
2 files changed, 2 deletions(-)
15
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
19
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
21
22
static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
23
{
24
- tcg_clear_temp_count();
25
}
26
27
static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
28
diff --git a/target/arm/translate.c b/target/arm/translate.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/translate.c
31
+++ b/target/arm/translate.c
32
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
33
tcg_gen_movi_i32(tmp, 0);
34
store_cpu_field(tmp, condexec_bits);
35
}
36
- tcg_clear_temp_count();
37
}
38
39
static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
40
--
41
2.19.1
42
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/45] target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20181011205206.3552-4-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-a64.c | 28 +++-------------------------
9
1 file changed, 3 insertions(+), 25 deletions(-)
10
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
16
for (xs = 0; xs < selem; xs++) {
17
if (replicate) {
18
/* Load and replicate to all elements */
19
- uint64_t mulconst;
20
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
21
22
tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
23
get_mem_index(s), s->be_data + scale);
24
- switch (scale) {
25
- case 0:
26
- mulconst = 0x0101010101010101ULL;
27
- break;
28
- case 1:
29
- mulconst = 0x0001000100010001ULL;
30
- break;
31
- case 2:
32
- mulconst = 0x0000000100000001ULL;
33
- break;
34
- case 3:
35
- mulconst = 0;
36
- break;
37
- default:
38
- g_assert_not_reached();
39
- }
40
- if (mulconst) {
41
- tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
42
- }
43
- write_vec_element(s, tcg_tmp, rt, 0, MO_64);
44
- if (is_q) {
45
- write_vec_element(s, tcg_tmp, rt, 1, MO_64);
46
- }
47
+ tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt),
48
+ (is_q + 1) * 8, vec_full_reg_size(s),
49
+ tcg_tmp);
50
tcg_temp_free_i64(tcg_tmp);
51
- clear_vec_high(s, is_q, rt);
52
} else {
53
/* Load/store one element per register */
54
if (is_load) {
55
--
56
2.19.1
57
58
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/45] target/arm: Mark some arrays const
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Message-id: 20181011205206.3552-6-richard.henderson@linaro.org
6
[PMM: drop change to now-deleted cpu_mode_names array]
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
16
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 cpu_F0d, cpu_F1d;
18
19
#include "exec/gen-icount.h"
20
21
-static const char *regnames[] =
22
+static const char * const regnames[] =
23
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
24
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
25
26
@@ -XXX,XX +XXX,XX @@ static struct {
27
int nregs;
28
int interleave;
29
int spacing;
30
-} neon_ls_element_type[11] = {
31
+} const neon_ls_element_type[11] = {
32
{4, 4, 1},
33
{4, 4, 2},
34
{4, 1, 1},
35
--
36
2.19.1
37
38
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/45] target/arm: Use gvec for NEON VDUP
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Also introduces neon_element_offset to find the env offset
4
of a specific element within a neon register.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20181011205206.3552-7-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate.c | 63 ++++++++++++++++++++++++------------------
12
1 file changed, 36 insertions(+), 27 deletions(-)
13
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
17
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ neon_reg_offset (int reg, int n)
19
return vfp_reg_offset(0, sreg);
20
}
21
22
+/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
23
+ * where 0 is the least significant end of the register.
24
+ */
25
+static inline long
26
+neon_element_offset(int reg, int element, TCGMemOp size)
27
+{
28
+ int element_size = 1 << size;
29
+ int ofs = element * element_size;
30
+#ifdef HOST_WORDS_BIGENDIAN
31
+ /* Calculate the offset assuming fully little-endian,
32
+ * then XOR to account for the order of the 8-byte units.
33
+ */
34
+ if (element_size < 8) {
35
+ ofs ^= 8 - element_size;
36
+ }
37
+#endif
38
+ return neon_reg_offset(reg, 0) + ofs;
39
+}
40
+
41
static TCGv_i32 neon_load_reg(int reg, int pass)
42
{
43
TCGv_i32 tmp = tcg_temp_new_i32();
44
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
45
tmp = load_reg(s, rd);
46
if (insn & (1 << 23)) {
47
/* VDUP */
48
- if (size == 0) {
49
- gen_neon_dup_u8(tmp, 0);
50
- } else if (size == 1) {
51
- gen_neon_dup_low16(tmp);
52
- }
53
- for (n = 0; n <= pass * 2; n++) {
54
- tmp2 = tcg_temp_new_i32();
55
- tcg_gen_mov_i32(tmp2, tmp);
56
- neon_store_reg(rn, n, tmp2);
57
- }
58
- neon_store_reg(rn, n, tmp);
59
+ int vec_size = pass ? 16 : 8;
60
+ tcg_gen_gvec_dup_i32(size, neon_reg_offset(rn, 0),
61
+ vec_size, vec_size, tmp);
62
+ tcg_temp_free_i32(tmp);
63
} else {
64
/* VMOV */
65
switch (size) {
66
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
67
tcg_temp_free_i32(tmp);
68
} else if ((insn & 0x380) == 0) {
69
/* VDUP */
70
+ int element;
71
+ TCGMemOp size;
72
+
73
if ((insn & (7 << 16)) == 0 || (q && (rd & 1))) {
74
return 1;
75
}
76
- if (insn & (1 << 19)) {
77
- tmp = neon_load_reg(rm, 1);
78
- } else {
79
- tmp = neon_load_reg(rm, 0);
80
- }
81
if (insn & (1 << 16)) {
82
- gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
83
+ size = MO_8;
84
+ element = (insn >> 17) & 7;
85
} else if (insn & (1 << 17)) {
86
- if ((insn >> 18) & 1)
87
- gen_neon_dup_high16(tmp);
88
- else
89
- gen_neon_dup_low16(tmp);
90
+ size = MO_16;
91
+ element = (insn >> 18) & 3;
92
+ } else {
93
+ size = MO_32;
94
+ element = (insn >> 19) & 1;
95
}
96
- for (pass = 0; pass < (q ? 4 : 2); pass++) {
97
- tmp2 = tcg_temp_new_i32();
98
- tcg_gen_mov_i32(tmp2, tmp);
99
- neon_store_reg(rd, pass, tmp2);
100
- }
101
- tcg_temp_free_i32(tmp);
102
+ tcg_gen_gvec_dup_mem(size, neon_reg_offset(rd, 0),
103
+ neon_element_offset(rm, element, size),
104
+ q ? 16 : 8, q ? 16 : 8);
105
} else {
106
return 1;
107
}
108
--
109
2.19.1
110
111
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/45] target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20181011205206.3552-8-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 67 ++++++++++++++++++++++++------------------
9
1 file changed, 39 insertions(+), 28 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
16
return 1;
17
}
18
} else { /* (insn & 0x00380080) == 0 */
19
- int invert;
20
+ int invert, reg_ofs, vec_size;
21
+
22
if (q && (rd & 1)) {
23
return 1;
24
}
25
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
26
break;
27
case 14:
28
imm |= (imm << 8) | (imm << 16) | (imm << 24);
29
- if (invert)
30
+ if (invert) {
31
imm = ~imm;
32
+ }
33
break;
34
case 15:
35
if (invert) {
36
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
37
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
38
break;
39
}
40
- if (invert)
41
+ if (invert) {
42
imm = ~imm;
43
+ }
44
45
- for (pass = 0; pass < (q ? 4 : 2); pass++) {
46
- if (op & 1 && op < 12) {
47
- tmp = neon_load_reg(rd, pass);
48
- if (invert) {
49
- /* The immediate value has already been inverted, so
50
- BIC becomes AND. */
51
- tcg_gen_andi_i32(tmp, tmp, imm);
52
- } else {
53
- tcg_gen_ori_i32(tmp, tmp, imm);
54
- }
55
+ reg_ofs = neon_reg_offset(rd, 0);
56
+ vec_size = q ? 16 : 8;
57
+
58
+ if (op & 1 && op < 12) {
59
+ if (invert) {
60
+ /* The immediate value has already been inverted,
61
+ * so BIC becomes AND.
62
+ */
63
+ tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm,
64
+ vec_size, vec_size);
65
} else {
66
- /* VMOV, VMVN. */
67
- tmp = tcg_temp_new_i32();
68
- if (op == 14 && invert) {
69
- int n;
70
- uint32_t val;
71
- val = 0;
72
- for (n = 0; n < 4; n++) {
73
- if (imm & (1 << (n + (pass & 1) * 4)))
74
- val |= 0xff << (n * 8);
75
- }
76
- tcg_gen_movi_i32(tmp, val);
77
- } else {
78
- tcg_gen_movi_i32(tmp, imm);
79
- }
80
+ tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm,
81
+ vec_size, vec_size);
82
+ }
83
+ } else {
84
+ /* VMOV, VMVN. */
85
+ if (op == 14 && invert) {
86
+ TCGv_i64 t64 = tcg_temp_new_i64();
87
+
88
+ for (pass = 0; pass <= q; ++pass) {
89
+ uint64_t val = 0;
90
+ int n;
91
+
92
+ for (n = 0; n < 8; n++) {
93
+ if (imm & (1 << (n + pass * 8))) {
94
+ val |= 0xffull << (n * 8);
95
+ }
96
+ }
97
+ tcg_gen_movi_i64(t64, val);
98
+ neon_store_reg64(t64, rd + pass);
99
+ }
100
+ tcg_temp_free_i64(t64);
101
+ } else {
102
+ tcg_gen_gvec_dup32i(reg_ofs, vec_size, vec_size, imm);
103
}
104
- neon_store_reg(rd, pass, tmp);
105
}
106
}
107
} else { /* (insn & 0x00800010 == 0x00800000) */
108
--
109
2.19.1
110
111
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/45] target/arm: Use gvec for NEON_3R_VADD_VSUB insns
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20181011205206.3552-10-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 29 ++++++++++-------------------
9
1 file changed, 10 insertions(+), 19 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
16
break;
17
}
18
return 0;
19
+
20
+ case NEON_3R_VADD_VSUB:
21
+ if (u) {
22
+ tcg_gen_gvec_sub(size, rd_ofs, rn_ofs, rm_ofs,
23
+ vec_size, vec_size);
24
+ } else {
25
+ tcg_gen_gvec_add(size, rd_ofs, rn_ofs, rm_ofs,
26
+ vec_size, vec_size);
27
+ }
28
+ return 0;
29
}
30
if (size == 3) {
31
/* 64-bit element instructions. */
32
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
33
cpu_V1, cpu_V0);
34
}
35
break;
36
- case NEON_3R_VADD_VSUB:
37
- if (u) {
38
- tcg_gen_sub_i64(CPU_V001);
39
- } else {
40
- tcg_gen_add_i64(CPU_V001);
41
- }
42
- break;
43
default:
44
abort();
45
}
46
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
47
tmp2 = neon_load_reg(rd, pass);
48
gen_neon_add(size, tmp, tmp2);
49
break;
50
- case NEON_3R_VADD_VSUB:
51
- if (!u) { /* VADD */
52
- gen_neon_add(size, tmp, tmp2);
53
- } else { /* VSUB */
54
- switch (size) {
55
- case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
56
- case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
57
- case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
58
- default: abort();
59
- }
60
- }
61
- break;
62
case NEON_3R_VTST_VCEQ:
63
if (!u) { /* VTST */
64
switch (size) {
65
--
66
2.19.1
67
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/45] target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20181011205206.3552-11-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 16 ++++++++--------
9
1 file changed, 8 insertions(+), 8 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
16
tcg_temp_free_ptr(ptr1);
17
tcg_temp_free_ptr(ptr2);
18
break;
19
+
20
+ case NEON_2RM_VMVN:
21
+ tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size);
22
+ break;
23
+ case NEON_2RM_VNEG:
24
+ tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_size);
25
+ break;
26
+
27
default:
28
elementwise:
29
for (pass = 0; pass < (q ? 4 : 2); pass++) {
30
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
31
case NEON_2RM_VCNT:
32
gen_helper_neon_cnt_u8(tmp, tmp);
33
break;
34
- case NEON_2RM_VMVN:
35
- tcg_gen_not_i32(tmp, tmp);
36
- break;
37
case NEON_2RM_VQABS:
38
switch (size) {
39
case 0:
40
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
41
default: abort();
42
}
43
break;
44
- case NEON_2RM_VNEG:
45
- tmp2 = tcg_const_i32(0);
46
- gen_neon_rsb(size, tmp, tmp2);
47
- tcg_temp_free_i32(tmp2);
48
- break;
49
case NEON_2RM_VCGT0_F:
50
{
51
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
52
--
53
2.19.1
54
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 32/45] target/arm: Use gvec for NEON_3R_VMUL
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20181011205206.3552-12-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate.c | 31 +++++++++++++++----------------
9
1 file changed, 15 insertions(+), 16 deletions(-)
10
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
+++ b/target/arm/translate.c
15
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
16
vec_size, vec_size);
17
}
18
return 0;
19
+
20
+ case NEON_3R_VMUL: /* VMUL */
21
+ if (u) {
22
+ /* Polynomial case allows only P8 and is handled below. */
23
+ if (size != 0) {
24
+ return 1;
25
+ }
26
+ } else {
27
+ tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs,
28
+ vec_size, vec_size);
29
+ return 0;
30
+ }
31
+ break;
32
}
33
if (size == 3) {
34
/* 64-bit element instructions. */
35
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
36
return 1;
37
}
38
break;
39
- case NEON_3R_VMUL:
40
- if (u && (size != 0)) {
41
- /* UNDEF on invalid size for polynomial subcase */
42
- return 1;
43
- }
44
- break;
45
case NEON_3R_VFM_VQRDMLSH:
46
if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
47
return 1;
48
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
49
}
50
break;
51
case NEON_3R_VMUL:
52
- if (u) { /* polynomial */
53
- gen_helper_neon_mul_p8(tmp, tmp, tmp2);
54
- } else { /* Integer */
55
- switch (size) {
56
- case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
57
- case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
58
- case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
59
- default: abort();
60
- }
61
- }
62
+ /* VMUL.P8; other cases already eliminated. */
63
+ gen_helper_neon_mul_p8(tmp, tmp, tmp2);
64
break;
65
case NEON_3R_VPMAX:
66
GEN_NEON_INTEGER_OP(pmax);
67
--
68
2.19.1
69
70
diff view generated by jsdifflib
[Qemu-devel] [PULL 33/45] target/arm: Use gvec for VSHR, VSHL
[PULL 21/21] docs: sbsa: correct graphics card name
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
We moved from VGA to Bochs to have PCIe card.
4
Message-id: 20181011205206.3552-13-richard.henderson@linaro.org
4
5
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
---
8
target/arm/translate.c | 70 +++++++++++++++++++++++++++++-------------
9
docs/system/arm/sbsa.rst | 2 +-
9
1 file changed, 48 insertions(+), 22 deletions(-)
10
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
11
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate.c
14
--- a/docs/system/arm/sbsa.rst
14
+++ b/target/arm/translate.c
15
+++ b/docs/system/arm/sbsa.rst
15
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
16
@@ -XXX,XX +XXX,XX @@ The sbsa-ref board supports:
16
size--;
17
- System bus EHCI controller
17
}
18
- CDROM and hard disc on AHCI bus
18
shift = (insn >> 16) & ((1 << (3 + size)) - 1);
19
- E1000E ethernet card on PCIe bus
19
- /* To avoid excessive duplication of ops we implement shift
20
- - VGA display adaptor on PCIe bus
20
- by immediate using the variable shift operations. */
21
+ - Bochs display adapter on PCIe bus
21
if (op < 8) {
22
- A generic SBSA watchdog device
22
/* Shift by immediate:
23
VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
24
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
25
}
26
/* Right shifts are encoded as N - shift, where N is the
27
element size in bits. */
28
- if (op <= 4)
29
+ if (op <= 4) {
30
shift = shift - (1 << (size + 3));
31
+ }
32
+
33
+ switch (op) {
34
+ case 0: /* VSHR */
35
+ /* Right shift comes here negative. */
36
+ shift = -shift;
37
+ /* Shifts larger than the element size are architecturally
38
+ * valid. Unsigned results in all zeros; signed results
39
+ * in all sign bits.
40
+ */
41
+ if (!u) {
42
+ tcg_gen_gvec_sari(size, rd_ofs, rm_ofs,
43
+ MIN(shift, (8 << size) - 1),
44
+ vec_size, vec_size);
45
+ } else if (shift >= 8 << size) {
46
+ tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
47
+ } else {
48
+ tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
49
+ vec_size, vec_size);
50
+ }
51
+ return 0;
52
+
53
+ case 5: /* VSHL, VSLI */
54
+ if (!u) { /* VSHL */
55
+ /* Shifts larger than the element size are
56
+ * architecturally valid and results in zero.
57
+ */
58
+ if (shift >= 8 << size) {
59
+ tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
60
+ } else {
61
+ tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
62
+ vec_size, vec_size);
63
+ }
64
+ return 0;
65
+ }
66
+ break;
67
+ }
68
+
69
if (size == 3) {
70
count = q + 1;
71
} else {
72
count = q ? 4: 2;
73
}
74
- switch (size) {
75
- case 0:
76
- imm = (uint8_t) shift;
77
- imm |= imm << 8;
78
- imm |= imm << 16;
79
- break;
80
- case 1:
81
- imm = (uint16_t) shift;
82
- imm |= imm << 16;
83
- break;
84
- case 2:
85
- case 3:
86
- imm = shift;
87
- break;
88
- default:
89
- abort();
90
- }
91
+
92
+ /* To avoid excessive duplication of ops we implement shift
93
+ * by immediate using the variable shift operations.
94
+ */
95
+ imm = dup_const(size, shift);
96
97
for (pass = 0; pass < count; pass++) {
98
if (size == 3) {
99
neon_load_reg64(cpu_V0, rm + pass);
100
tcg_gen_movi_i64(cpu_V1, imm);
101
switch (op) {
102
- case 0: /* VSHR */
103
case 1: /* VSRA */
104
if (u)
105
gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
106
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
107
cpu_V0, cpu_V1);
108
}
109
break;
110
+ default:
111
+ g_assert_not_reached();
112
}
113
if (op == 1 || op == 3) {
114
/* Accumulate. */
115
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
116
tmp2 = tcg_temp_new_i32();
117
tcg_gen_movi_i32(tmp2, imm);
118
switch (op) {
119
- case 0: /* VSHR */
120
case 1: /* VSRA */
121
GEN_NEON_INTEGER_OP(shl);
122
break;
123
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
124
case 7: /* VQSHL */
125
GEN_NEON_INTEGER_OP_ENV(qshl);
126
break;
127
+ default:
128
+ g_assert_not_reached();
129
}
130
tcg_temp_free_i32(tmp2);
131
23
132
--
24
--
133
2.19.1
25
2.34.1
134
135
diff view generated by jsdifflib
[Qemu-devel] [PULL 34/45] target/arm: Use gvec for VSRA
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Move ssra_op and usra_op expanders from translate-a64.c.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20181011205206.3552-14-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate.h | 2 +
11
target/arm/translate-a64.c | 106 ----------------------------
12
target/arm/translate.c | 139 ++++++++++++++++++++++++++++++++++---
13
3 files changed, 130 insertions(+), 117 deletions(-)
14
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
18
+++ b/target/arm/translate.h
19
@@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 get_ahp_flag(void)
20
extern const GVecGen3 bsl_op;
21
extern const GVecGen3 bit_op;
22
extern const GVecGen3 bif_op;
23
+extern const GVecGen2i ssra_op[4];
24
+extern const GVecGen2i usra_op[4];
25
26
/*
27
* Forward to the isar_feature_* tests given a DisasContext pointer.
28
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/translate-a64.c
31
+++ b/target/arm/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
33
}
34
}
35
36
-static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
37
-{
38
- tcg_gen_vec_sar8i_i64(a, a, shift);
39
- tcg_gen_vec_add8_i64(d, d, a);
40
-}
41
-
42
-static void gen_ssra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
43
-{
44
- tcg_gen_vec_sar16i_i64(a, a, shift);
45
- tcg_gen_vec_add16_i64(d, d, a);
46
-}
47
-
48
-static void gen_ssra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
49
-{
50
- tcg_gen_sari_i32(a, a, shift);
51
- tcg_gen_add_i32(d, d, a);
52
-}
53
-
54
-static void gen_ssra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
55
-{
56
- tcg_gen_sari_i64(a, a, shift);
57
- tcg_gen_add_i64(d, d, a);
58
-}
59
-
60
-static void gen_ssra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
61
-{
62
- tcg_gen_sari_vec(vece, a, a, sh);
63
- tcg_gen_add_vec(vece, d, d, a);
64
-}
65
-
66
-static void gen_usra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
67
-{
68
- tcg_gen_vec_shr8i_i64(a, a, shift);
69
- tcg_gen_vec_add8_i64(d, d, a);
70
-}
71
-
72
-static void gen_usra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
73
-{
74
- tcg_gen_vec_shr16i_i64(a, a, shift);
75
- tcg_gen_vec_add16_i64(d, d, a);
76
-}
77
-
78
-static void gen_usra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
79
-{
80
- tcg_gen_shri_i32(a, a, shift);
81
- tcg_gen_add_i32(d, d, a);
82
-}
83
-
84
-static void gen_usra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
85
-{
86
- tcg_gen_shri_i64(a, a, shift);
87
- tcg_gen_add_i64(d, d, a);
88
-}
89
-
90
-static void gen_usra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
91
-{
92
- tcg_gen_shri_vec(vece, a, a, sh);
93
- tcg_gen_add_vec(vece, d, d, a);
94
-}
95
-
96
static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
97
{
98
uint64_t mask = dup_const(MO_8, 0xff >> shift);
99
@@ -XXX,XX +XXX,XX @@ static void gen_shr_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
100
static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
101
int immh, int immb, int opcode, int rn, int rd)
102
{
103
- static const GVecGen2i ssra_op[4] = {
104
- { .fni8 = gen_ssra8_i64,
105
- .fniv = gen_ssra_vec,
106
- .load_dest = true,
107
- .opc = INDEX_op_sari_vec,
108
- .vece = MO_8 },
109
- { .fni8 = gen_ssra16_i64,
110
- .fniv = gen_ssra_vec,
111
- .load_dest = true,
112
- .opc = INDEX_op_sari_vec,
113
- .vece = MO_16 },
114
- { .fni4 = gen_ssra32_i32,
115
- .fniv = gen_ssra_vec,
116
- .load_dest = true,
117
- .opc = INDEX_op_sari_vec,
118
- .vece = MO_32 },
119
- { .fni8 = gen_ssra64_i64,
120
- .fniv = gen_ssra_vec,
121
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
122
- .load_dest = true,
123
- .opc = INDEX_op_sari_vec,
124
- .vece = MO_64 },
125
- };
126
- static const GVecGen2i usra_op[4] = {
127
- { .fni8 = gen_usra8_i64,
128
- .fniv = gen_usra_vec,
129
- .load_dest = true,
130
- .opc = INDEX_op_shri_vec,
131
- .vece = MO_8, },
132
- { .fni8 = gen_usra16_i64,
133
- .fniv = gen_usra_vec,
134
- .load_dest = true,
135
- .opc = INDEX_op_shri_vec,
136
- .vece = MO_16, },
137
- { .fni4 = gen_usra32_i32,
138
- .fniv = gen_usra_vec,
139
- .load_dest = true,
140
- .opc = INDEX_op_shri_vec,
141
- .vece = MO_32, },
142
- { .fni8 = gen_usra64_i64,
143
- .fniv = gen_usra_vec,
144
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
145
- .load_dest = true,
146
- .opc = INDEX_op_shri_vec,
147
- .vece = MO_64, },
148
- };
149
static const GVecGen2i sri_op[4] = {
150
{ .fni8 = gen_shr8_ins_i64,
151
.fniv = gen_shr_ins_vec,
152
diff --git a/target/arm/translate.c b/target/arm/translate.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/target/arm/translate.c
155
+++ b/target/arm/translate.c
156
@@ -XXX,XX +XXX,XX @@ const GVecGen3 bif_op = {
157
.load_dest = true
158
};
159
160
+static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
161
+{
162
+ tcg_gen_vec_sar8i_i64(a, a, shift);
163
+ tcg_gen_vec_add8_i64(d, d, a);
164
+}
165
+
166
+static void gen_ssra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
167
+{
168
+ tcg_gen_vec_sar16i_i64(a, a, shift);
169
+ tcg_gen_vec_add16_i64(d, d, a);
170
+}
171
+
172
+static void gen_ssra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
173
+{
174
+ tcg_gen_sari_i32(a, a, shift);
175
+ tcg_gen_add_i32(d, d, a);
176
+}
177
+
178
+static void gen_ssra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
179
+{
180
+ tcg_gen_sari_i64(a, a, shift);
181
+ tcg_gen_add_i64(d, d, a);
182
+}
183
+
184
+static void gen_ssra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
185
+{
186
+ tcg_gen_sari_vec(vece, a, a, sh);
187
+ tcg_gen_add_vec(vece, d, d, a);
188
+}
189
+
190
+const GVecGen2i ssra_op[4] = {
191
+ { .fni8 = gen_ssra8_i64,
192
+ .fniv = gen_ssra_vec,
193
+ .load_dest = true,
194
+ .opc = INDEX_op_sari_vec,
195
+ .vece = MO_8 },
196
+ { .fni8 = gen_ssra16_i64,
197
+ .fniv = gen_ssra_vec,
198
+ .load_dest = true,
199
+ .opc = INDEX_op_sari_vec,
200
+ .vece = MO_16 },
201
+ { .fni4 = gen_ssra32_i32,
202
+ .fniv = gen_ssra_vec,
203
+ .load_dest = true,
204
+ .opc = INDEX_op_sari_vec,
205
+ .vece = MO_32 },
206
+ { .fni8 = gen_ssra64_i64,
207
+ .fniv = gen_ssra_vec,
208
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
209
+ .load_dest = true,
210
+ .opc = INDEX_op_sari_vec,
211
+ .vece = MO_64 },
212
+};
213
+
214
+static void gen_usra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
215
+{
216
+ tcg_gen_vec_shr8i_i64(a, a, shift);
217
+ tcg_gen_vec_add8_i64(d, d, a);
218
+}
219
+
220
+static void gen_usra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
221
+{
222
+ tcg_gen_vec_shr16i_i64(a, a, shift);
223
+ tcg_gen_vec_add16_i64(d, d, a);
224
+}
225
+
226
+static void gen_usra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
227
+{
228
+ tcg_gen_shri_i32(a, a, shift);
229
+ tcg_gen_add_i32(d, d, a);
230
+}
231
+
232
+static void gen_usra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
233
+{
234
+ tcg_gen_shri_i64(a, a, shift);
235
+ tcg_gen_add_i64(d, d, a);
236
+}
237
+
238
+static void gen_usra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
239
+{
240
+ tcg_gen_shri_vec(vece, a, a, sh);
241
+ tcg_gen_add_vec(vece, d, d, a);
242
+}
243
+
244
+const GVecGen2i usra_op[4] = {
245
+ { .fni8 = gen_usra8_i64,
246
+ .fniv = gen_usra_vec,
247
+ .load_dest = true,
248
+ .opc = INDEX_op_shri_vec,
249
+ .vece = MO_8, },
250
+ { .fni8 = gen_usra16_i64,
251
+ .fniv = gen_usra_vec,
252
+ .load_dest = true,
253
+ .opc = INDEX_op_shri_vec,
254
+ .vece = MO_16, },
255
+ { .fni4 = gen_usra32_i32,
256
+ .fniv = gen_usra_vec,
257
+ .load_dest = true,
258
+ .opc = INDEX_op_shri_vec,
259
+ .vece = MO_32, },
260
+ { .fni8 = gen_usra64_i64,
261
+ .fniv = gen_usra_vec,
262
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
263
+ .load_dest = true,
264
+ .opc = INDEX_op_shri_vec,
265
+ .vece = MO_64, },
266
+};
267
268
/* Translate a NEON data processing instruction. Return nonzero if the
269
instruction is invalid.
270
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
271
}
272
return 0;
273
274
+ case 1: /* VSRA */
275
+ /* Right shift comes here negative. */
276
+ shift = -shift;
277
+ /* Shifts larger than the element size are architecturally
278
+ * valid. Unsigned results in all zeros; signed results
279
+ * in all sign bits.
280
+ */
281
+ if (!u) {
282
+ tcg_gen_gvec_2i(rd_ofs, rm_ofs, vec_size, vec_size,
283
+ MIN(shift, (8 << size) - 1),
284
+ &ssra_op[size]);
285
+ } else if (shift >= 8 << size) {
286
+ /* rd += 0 */
287
+ } else {
288
+ tcg_gen_gvec_2i(rd_ofs, rm_ofs, vec_size, vec_size,
289
+ shift, &usra_op[size]);
290
+ }
291
+ return 0;
292
+
293
case 5: /* VSHL, VSLI */
294
if (!u) { /* VSHL */
295
/* Shifts larger than the element size are
296
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
297
neon_load_reg64(cpu_V0, rm + pass);
298
tcg_gen_movi_i64(cpu_V1, imm);
299
switch (op) {
300
- case 1: /* VSRA */
301
- if (u)
302
- gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
303
- else
304
- gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
305
- break;
306
case 2: /* VRSHR */
307
case 3: /* VRSRA */
308
if (u)
309
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
310
default:
311
g_assert_not_reached();
312
}
313
- if (op == 1 || op == 3) {
314
+ if (op == 3) {
315
/* Accumulate. */
316
neon_load_reg64(cpu_V1, rd + pass);
317
tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
318
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
319
tmp2 = tcg_temp_new_i32();
320
tcg_gen_movi_i32(tmp2, imm);
321
switch (op) {
322
- case 1: /* VSRA */
323
- GEN_NEON_INTEGER_OP(shl);
324
- break;
325
case 2: /* VRSHR */
326
case 3: /* VRSRA */
327
GEN_NEON_INTEGER_OP(rshl);
328
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
329
}
330
tcg_temp_free_i32(tmp2);
331
332
- if (op == 1 || op == 3) {
333
+ if (op == 3) {
334
/* Accumulate. */
335
tmp2 = neon_load_reg(rd, pass);
336
gen_neon_add(size, tmp, tmp2);
337
--
338
2.19.1
339
340
diff view generated by jsdifflib
[Qemu-devel] [PULL 35/45] target/arm: Use gvec for VSRI, VSLI
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Move shi_op and sli_op expanders from translate-a64.c.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20181011205206.3552-15-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate.h | 2 +
11
target/arm/translate-a64.c | 152 +----------------------
12
target/arm/translate.c | 244 ++++++++++++++++++++++++++-----------
13
3 files changed, 179 insertions(+), 219 deletions(-)
14
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
18
+++ b/target/arm/translate.h
19
@@ -XXX,XX +XXX,XX @@ extern const GVecGen3 bit_op;
20
extern const GVecGen3 bif_op;
21
extern const GVecGen2i ssra_op[4];
22
extern const GVecGen2i usra_op[4];
23
+extern const GVecGen2i sri_op[4];
24
+extern const GVecGen2i sli_op[4];
25
26
/*
27
* Forward to the isar_feature_* tests given a DisasContext pointer.
28
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/translate-a64.c
31
+++ b/target/arm/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
33
}
34
}
35
36
-static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
37
-{
38
- uint64_t mask = dup_const(MO_8, 0xff >> shift);
39
- TCGv_i64 t = tcg_temp_new_i64();
40
-
41
- tcg_gen_shri_i64(t, a, shift);
42
- tcg_gen_andi_i64(t, t, mask);
43
- tcg_gen_andi_i64(d, d, ~mask);
44
- tcg_gen_or_i64(d, d, t);
45
- tcg_temp_free_i64(t);
46
-}
47
-
48
-static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
49
-{
50
- uint64_t mask = dup_const(MO_16, 0xffff >> shift);
51
- TCGv_i64 t = tcg_temp_new_i64();
52
-
53
- tcg_gen_shri_i64(t, a, shift);
54
- tcg_gen_andi_i64(t, t, mask);
55
- tcg_gen_andi_i64(d, d, ~mask);
56
- tcg_gen_or_i64(d, d, t);
57
- tcg_temp_free_i64(t);
58
-}
59
-
60
-static void gen_shr32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
61
-{
62
- tcg_gen_shri_i32(a, a, shift);
63
- tcg_gen_deposit_i32(d, d, a, 0, 32 - shift);
64
-}
65
-
66
-static void gen_shr64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
67
-{
68
- tcg_gen_shri_i64(a, a, shift);
69
- tcg_gen_deposit_i64(d, d, a, 0, 64 - shift);
70
-}
71
-
72
-static void gen_shr_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
73
-{
74
- uint64_t mask = (2ull << ((8 << vece) - 1)) - 1;
75
- TCGv_vec t = tcg_temp_new_vec_matching(d);
76
- TCGv_vec m = tcg_temp_new_vec_matching(d);
77
-
78
- tcg_gen_dupi_vec(vece, m, mask ^ (mask >> sh));
79
- tcg_gen_shri_vec(vece, t, a, sh);
80
- tcg_gen_and_vec(vece, d, d, m);
81
- tcg_gen_or_vec(vece, d, d, t);
82
-
83
- tcg_temp_free_vec(t);
84
- tcg_temp_free_vec(m);
85
-}
86
-
87
/* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
88
static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
89
int immh, int immb, int opcode, int rn, int rd)
90
{
91
- static const GVecGen2i sri_op[4] = {
92
- { .fni8 = gen_shr8_ins_i64,
93
- .fniv = gen_shr_ins_vec,
94
- .load_dest = true,
95
- .opc = INDEX_op_shri_vec,
96
- .vece = MO_8 },
97
- { .fni8 = gen_shr16_ins_i64,
98
- .fniv = gen_shr_ins_vec,
99
- .load_dest = true,
100
- .opc = INDEX_op_shri_vec,
101
- .vece = MO_16 },
102
- { .fni4 = gen_shr32_ins_i32,
103
- .fniv = gen_shr_ins_vec,
104
- .load_dest = true,
105
- .opc = INDEX_op_shri_vec,
106
- .vece = MO_32 },
107
- { .fni8 = gen_shr64_ins_i64,
108
- .fniv = gen_shr_ins_vec,
109
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
110
- .load_dest = true,
111
- .opc = INDEX_op_shri_vec,
112
- .vece = MO_64 },
113
- };
114
-
115
int size = 32 - clz32(immh) - 1;
116
int immhb = immh << 3 | immb;
117
int shift = 2 * (8 << size) - immhb;
118
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
119
clear_vec_high(s, is_q, rd);
120
}
121
122
-static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
123
-{
124
- uint64_t mask = dup_const(MO_8, 0xff << shift);
125
- TCGv_i64 t = tcg_temp_new_i64();
126
-
127
- tcg_gen_shli_i64(t, a, shift);
128
- tcg_gen_andi_i64(t, t, mask);
129
- tcg_gen_andi_i64(d, d, ~mask);
130
- tcg_gen_or_i64(d, d, t);
131
- tcg_temp_free_i64(t);
132
-}
133
-
134
-static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
135
-{
136
- uint64_t mask = dup_const(MO_16, 0xffff << shift);
137
- TCGv_i64 t = tcg_temp_new_i64();
138
-
139
- tcg_gen_shli_i64(t, a, shift);
140
- tcg_gen_andi_i64(t, t, mask);
141
- tcg_gen_andi_i64(d, d, ~mask);
142
- tcg_gen_or_i64(d, d, t);
143
- tcg_temp_free_i64(t);
144
-}
145
-
146
-static void gen_shl32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
147
-{
148
- tcg_gen_deposit_i32(d, d, a, shift, 32 - shift);
149
-}
150
-
151
-static void gen_shl64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
152
-{
153
- tcg_gen_deposit_i64(d, d, a, shift, 64 - shift);
154
-}
155
-
156
-static void gen_shl_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
157
-{
158
- uint64_t mask = (1ull << sh) - 1;
159
- TCGv_vec t = tcg_temp_new_vec_matching(d);
160
- TCGv_vec m = tcg_temp_new_vec_matching(d);
161
-
162
- tcg_gen_dupi_vec(vece, m, mask);
163
- tcg_gen_shli_vec(vece, t, a, sh);
164
- tcg_gen_and_vec(vece, d, d, m);
165
- tcg_gen_or_vec(vece, d, d, t);
166
-
167
- tcg_temp_free_vec(t);
168
- tcg_temp_free_vec(m);
169
-}
170
-
171
/* SHL/SLI - Vector shift left */
172
static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
173
int immh, int immb, int opcode, int rn, int rd)
174
{
175
- static const GVecGen2i shi_op[4] = {
176
- { .fni8 = gen_shl8_ins_i64,
177
- .fniv = gen_shl_ins_vec,
178
- .opc = INDEX_op_shli_vec,
179
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
180
- .load_dest = true,
181
- .vece = MO_8 },
182
- { .fni8 = gen_shl16_ins_i64,
183
- .fniv = gen_shl_ins_vec,
184
- .opc = INDEX_op_shli_vec,
185
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
186
- .load_dest = true,
187
- .vece = MO_16 },
188
- { .fni4 = gen_shl32_ins_i32,
189
- .fniv = gen_shl_ins_vec,
190
- .opc = INDEX_op_shli_vec,
191
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
192
- .load_dest = true,
193
- .vece = MO_32 },
194
- { .fni8 = gen_shl64_ins_i64,
195
- .fniv = gen_shl_ins_vec,
196
- .opc = INDEX_op_shli_vec,
197
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
198
- .load_dest = true,
199
- .vece = MO_64 },
200
- };
201
int size = 32 - clz32(immh) - 1;
202
int immhb = immh << 3 | immb;
203
int shift = immhb - (8 << size);
204
@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
205
}
206
207
if (insert) {
208
- gen_gvec_op2i(s, is_q, rd, rn, shift, &shi_op[size]);
209
+ gen_gvec_op2i(s, is_q, rd, rn, shift, &sli_op[size]);
210
} else {
211
gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size);
212
}
213
diff --git a/target/arm/translate.c b/target/arm/translate.c
214
index XXXXXXX..XXXXXXX 100644
215
--- a/target/arm/translate.c
216
+++ b/target/arm/translate.c
217
@@ -XXX,XX +XXX,XX @@ const GVecGen2i usra_op[4] = {
218
.vece = MO_64, },
219
};
220
221
+static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
222
+{
223
+ uint64_t mask = dup_const(MO_8, 0xff >> shift);
224
+ TCGv_i64 t = tcg_temp_new_i64();
225
+
226
+ tcg_gen_shri_i64(t, a, shift);
227
+ tcg_gen_andi_i64(t, t, mask);
228
+ tcg_gen_andi_i64(d, d, ~mask);
229
+ tcg_gen_or_i64(d, d, t);
230
+ tcg_temp_free_i64(t);
231
+}
232
+
233
+static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
234
+{
235
+ uint64_t mask = dup_const(MO_16, 0xffff >> shift);
236
+ TCGv_i64 t = tcg_temp_new_i64();
237
+
238
+ tcg_gen_shri_i64(t, a, shift);
239
+ tcg_gen_andi_i64(t, t, mask);
240
+ tcg_gen_andi_i64(d, d, ~mask);
241
+ tcg_gen_or_i64(d, d, t);
242
+ tcg_temp_free_i64(t);
243
+}
244
+
245
+static void gen_shr32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
246
+{
247
+ tcg_gen_shri_i32(a, a, shift);
248
+ tcg_gen_deposit_i32(d, d, a, 0, 32 - shift);
249
+}
250
+
251
+static void gen_shr64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
252
+{
253
+ tcg_gen_shri_i64(a, a, shift);
254
+ tcg_gen_deposit_i64(d, d, a, 0, 64 - shift);
255
+}
256
+
257
+static void gen_shr_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
258
+{
259
+ if (sh == 0) {
260
+ tcg_gen_mov_vec(d, a);
261
+ } else {
262
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
263
+ TCGv_vec m = tcg_temp_new_vec_matching(d);
264
+
265
+ tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK((8 << vece) - sh, sh));
266
+ tcg_gen_shri_vec(vece, t, a, sh);
267
+ tcg_gen_and_vec(vece, d, d, m);
268
+ tcg_gen_or_vec(vece, d, d, t);
269
+
270
+ tcg_temp_free_vec(t);
271
+ tcg_temp_free_vec(m);
272
+ }
273
+}
274
+
275
+const GVecGen2i sri_op[4] = {
276
+ { .fni8 = gen_shr8_ins_i64,
277
+ .fniv = gen_shr_ins_vec,
278
+ .load_dest = true,
279
+ .opc = INDEX_op_shri_vec,
280
+ .vece = MO_8 },
281
+ { .fni8 = gen_shr16_ins_i64,
282
+ .fniv = gen_shr_ins_vec,
283
+ .load_dest = true,
284
+ .opc = INDEX_op_shri_vec,
285
+ .vece = MO_16 },
286
+ { .fni4 = gen_shr32_ins_i32,
287
+ .fniv = gen_shr_ins_vec,
288
+ .load_dest = true,
289
+ .opc = INDEX_op_shri_vec,
290
+ .vece = MO_32 },
291
+ { .fni8 = gen_shr64_ins_i64,
292
+ .fniv = gen_shr_ins_vec,
293
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
294
+ .load_dest = true,
295
+ .opc = INDEX_op_shri_vec,
296
+ .vece = MO_64 },
297
+};
298
+
299
+static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
300
+{
301
+ uint64_t mask = dup_const(MO_8, 0xff << shift);
302
+ TCGv_i64 t = tcg_temp_new_i64();
303
+
304
+ tcg_gen_shli_i64(t, a, shift);
305
+ tcg_gen_andi_i64(t, t, mask);
306
+ tcg_gen_andi_i64(d, d, ~mask);
307
+ tcg_gen_or_i64(d, d, t);
308
+ tcg_temp_free_i64(t);
309
+}
310
+
311
+static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
312
+{
313
+ uint64_t mask = dup_const(MO_16, 0xffff << shift);
314
+ TCGv_i64 t = tcg_temp_new_i64();
315
+
316
+ tcg_gen_shli_i64(t, a, shift);
317
+ tcg_gen_andi_i64(t, t, mask);
318
+ tcg_gen_andi_i64(d, d, ~mask);
319
+ tcg_gen_or_i64(d, d, t);
320
+ tcg_temp_free_i64(t);
321
+}
322
+
323
+static void gen_shl32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
324
+{
325
+ tcg_gen_deposit_i32(d, d, a, shift, 32 - shift);
326
+}
327
+
328
+static void gen_shl64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
329
+{
330
+ tcg_gen_deposit_i64(d, d, a, shift, 64 - shift);
331
+}
332
+
333
+static void gen_shl_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
334
+{
335
+ if (sh == 0) {
336
+ tcg_gen_mov_vec(d, a);
337
+ } else {
338
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
339
+ TCGv_vec m = tcg_temp_new_vec_matching(d);
340
+
341
+ tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK(0, sh));
342
+ tcg_gen_shli_vec(vece, t, a, sh);
343
+ tcg_gen_and_vec(vece, d, d, m);
344
+ tcg_gen_or_vec(vece, d, d, t);
345
+
346
+ tcg_temp_free_vec(t);
347
+ tcg_temp_free_vec(m);
348
+ }
349
+}
350
+
351
+const GVecGen2i sli_op[4] = {
352
+ { .fni8 = gen_shl8_ins_i64,
353
+ .fniv = gen_shl_ins_vec,
354
+ .load_dest = true,
355
+ .opc = INDEX_op_shli_vec,
356
+ .vece = MO_8 },
357
+ { .fni8 = gen_shl16_ins_i64,
358
+ .fniv = gen_shl_ins_vec,
359
+ .load_dest = true,
360
+ .opc = INDEX_op_shli_vec,
361
+ .vece = MO_16 },
362
+ { .fni4 = gen_shl32_ins_i32,
363
+ .fniv = gen_shl_ins_vec,
364
+ .load_dest = true,
365
+ .opc = INDEX_op_shli_vec,
366
+ .vece = MO_32 },
367
+ { .fni8 = gen_shl64_ins_i64,
368
+ .fniv = gen_shl_ins_vec,
369
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
370
+ .load_dest = true,
371
+ .opc = INDEX_op_shli_vec,
372
+ .vece = MO_64 },
373
+};
374
+
375
/* Translate a NEON data processing instruction. Return nonzero if the
376
instruction is invalid.
377
We process data in a mixture of 32-bit and 64-bit chunks.
378
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
379
int pairwise;
380
int u;
381
int vec_size;
382
- uint32_t imm, mask;
383
+ uint32_t imm;
384
TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
385
TCGv_ptr ptr1, ptr2, ptr3;
386
TCGv_i64 tmp64;
387
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
388
}
389
return 0;
390
391
+ case 4: /* VSRI */
392
+ if (!u) {
393
+ return 1;
394
+ }
395
+ /* Right shift comes here negative. */
396
+ shift = -shift;
397
+ /* Shift out of range leaves destination unchanged. */
398
+ if (shift < 8 << size) {
399
+ tcg_gen_gvec_2i(rd_ofs, rm_ofs, vec_size, vec_size,
400
+ shift, &sri_op[size]);
401
+ }
402
+ return 0;
403
+
404
case 5: /* VSHL, VSLI */
405
- if (!u) { /* VSHL */
406
+ if (u) { /* VSLI */
407
+ /* Shift out of range leaves destination unchanged. */
408
+ if (shift < 8 << size) {
409
+ tcg_gen_gvec_2i(rd_ofs, rm_ofs, vec_size,
410
+ vec_size, shift, &sli_op[size]);
411
+ }
412
+ } else { /* VSHL */
413
/* Shifts larger than the element size are
414
* architecturally valid and results in zero.
415
*/
416
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
417
tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
418
vec_size, vec_size);
419
}
420
- return 0;
421
}
422
- break;
423
+ return 0;
424
}
425
426
if (size == 3) {
427
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
428
else
429
gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
430
break;
431
- case 4: /* VSRI */
432
- case 5: /* VSHL, VSLI */
433
- gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
434
- break;
435
case 6: /* VQSHLU */
436
gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
437
cpu_V0, cpu_V1);
438
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
439
/* Accumulate. */
440
neon_load_reg64(cpu_V1, rd + pass);
441
tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
442
- } else if (op == 4 || (op == 5 && u)) {
443
- /* Insert */
444
- neon_load_reg64(cpu_V1, rd + pass);
445
- uint64_t mask;
446
- if (shift < -63 || shift > 63) {
447
- mask = 0;
448
- } else {
449
- if (op == 4) {
450
- mask = 0xffffffffffffffffull >> -shift;
451
- } else {
452
- mask = 0xffffffffffffffffull << shift;
453
- }
454
- }
455
- tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
456
- tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
457
}
458
neon_store_reg64(cpu_V0, rd + pass);
459
} else { /* size < 3 */
460
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
461
case 3: /* VRSRA */
462
GEN_NEON_INTEGER_OP(rshl);
463
break;
464
- case 4: /* VSRI */
465
- case 5: /* VSHL, VSLI */
466
- switch (size) {
467
- case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
468
- case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
469
- case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
470
- default: abort();
471
- }
472
- break;
473
case 6: /* VQSHLU */
474
switch (size) {
475
case 0:
476
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
477
tmp2 = neon_load_reg(rd, pass);
478
gen_neon_add(size, tmp, tmp2);
479
tcg_temp_free_i32(tmp2);
480
- } else if (op == 4 || (op == 5 && u)) {
481
- /* Insert */
482
- switch (size) {
483
- case 0:
484
- if (op == 4)
485
- mask = 0xff >> -shift;
486
- else
487
- mask = (uint8_t)(0xff << shift);
488
- mask |= mask << 8;
489
- mask |= mask << 16;
490
- break;
491
- case 1:
492
- if (op == 4)
493
- mask = 0xffff >> -shift;
494
- else
495
- mask = (uint16_t)(0xffff << shift);
496
- mask |= mask << 16;
497
- break;
498
- case 2:
499
- if (shift < -31 || shift > 31) {
500
- mask = 0;
501
- } else {
502
- if (op == 4)
503
- mask = 0xffffffffu >> -shift;
504
- else
505
- mask = 0xffffffffu << shift;
506
- }
507
- break;
508
- default:
509
- abort();
510
- }
511
- tmp2 = neon_load_reg(rd, pass);
512
- tcg_gen_andi_i32(tmp, tmp, mask);
513
- tcg_gen_andi_i32(tmp2, tmp2, ~mask);
514
- tcg_gen_or_i32(tmp, tmp, tmp2);
515
- tcg_temp_free_i32(tmp2);
516
}
517
neon_store_reg(rd, pass, tmp);
518
}
519
--
520
2.19.1
521
522
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.