This edition moves some of the system registers into a substructure,
which is then shared with "normal" runtime and the translators.
This is seen as a better solution than letting the entire translator
have access to the main ARMCPU structure.

Also after rebasing on mainline, there was a new cortex-m33 failure
caused by v8m implying v7ve implying arm_div.


r~


Richard Henderson (8):
  target/arm: Move some system registers into a substructure
  target/arm: V8M should not imply V7VE
  target/arm: Convert v8 extensions from feature bits to isar tests
  target/arm: Convert division from feature bits to isar0 tests
  target/arm: Convert jazelle from feature bit to isar1 test
  target/arm: Convert t32ee from feature bit to isar3 test
  target/arm: Convert sve from feature bit to aa64pfr0 test
  target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test

 target/arm/cpu.h            | 220 +++++++++++++++++++++++++++-----
 target/arm/translate.h      |   7 ++
 hw/intc/armv7m_nvic.c       |  12 +-
 linux-user/aarch64/signal.c |   4 +-
 linux-user/elfload.c        |  60 +++++----
 linux-user/syscall.c        |  10 +-
 target/arm/cpu.c            | 242 +++++++++++++++++++-----------------
 target/arm/cpu64.c          | 148 ++++++++++++----------
 target/arm/helper.c         |  41 +++---
 target/arm/machine.c        |   6 +-
 target/arm/translate-a64.c  | 145 +++++++++++----------
 target/arm/translate.c      |  48 ++++---
 12 files changed, 570 insertions(+), 373 deletions(-)

-- 
2.17.2

On 16 October 2018 at 23:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
> This edition moves some of the system registers into a substructure,
> which is then shared with "normal" runtime and the translators.
> This is seen as a better solution than letting the entire translator
> have access to the main ARMCPU structure.
>
> Also after rebasing on mainline, there was a new cortex-m33 failure
> caused by v8m implying v7ve implying arm_div.
>



Applied to target-arm.next, thanks.

-- PMM