[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 0/9] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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This one's almost all docs fixes.
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caused new clang sanitizer warnings.
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2
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thanks
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-- PMM
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-- PMM
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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The following changes since commit ba54a7e6b86884e43bed2d2f5a79c719059652a8:
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-11-26 14:06:40 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241126
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to d8790ead55a2ef1e65332ebec63ae3c5db598942:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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docs/system/arm/aspeed: add missing model supermicrox11spi-bmc (2024-11-26 16:22:38 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* docs/system/arm: Fix broken links and missing feature names
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* target/arm: Define fields of ISAR registers
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* target/arm: Align cortex-r5 id_isar0
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* target/arm: Fix cortex-a7 id_isar0
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* net/cadence_gem: Fix various bugs, add support for new
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features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Michael Tokarev (1):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
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target/arm: Mask PMOVSR writes based on supported counters
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Edgar E. Iglesias (8):
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Pierrick Bouvier (8):
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net: cadence_gem: Disable TSU feature bit
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docs/system/arm/emulation: mention armv9
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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docs/system/arm/emulation: fix typo in feature name
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net: cadence_gem: Add macro with max number of descriptor words
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docs/system/arm/emulation: add FEAT_SSBS2
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net: cadence_gem: Add support for extended descriptors
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target/arm/tcg/: fix typo in FEAT name
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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docs/system/arm/: add FEAT_MTE_ASYNC
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net: cadence_gem: Implement support for 64bit descriptor addresses
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docs/system/arm/: add FEAT_DoubleLock
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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docs/system/arm/fby35: update link to product page
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target/arm: Add the Cortex-A72
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docs/system/arm/aspeed: add missing model supermicrox11spi-bmc
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Jerome Forissier (1):
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docs/system/arm/aspeed.rst | 7 ++++---
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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docs/system/arm/emulation.rst | 11 +++++++----
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docs/system/arm/fby35.rst | 2 +-
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Peter Maydell (2):
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target/arm/tcg/cpu32.c | 6 +++---
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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4 files changed, 15 insertions(+), 11 deletions(-)
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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Richard Henderson (4):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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diff view generated by jsdifflib
New patch
[PULL 1/9] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
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From: Michael Tokarev <mjt@tls.msk.ru>
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According to Cortex-R5 r1p2 manual, register with opcode2=0 is
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BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
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qemu labels them. Just swap the labels to avoid confusion, -
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both registers are implemented as always-zero.
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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241121171602.3273252-1-mjt@tls.msk.ru
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/tcg/cpu32.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/tcg/cpu32.c
19
+++ b/target/arm/tcg/cpu32.c
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@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
21
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static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
23
/* Dummy the TCM region regs for the moment */
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- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
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+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST },
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- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
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+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST },
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{ .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
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.opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
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--
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2.34.1
diff view generated by jsdifflib
New patch
[PULL 2/9] docs/system/arm/emulation: mention armv9
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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241122225049.1617774-2-pierrick.bouvier@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/system/arm/emulation.rst | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
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index XXXXXXX..XXXXXXX 100644
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--- a/docs/system/arm/emulation.rst
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+++ b/docs/system/arm/emulation.rst
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@@ -XXX,XX +XXX,XX @@
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A-profile CPU architecture support
17
==================================
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-QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and
20
-Armv8 versions of the A-profile architecture. It also has support for
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+QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7,
22
+Armv8 and Armv9 versions of the A-profile architecture. It also has support for
23
the following architecture extensions:
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- FEAT_AA32BF16 (AArch32 BFloat16 instructions)
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@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
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- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
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For information on the specifics of these extensions, please refer
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-to the `Armv8-A Arm Architecture Reference Manual
31
+to the `Arm Architecture Reference Manual for A-profile architecture
32
<https://developer.arm.com/documentation/ddi0487/latest>`_.
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When a specific named CPU is being emulated, only those features which
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--
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2.34.1
diff view generated by jsdifflib
New patch
[PULL 3/9] docs/system/arm/emulation: fix typo in feature name
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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241122225049.1617774-3-pierrick.bouvier@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/system/arm/emulation.rst | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
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index XXXXXXX..XXXXXXX 100644
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--- a/docs/system/arm/emulation.rst
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+++ b/docs/system/arm/emulation.rst
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@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
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- FEAT_LSE2 (Large System Extensions v2)
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- FEAT_LVA (Large Virtual Address space)
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- FEAT_MixedEnd (Mixed-endian support)
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-- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
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+- FEAT_MixedEndEL0 (Mixed-endian support at EL0)
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- FEAT_MOPS (Standardization of memory operations)
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- FEAT_MTE (Memory Tagging Extension)
23
- FEAT_MTE2 (Memory Tagging Extension)
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--
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2.34.1
diff view generated by jsdifflib
New patch
[PULL 4/9] docs/system/arm/emulation: add FEAT_SSBS2
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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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We implemented this at the same times as FEAT_SSBS, but forgot
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to list it in the documentation.
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Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241122225049.1617774-4-pierrick.bouvier@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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[PMM: improve commit message]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/system/arm/emulation.rst | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
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index XXXXXXX..XXXXXXX 100644
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--- a/docs/system/arm/emulation.rst
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+++ b/docs/system/arm/emulation.rst
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@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
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- FEAT_SVE2 (Scalable Vector Extension version 2)
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- FEAT_SPECRES (Speculation restriction instructions)
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- FEAT_SSBS (Speculative Store Bypass Safe)
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+- FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2)
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- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
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- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
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- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
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--
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2.34.1
diff view generated by jsdifflib
New patch
[PULL 5/9] target/arm/tcg/: fix typo in FEAT name
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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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2
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Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241122225049.1617774-5-pierrick.bouvier@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/tcg/cpu32.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/tcg/cpu32.c
15
+++ b/target/arm/tcg/cpu32.c
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@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
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cpu->isar.id_mmfr5 = t;
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t = cpu->isar.id_pfr0;
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- t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
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+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
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t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
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t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
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cpu->isar.id_pfr0 = t;
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--
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2.34.1
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diff view generated by jsdifflib
New patch
[PULL 6/9] docs/system/arm/: add FEAT_MTE_ASYNC
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From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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2
3
We already implement FEAT_MTE_ASYNC; we just forgot to list it
4
in the documentation.
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Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20241122225049.1617774-6-pierrick.bouvier@linaro.org
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[PMM: expand commit message]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/system/arm/emulation.rst | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
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index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/arm/emulation.rst
18
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
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- FEAT_MTE2 (Memory Tagging Extension)
21
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
22
- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
23
+- FEAT_MTE_ASYNC (Asynchronous reporting of Tag Check Fault)
24
- FEAT_NMI (Non-maskable Interrupt)
25
- FEAT_NV (Nested Virtualization)
26
- FEAT_NV2 (Enhanced nested virtualization support)
27
--
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2.34.1
diff view generated by jsdifflib
New patch
[PULL 7/9] docs/system/arm/: add FEAT_DoubleLock
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when
4
the ID registers call for it. This feature is actually one that must
5
*not* be implemented in v9.0, but since our documentation lists
6
everything we can emulate, we should include FEAT_DoubleLock in the
7
list.
8
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Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Message-id: 20241122225049.1617774-7-pierrick.bouvier@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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[PMM: expand commit message]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/system/arm/emulation.rst | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
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index XXXXXXX..XXXXXXX 100644
20
--- a/docs/system/arm/emulation.rst
21
+++ b/docs/system/arm/emulation.rst
22
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
23
- FEAT_CSV3 (Cache speculation variant 3)
24
- FEAT_DGH (Data gathering hint)
25
- FEAT_DIT (Data Independent Timing instructions)
26
+- FEAT_DoubleLock (Double Lock)
27
- FEAT_DPB (DC CVAP instruction)
28
- FEAT_DPB2 (DC CVADP instruction)
29
- FEAT_Debugv8p1 (Debug with VHE)
30
--
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2.34.1
diff view generated by jsdifflib
New patch
[PULL 8/9] docs/system/arm/fby35: update link to product page
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Message-id: 20241122225049.1617774-8-pierrick.bouvier@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/system/arm/fby35.rst | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst
14
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/system/arm/fby35.rst
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+++ b/docs/system/arm/fby35.rst
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@@ -XXX,XX +XXX,XX @@ include various compute accelerators (video, inferencing, etc). At the moment,
18
only the first server slot's BIC is included.
19
20
Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds
21
-can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__
22
+can be fit into a chassis. See `here <https://www.opencompute.org/products-chiplets/237/wiwynn-yosemite-v3-server>`__
23
for an example.
24
25
In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC
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--
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2.34.1
28
29
diff view generated by jsdifflib
New patch
[PULL 9/9] docs/system/arm/aspeed: add missing model supermicrox11spi-bmc
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
5
Message-id: 20241122225049.1617774-13-pierrick.bouvier@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/system/arm/aspeed.rst | 7 ++++---
9
1 file changed, 4 insertions(+), 3 deletions(-)
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diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
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index XXXXXXX..XXXXXXX 100644
13
--- a/docs/system/arm/aspeed.rst
14
+++ b/docs/system/arm/aspeed.rst
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@@ -XXX,XX +XXX,XX @@
16
-Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
17
-========================================================================================================================================================================================================================================================================================================================================================================================================
18
+Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
19
+==================================================================================================================================================================================================================================================================================================================================================================================================================================
20
21
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
22
Aspeed evaluation boards. They are based on different releases of the
23
@@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines :
24
25
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
26
- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
27
-- ``supermicrox11-bmc`` Supermicro X11 BMC
28
+- ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
29
+- ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
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31
AST2500 SoC based machines :
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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