| 1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | v2: added a missing #include qemu/error-report.h which only causes |
|---|---|---|---|
| 2 | caused new clang sanitizer warnings. | 2 | build failure in some configs, not all. |
| 3 | 3 | ||
| 4 | -- PMM | 4 | The following changes since commit 853546f8128476eefb701d4a55b2781bb3a46faa: |
| 5 | 5 | ||
| 6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 6 | Merge tag 'pull-loongarch-20240322' of https://gitlab.com/gaosong/qemu into staging (2024-03-22 10:59:57 +0000) |
| 7 | |||
| 8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | ||
| 9 | 7 | ||
| 10 | are available in the Git repository at: | 8 | are available in the Git repository at: |
| 11 | 9 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 10 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240325-1 |
| 13 | 11 | ||
| 14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 12 | for you to fetch changes up to fe3e38390126c2202292911c49d46fc7ee4a163a: |
| 15 | 13 | ||
| 16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 14 | tests/qtest/libqtest.c: Check for g_setenv() failure (2024-03-25 14:17:07 +0000) |
| 17 | 15 | ||
| 18 | ---------------------------------------------------------------- | 16 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 17 | target-arm queue: |
| 20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 18 | * Fixes for seven minor coverity issues |
| 21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | ||
| 22 | * target/arm: Define fields of ISAR registers | ||
| 23 | * target/arm: Align cortex-r5 id_isar0 | ||
| 24 | * target/arm: Fix cortex-a7 id_isar0 | ||
| 25 | * net/cadence_gem: Fix various bugs, add support for new | ||
| 26 | features that will be used by the Xilinx Versal board | ||
| 27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 28 | * target/arm: Add the Cortex-A72 | ||
| 29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | ||
| 30 | * target/arm: Mask PMOVSR writes based on supported counters | ||
| 31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 33 | 19 | ||
| 34 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 35 | Aaron Lindsay (2): | 21 | Peter Maydell (7): |
| 36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 22 | tests/qtest/npcm7xx_emc_test: Don't leak cmd_line |
| 37 | target/arm: Mask PMOVSR writes based on supported counters | 23 | tests/unit/socket-helpers: Don't close(-1) |
| 24 | net/af-xdp.c: Don't leak sock_fds array in net_init_af_xdp() | ||
| 25 | hw/misc/pca9554: Correct error check bounds in get/set pin functions | ||
| 26 | hw/nvram/mac_nvram: Report failure to write data | ||
| 27 | tests/unit/test-throttle: Avoid unintended integer division | ||
| 28 | tests/qtest/libqtest.c: Check for g_setenv() failure | ||
| 38 | 29 | ||
| 39 | Edgar E. Iglesias (8): | 30 | hw/misc/pca9554.c | 4 ++-- |
| 40 | net: cadence_gem: Disable TSU feature bit | 31 | hw/nvram/mac_nvram.c | 6 +++++- |
| 41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | 32 | net/af-xdp.c | 3 +-- |
| 42 | net: cadence_gem: Add macro with max number of descriptor words | 33 | tests/qtest/libqtest.c | 6 +++++- |
| 43 | net: cadence_gem: Add support for extended descriptors | 34 | tests/qtest/npcm7xx_emc-test.c | 4 ++-- |
| 44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | 35 | tests/unit/socket-helpers.c | 4 +++- |
| 45 | net: cadence_gem: Implement support for 64bit descriptor addresses | 36 | tests/unit/test-throttle.c | 4 ++-- |
| 46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | 37 | 7 files changed, 20 insertions(+), 11 deletions(-) |
| 47 | target/arm: Add the Cortex-A72 | ||
| 48 | |||
| 49 | Jerome Forissier (1): | ||
| 50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | ||
| 51 | |||
| 52 | Peter Maydell (2): | ||
| 53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 55 | |||
| 56 | Richard Henderson (4): | ||
| 57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | ||
| 58 | target/arm: Define fields of ISAR registers | ||
| 59 | target/arm: Align cortex-r5 id_isar0 | ||
| 60 | target/arm: Fix cortex-a7 id_isar0 | ||
| 61 | |||
| 62 | include/hw/net/cadence_gem.h | 7 +- | ||
| 63 | target/arm/cpu.h | 95 ++++++++++++++- | ||
| 64 | hw/arm/virt.c | 4 + | ||
| 65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | ||
| 66 | target/arm/arm-powerctl.c | 10 ++ | ||
| 67 | target/arm/cpu.c | 7 +- | ||
| 68 | target/arm/cpu64.c | 66 +++++++++- | ||
| 69 | target/arm/helper.c | 27 +++-- | ||
| 70 | target/arm/op_helper.c | 6 +- | ||
| 71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | ||
| 72 | 10 files changed, 402 insertions(+), 70 deletions(-) | ||
| 73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | ||
| 74 | diff view generated by jsdifflib |