[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 00/41] target-arm queue
1
v2: dropped a couple of cadence_gem changes to ID regs that
1
Hi; here's the latest target-arm queue. Mostly this is refactoring
2
caused new clang sanitizer warnings.
2
and cleanup type patches.
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3
4
thanks
4
-- PMM
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-- PMM
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6
6
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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The following changes since commit c60be6e3e38cb36dc66129e757ec4b34152232be:
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging (2023-10-27 09:43:53 +0900)
9
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are available in the Git repository at:
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are available in the Git repository at:
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12
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to df93de987f423a0ed918c425f5dbd9a25d3c6229:
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16
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
17
hw/net/cadence_gem: enforce 32 bits variable size for CRC (2023-10-27 15:27:06 +0100)
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18
18
----------------------------------------------------------------
19
----------------------------------------------------------------
19
target-arm queue:
20
target-arm queue:
20
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
21
* Correct minor errors in Cortex-A710 definition
21
* target/arm: Fix aarch64_sve_change_el wrt EL0
22
* Implement Neoverse N2 CPU model
22
* target/arm: Define fields of ISAR registers
23
* Refactor feature test functions out into separate header
23
* target/arm: Align cortex-r5 id_isar0
24
* Fix syndrome for FGT traps on ERET
24
* target/arm: Fix cortex-a7 id_isar0
25
* Remove 'hw/arm/boot.h' includes from various header files
25
* net/cadence_gem: Fix various bugs, add support for new
26
* pxa2xx: Refactoring/cleanup
26
features that will be used by the Xilinx Versal board
27
* Avoid using 'first_cpu' when first ARM CPU is reachable
27
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
28
* misc/led: LED state is set opposite of what is expected
28
* target/arm: Add the Cortex-A72
29
* hw/net/cadence_gen: clean up to use FIELD macros
29
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
30
* hw/net/cadence_gem: perform PHY access on write only
30
* target/arm: Mask PMOVSR writes based on supported counters
31
* hw/net/cadence_gem: enforce 32 bits variable size for CRC
31
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
32
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
33
32
34
----------------------------------------------------------------
33
----------------------------------------------------------------
35
Aaron Lindsay (2):
34
Glenn Miles (1):
36
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
35
misc/led: LED state is set opposite of what is expected
37
target/arm: Mask PMOVSR writes based on supported counters
38
36
39
Edgar E. Iglesias (8):
37
Luc Michel (11):
40
net: cadence_gem: Disable TSU feature bit
38
hw/net/cadence_gem: use REG32 macro for register definitions
41
net: cadence_gem: Use uint32_t for 32bit descriptor words
39
hw/net/cadence_gem: use FIELD for screening registers
42
net: cadence_gem: Add macro with max number of descriptor words
40
hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
43
net: cadence_gem: Add support for extended descriptors
41
hw/net/cadence_gem: use FIELD to describe NWCFG register fields
44
net: cadence_gem: Add support for selecting the DMA MemoryRegion
42
hw/net/cadence_gem: use FIELD to describe DMACFG register fields
45
net: cadence_gem: Implement support for 64bit descriptor addresses
43
hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
46
target-arm: powerctl: Enable HVC when starting CPUs to EL2
44
hw/net/cadence_gem: use FIELD to describe IRQ register fields
47
target/arm: Add the Cortex-A72
45
hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
46
hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
47
hw/net/cadence_gem: perform PHY access on write only
48
hw/net/cadence_gem: enforce 32 bits variable size for CRC
48
49
49
Jerome Forissier (1):
50
Peter Maydell (9):
50
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
51
target/arm: Correct minor errors in Cortex-A710 definition
52
target/arm: Implement Neoverse N2 CPU model
53
target/arm: Move feature test functions to their own header
54
target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together
55
target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2
56
target/arm: Move ID_AA64ISAR* test functions together
57
target/arm: Move ID_AA64PFR* tests together
58
target/arm: Move ID_AA64DFR* feature tests together
59
target/arm: Fix syndrome for FGT traps on ERET
51
60
52
Peter Maydell (2):
61
Philippe Mathieu-Daudé (20):
53
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
62
hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header
54
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
63
hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header
64
hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header
65
hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header
66
hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header
67
hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header
68
hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header
69
hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header
70
hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
71
hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header
72
hw/sd/pxa2xx: Realize sysbus device before accessing it
73
hw/sd/pxa2xx: Do not open-code sysbus_create_simple()
74
hw/pcmcia/pxa2xx: Realize sysbus device before accessing it
75
hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()
76
hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()
77
hw/intc/pxa2xx: Convert to Resettable interface
78
hw/intc/pxa2xx: Pass CPU reference using QOM link property
79
hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()
80
hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it
81
hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable
55
82
56
Richard Henderson (4):
83
docs/system/arm/virt.rst | 1 +
57
target/arm: Fix aarch64_sve_change_el wrt EL0
84
bsd-user/arm/target_arch.h | 1 +
58
target/arm: Define fields of ISAR registers
85
include/hw/arm/allwinner-a10.h | 1 -
59
target/arm: Align cortex-r5 id_isar0
86
include/hw/arm/allwinner-h3.h | 1 -
60
target/arm: Fix cortex-a7 id_isar0
87
include/hw/arm/allwinner-r40.h | 1 -
88
include/hw/arm/fsl-imx25.h | 1 -
89
include/hw/arm/fsl-imx31.h | 1 -
90
include/hw/arm/fsl-imx6.h | 1 -
91
include/hw/arm/fsl-imx6ul.h | 1 -
92
include/hw/arm/fsl-imx7.h | 1 -
93
include/hw/arm/pxa.h | 2 -
94
include/hw/arm/xlnx-versal.h | 1 -
95
include/hw/arm/xlnx-zynqmp.h | 1 -
96
linux-user/aarch64/target_prctl.h | 2 +
97
target/arm/cpu-features.h | 994 ++++++++++++++++++++++++++++++++++++++
98
target/arm/cpu.h | 971 -------------------------------------
99
target/arm/internals.h | 1 +
100
target/arm/tcg/translate.h | 2 +-
101
hw/arm/armv7m.c | 1 +
102
hw/arm/bananapi_m2u.c | 3 +-
103
hw/arm/cubieboard.c | 1 +
104
hw/arm/exynos4_boards.c | 7 +-
105
hw/arm/imx25_pdk.c | 1 +
106
hw/arm/kzm.c | 1 +
107
hw/arm/mcimx6ul-evk.c | 1 +
108
hw/arm/mcimx7d-sabre.c | 1 +
109
hw/arm/orangepi.c | 3 +-
110
hw/arm/pxa2xx.c | 17 +-
111
hw/arm/pxa2xx_pic.c | 38 +-
112
hw/arm/realview.c | 2 +-
113
hw/arm/sabrelite.c | 1 +
114
hw/arm/sbsa-ref.c | 1 +
115
hw/arm/virt.c | 1 +
116
hw/arm/xilinx_zynq.c | 2 +-
117
hw/arm/xlnx-versal-virt.c | 1 +
118
hw/arm/xlnx-zcu102.c | 1 +
119
hw/intc/armv7m_nvic.c | 1 +
120
hw/misc/led.c | 2 +-
121
hw/net/cadence_gem.c | 884 ++++++++++++++++++---------------
122
hw/pcmcia/pxa2xx.c | 15 -
123
hw/sd/pxa2xx_mmci.c | 7 +-
124
linux-user/aarch64/cpu_loop.c | 1 +
125
linux-user/aarch64/signal.c | 1 +
126
linux-user/arm/signal.c | 1 +
127
linux-user/elfload.c | 4 +
128
linux-user/mmap.c | 4 +
129
target/arm/arch_dump.c | 1 +
130
target/arm/cpu.c | 1 +
131
target/arm/cpu64.c | 1 +
132
target/arm/debug_helper.c | 1 +
133
target/arm/gdbstub.c | 1 +
134
target/arm/helper.c | 1 +
135
target/arm/kvm64.c | 1 +
136
target/arm/machine.c | 1 +
137
target/arm/ptw.c | 1 +
138
target/arm/tcg/cpu64.c | 115 ++++-
139
target/arm/tcg/hflags.c | 1 +
140
target/arm/tcg/m_helper.c | 1 +
141
target/arm/tcg/op_helper.c | 1 +
142
target/arm/tcg/pauth_helper.c | 1 +
143
target/arm/tcg/tlb_helper.c | 1 +
144
target/arm/tcg/translate-a64.c | 4 +-
145
target/arm/vfp_helper.c | 1 +
146
63 files changed, 1702 insertions(+), 1419 deletions(-)
147
create mode 100644 target/arm/cpu-features.h
61
148
62
include/hw/net/cadence_gem.h | 7 +-
63
target/arm/cpu.h | 95 ++++++++++++++-
64
hw/arm/virt.c | 4 +
65
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
66
target/arm/arm-powerctl.c | 10 ++
67
target/arm/cpu.c | 7 +-
68
target/arm/cpu64.c | 66 +++++++++-
69
target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
71
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
72
10 files changed, 402 insertions(+), 70 deletions(-)
73
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
74
diff view generated by jsdifflib
New patch
[PULL 01/41] target/arm: Correct minor errors in Cortex-A710 definition
1
Correct a couple of minor errors in the Cortex-A710 definition:
2
* ID_AA64DFR0_EL1.DebugVer is 9 (indicating Armv8.4 debug architecture)
3
* ID_AA64ISAR1_EL1.APA is 5 (indicating more PAuth support)
4
* there is an IMPDEF CPUCFR_EL1, like that on the Neoverse-N1
1
5
6
Fixes: e3d45c0a89576 ("target/arm: Implement cortex-a710")
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20230915185453.1871167-2-peter.maydell@linaro.org
11
---
12
target/arm/tcg/cpu64.c | 11 +++++++++--
13
1 file changed, 9 insertions(+), 2 deletions(-)
14
15
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/tcg/cpu64.c
18
+++ b/target/arm/tcg/cpu64.c
19
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cortex_a710_cp_reginfo[] = {
20
{ .name = "CPUPFR_EL3", .state = ARM_CP_STATE_AA64,
21
.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 6,
22
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
23
+ /*
24
+ * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
25
+ * (and in particular its system registers).
26
+ */
27
+ { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
28
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
29
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
30
31
/*
32
* Stub RAMINDEX, as we don't actually implement caches, BTB,
33
@@ -XXX,XX +XXX,XX @@ static void aarch64_a710_initfn(Object *obj)
34
cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
35
cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
36
cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
37
- cpu->isar.id_aa64dfr0 = 0x000011f010305611ull;
38
+ cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
39
cpu->isar.id_aa64dfr1 = 0;
40
cpu->id_aa64afr0 = 0;
41
cpu->id_aa64afr1 = 0;
42
cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
43
- cpu->isar.id_aa64isar1 = 0x0010111101211032ull;
44
+ cpu->isar.id_aa64isar1 = 0x0010111101211052ull;
45
cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
46
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
47
cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull;
48
--
49
2.34.1
50
51
diff view generated by jsdifflib
New patch
[PULL 02/41] target/arm: Implement Neoverse N2 CPU model
1
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A
2
processor very similar to the Cortex-A710. The differences are:
3
* no FEAT_EVT
4
* FEAT_DGH (data gathering hint)
5
* FEAT_NV (not yet implemented in QEMU)
6
* Statistical Profiling Extension (not implemented in QEMU)
7
* 48 bit physical address range, not 40
8
* CTR_EL0.DIC = 1 (no explicit icache cleaning needed)
9
* PMCR_EL0.N = 6 (always 6 PMU counters, not 20)
1
10
11
Because it has 48-bit physical address support, we can use
12
this CPU in the sbsa-ref board as well as the virt board.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
16
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
17
Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org
18
---
19
docs/system/arm/virt.rst | 1 +
20
hw/arm/sbsa-ref.c | 1 +
21
hw/arm/virt.c | 1 +
22
target/arm/tcg/cpu64.c | 103 +++++++++++++++++++++++++++++++++++++++
23
4 files changed, 106 insertions(+)
24
25
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
26
index XXXXXXX..XXXXXXX 100644
27
--- a/docs/system/arm/virt.rst
28
+++ b/docs/system/arm/virt.rst
29
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
30
- ``host`` (with KVM only)
31
- ``neoverse-n1`` (64-bit)
32
- ``neoverse-v1`` (64-bit)
33
+- ``neoverse-n2`` (64-bit)
34
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
35
36
Note that the default is ``cortex-a15``, so for an AArch64 guest you must
37
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/sbsa-ref.c
40
+++ b/hw/arm/sbsa-ref.c
41
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
42
ARM_CPU_TYPE_NAME("cortex-a72"),
43
ARM_CPU_TYPE_NAME("neoverse-n1"),
44
ARM_CPU_TYPE_NAME("neoverse-v1"),
45
+ ARM_CPU_TYPE_NAME("neoverse-n2"),
46
ARM_CPU_TYPE_NAME("max"),
47
};
48
49
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/arm/virt.c
52
+++ b/hw/arm/virt.c
53
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
54
ARM_CPU_TYPE_NAME("a64fx"),
55
ARM_CPU_TYPE_NAME("neoverse-n1"),
56
ARM_CPU_TYPE_NAME("neoverse-v1"),
57
+ ARM_CPU_TYPE_NAME("neoverse-n2"),
58
#endif
59
ARM_CPU_TYPE_NAME("cortex-a53"),
60
ARM_CPU_TYPE_NAME("cortex-a57"),
61
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/tcg/cpu64.c
64
+++ b/target/arm/tcg/cpu64.c
65
@@ -XXX,XX +XXX,XX @@ static void aarch64_a710_initfn(Object *obj)
66
aarch64_add_sve_properties(obj);
67
}
68
69
+/* Extra IMPDEF regs in the N2 beyond those in the A710 */
70
+static const ARMCPRegInfo neoverse_n2_cp_reginfo[] = {
71
+ { .name = "CPURNDBR_EL3", .state = ARM_CP_STATE_AA64,
72
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 0,
73
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
74
+ { .name = "CPURNDPEID_EL3", .state = ARM_CP_STATE_AA64,
75
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 1,
76
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
77
+};
78
+
79
+static void aarch64_neoverse_n2_initfn(Object *obj)
80
+{
81
+ ARMCPU *cpu = ARM_CPU(obj);
82
+
83
+ cpu->dtb_compatible = "arm,neoverse-n2";
84
+ set_feature(&cpu->env, ARM_FEATURE_V8);
85
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
86
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
87
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
88
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
89
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
90
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
91
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
92
+
93
+ /* Ordered by Section B.5: AArch64 ID registers */
94
+ cpu->midr = 0x410FD493; /* r0p3 */
95
+ cpu->revidr = 0;
96
+ cpu->isar.id_pfr0 = 0x21110131;
97
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
98
+ cpu->isar.id_dfr0 = 0x16011099;
99
+ cpu->id_afr0 = 0;
100
+ cpu->isar.id_mmfr0 = 0x10201105;
101
+ cpu->isar.id_mmfr1 = 0x40000000;
102
+ cpu->isar.id_mmfr2 = 0x01260000;
103
+ cpu->isar.id_mmfr3 = 0x02122211;
104
+ cpu->isar.id_isar0 = 0x02101110;
105
+ cpu->isar.id_isar1 = 0x13112111;
106
+ cpu->isar.id_isar2 = 0x21232042;
107
+ cpu->isar.id_isar3 = 0x01112131;
108
+ cpu->isar.id_isar4 = 0x00010142;
109
+ cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
110
+ cpu->isar.id_mmfr4 = 0x01021110;
111
+ cpu->isar.id_isar6 = 0x01111111;
112
+ cpu->isar.mvfr0 = 0x10110222;
113
+ cpu->isar.mvfr1 = 0x13211111;
114
+ cpu->isar.mvfr2 = 0x00000043;
115
+ cpu->isar.id_pfr2 = 0x00000011;
116
+ cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
117
+ cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
118
+ cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
119
+ cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
120
+ cpu->isar.id_aa64dfr1 = 0;
121
+ cpu->id_aa64afr0 = 0;
122
+ cpu->id_aa64afr1 = 0;
123
+ cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
124
+ cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
125
+ cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
126
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
127
+ cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull;
128
+ cpu->clidr = 0x0000001482000023ull;
129
+ cpu->gm_blocksize = 4;
130
+ cpu->ctr = 0x00000004b444c004ull;
131
+ cpu->dcz_blocksize = 4;
132
+ /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_001e_01ff */
133
+
134
+ /* Section B.7.2: PMCR_EL0 */
135
+ cpu->isar.reset_pmcr_el0 = 0x3000; /* with 6 counters */
136
+
137
+ /* Section B.8.9: ICH_VTR_EL2 */
138
+ cpu->gic_num_lrs = 4;
139
+ cpu->gic_vpribits = 5;
140
+ cpu->gic_vprebits = 5;
141
+ cpu->gic_pribits = 5;
142
+
143
+ /* Section 14: Scalable Vector Extensions support */
144
+ cpu->sve_vq.supported = 1 << 0; /* 128bit */
145
+
146
+ /*
147
+ * The Neoverse N2 TRM does not list CCSIDR values. The layout of
148
+ * the caches are in text in Table 7-1, Table 8-1, and Table 9-1.
149
+ *
150
+ * L1: 4-way set associative 64-byte line size, total 64K.
151
+ * L2: 8-way set associative 64 byte line size, total either 512K or 1024K.
152
+ */
153
+ cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
154
+ cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
155
+ cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */
156
+
157
+ /* FIXME: Not documented -- copied from neoverse-v1 */
158
+ cpu->reset_sctlr = 0x30c50838;
159
+
160
+ /*
161
+ * The Neoverse N2 has all of the Cortex-A710 IMPDEF registers,
162
+ * and a few more RNG related ones.
163
+ */
164
+ define_arm_cp_regs(cpu, cortex_a710_cp_reginfo);
165
+ define_arm_cp_regs(cpu, neoverse_n2_cp_reginfo);
166
+
167
+ aarch64_add_pauth_properties(obj);
168
+ aarch64_add_sve_properties(obj);
169
+}
170
+
171
/*
172
* -cpu max: a CPU with as many features enabled as our emulation supports.
173
* The version of '-cpu max' for qemu-system-arm is defined in cpu32.c;
174
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
175
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
176
{ .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
177
{ .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn },
178
+ { .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn },
179
};
180
181
static void aarch64_cpu_register_types(void)
182
--
183
2.34.1
184
185
diff view generated by jsdifflib
New patch
[PULL 03/41] target/arm: Move feature test functions to their own header
1
The feature test functions isar_feature_*() now take up nearly
2
a thousand lines in target/arm/cpu.h. This header file is included
3
by a lot of source files, most of which don't need these functions.
4
Move the feature test functions to their own header file.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
10
---
11
bsd-user/arm/target_arch.h | 1 +
12
linux-user/aarch64/target_prctl.h | 2 +
13
target/arm/cpu-features.h | 994 ++++++++++++++++++++++++++++++
14
target/arm/cpu.h | 971 -----------------------------
15
target/arm/internals.h | 1 +
16
target/arm/tcg/translate.h | 2 +-
17
hw/arm/armv7m.c | 1 +
18
hw/intc/armv7m_nvic.c | 1 +
19
linux-user/aarch64/cpu_loop.c | 1 +
20
linux-user/aarch64/signal.c | 1 +
21
linux-user/arm/signal.c | 1 +
22
linux-user/elfload.c | 4 +
23
linux-user/mmap.c | 4 +
24
target/arm/arch_dump.c | 1 +
25
target/arm/cpu.c | 1 +
26
target/arm/cpu64.c | 1 +
27
target/arm/debug_helper.c | 1 +
28
target/arm/gdbstub.c | 1 +
29
target/arm/helper.c | 1 +
30
target/arm/kvm64.c | 1 +
31
target/arm/machine.c | 1 +
32
target/arm/ptw.c | 1 +
33
target/arm/tcg/cpu64.c | 1 +
34
target/arm/tcg/hflags.c | 1 +
35
target/arm/tcg/m_helper.c | 1 +
36
target/arm/tcg/op_helper.c | 1 +
37
target/arm/tcg/pauth_helper.c | 1 +
38
target/arm/tcg/tlb_helper.c | 1 +
39
target/arm/vfp_helper.c | 1 +
40
29 files changed, 1028 insertions(+), 972 deletions(-)
41
create mode 100644 target/arm/cpu-features.h
42
43
diff --git a/bsd-user/arm/target_arch.h b/bsd-user/arm/target_arch.h
44
index XXXXXXX..XXXXXXX 100644
45
--- a/bsd-user/arm/target_arch.h
46
+++ b/bsd-user/arm/target_arch.h
47
@@ -XXX,XX +XXX,XX @@
48
#define TARGET_ARCH_H
49
50
#include "qemu.h"
51
+#include "target/arm/cpu-features.h"
52
53
void target_cpu_set_tls(CPUARMState *env, target_ulong newtls);
54
target_ulong target_cpu_get_tls(CPUARMState *env);
55
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/linux-user/aarch64/target_prctl.h
58
+++ b/linux-user/aarch64/target_prctl.h
59
@@ -XXX,XX +XXX,XX @@
60
#ifndef AARCH64_TARGET_PRCTL_H
61
#define AARCH64_TARGET_PRCTL_H
62
63
+#include "target/arm/cpu-features.h"
64
+
65
static abi_long do_prctl_sve_get_vl(CPUArchState *env)
66
{
67
ARMCPU *cpu = env_archcpu(env);
68
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
69
new file mode 100644
70
index XXXXXXX..XXXXXXX
71
--- /dev/null
72
+++ b/target/arm/cpu-features.h
73
@@ -XXX,XX +XXX,XX @@
74
+/*
75
+ * QEMU Arm CPU -- feature test functions
76
+ *
77
+ * Copyright (c) 2023 Linaro Ltd
78
+ *
79
+ * This library is free software; you can redistribute it and/or
80
+ * modify it under the terms of the GNU Lesser General Public
81
+ * License as published by the Free Software Foundation; either
82
+ * version 2.1 of the License, or (at your option) any later version.
83
+ *
84
+ * This library is distributed in the hope that it will be useful,
85
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
86
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
87
+ * Lesser General Public License for more details.
88
+ *
89
+ * You should have received a copy of the GNU Lesser General Public
90
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
91
+ */
92
+
93
+#ifndef TARGET_ARM_FEATURES_H
94
+#define TARGET_ARM_FEATURES_H
95
+
96
+/*
97
+ * Naming convention for isar_feature functions:
98
+ * Functions which test 32-bit ID registers should have _aa32_ in
99
+ * their name. Functions which test 64-bit ID registers should have
100
+ * _aa64_ in their name. These must only be used in code where we
101
+ * know for certain that the CPU has AArch32 or AArch64 respectively
102
+ * or where the correct answer for a CPU which doesn't implement that
103
+ * CPU state is "false" (eg when generating A32 or A64 code, if adding
104
+ * system registers that are specific to that CPU state, for "should
105
+ * we let this system register bit be set" tests where the 32-bit
106
+ * flavour of the register doesn't have the bit, and so on).
107
+ * Functions which simply ask "does this feature exist at all" have
108
+ * _any_ in their name, and always return the logical OR of the _aa64_
109
+ * and the _aa32_ function.
110
+ */
111
+
112
+/*
113
+ * 32-bit feature tests via id registers.
114
+ */
115
+static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
116
+{
117
+ return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
118
+}
119
+
120
+static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
121
+{
122
+ return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
123
+}
124
+
125
+static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
126
+{
127
+ /* (M-profile) low-overhead loops and branch future */
128
+ return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
129
+}
130
+
131
+static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
132
+{
133
+ return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
134
+}
135
+
136
+static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
137
+{
138
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
139
+}
140
+
141
+static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
142
+{
143
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
144
+}
145
+
146
+static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
147
+{
148
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
149
+}
150
+
151
+static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
152
+{
153
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
154
+}
155
+
156
+static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
157
+{
158
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
159
+}
160
+
161
+static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
162
+{
163
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
164
+}
165
+
166
+static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
167
+{
168
+ return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
169
+}
170
+
171
+static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
172
+{
173
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
174
+}
175
+
176
+static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
177
+{
178
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
179
+}
180
+
181
+static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
182
+{
183
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
184
+}
185
+
186
+static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
187
+{
188
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
189
+}
190
+
191
+static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
192
+{
193
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
194
+}
195
+
196
+static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
197
+{
198
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
199
+}
200
+
201
+static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
202
+{
203
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
204
+}
205
+
206
+static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
207
+{
208
+ return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
209
+}
210
+
211
+static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
212
+{
213
+ return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
214
+}
215
+
216
+static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
217
+{
218
+ /*
219
+ * Return true if M-profile state handling insns
220
+ * (VSCCLRM, CLRM, FPCTX access insns) are implemented
221
+ */
222
+ return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
223
+}
224
+
225
+static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
226
+{
227
+ /* Sadly this is encoded differently for A-profile and M-profile */
228
+ if (isar_feature_aa32_mprofile(id)) {
229
+ return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
230
+ } else {
231
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
232
+ }
233
+}
234
+
235
+static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
236
+{
237
+ /*
238
+ * Return true if MVE is supported (either integer or floating point).
239
+ * We must check for M-profile as the MVFR1 field means something
240
+ * else for A-profile.
241
+ */
242
+ return isar_feature_aa32_mprofile(id) &&
243
+ FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
244
+}
245
+
246
+static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
247
+{
248
+ /*
249
+ * Return true if MVE is supported (either integer or floating point).
250
+ * We must check for M-profile as the MVFR1 field means something
251
+ * else for A-profile.
252
+ */
253
+ return isar_feature_aa32_mprofile(id) &&
254
+ FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
255
+}
256
+
257
+static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
258
+{
259
+ /*
260
+ * Return true if either VFP or SIMD is implemented.
261
+ * In this case, a minimum of VFP w/ D0-D15.
262
+ */
263
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
264
+}
265
+
266
+static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
267
+{
268
+ /* Return true if D16-D31 are implemented */
269
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
270
+}
271
+
272
+static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
273
+{
274
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
275
+}
276
+
277
+static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
278
+{
279
+ /* Return true if CPU supports single precision floating point, VFPv2 */
280
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
281
+}
282
+
283
+static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
284
+{
285
+ /* Return true if CPU supports single precision floating point, VFPv3 */
286
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
287
+}
288
+
289
+static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
290
+{
291
+ /* Return true if CPU supports double precision floating point, VFPv2 */
292
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
293
+}
294
+
295
+static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
296
+{
297
+ /* Return true if CPU supports double precision floating point, VFPv3 */
298
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
299
+}
300
+
301
+static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
302
+{
303
+ return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
304
+}
305
+
306
+/*
307
+ * We always set the FP and SIMD FP16 fields to indicate identical
308
+ * levels of support (assuming SIMD is implemented at all), so
309
+ * we only need one set of accessors.
310
+ */
311
+static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
312
+{
313
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
314
+}
315
+
316
+static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
317
+{
318
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
319
+}
320
+
321
+/*
322
+ * Note that this ID register field covers both VFP and Neon FMAC,
323
+ * so should usually be tested in combination with some other
324
+ * check that confirms the presence of whichever of VFP or Neon is
325
+ * relevant, to avoid accidentally enabling a Neon feature on
326
+ * a VFP-no-Neon core or vice-versa.
327
+ */
328
+static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
329
+{
330
+ return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
331
+}
332
+
333
+static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
334
+{
335
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
336
+}
337
+
338
+static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
339
+{
340
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
341
+}
342
+
343
+static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
344
+{
345
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
346
+}
347
+
348
+static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
349
+{
350
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
351
+}
352
+
353
+static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
354
+{
355
+ return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
356
+}
357
+
358
+static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
359
+{
360
+ return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
361
+}
362
+
363
+static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
364
+{
365
+ return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
366
+}
367
+
368
+static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
369
+{
370
+ /* 0xf means "non-standard IMPDEF PMU" */
371
+ return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
372
+ FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
373
+}
374
+
375
+static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id)
376
+{
377
+ /* 0xf means "non-standard IMPDEF PMU" */
378
+ return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
379
+ FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
380
+}
381
+
382
+static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
383
+{
384
+ /* 0xf means "non-standard IMPDEF PMU" */
385
+ return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 &&
386
+ FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
387
+}
388
+
389
+static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
390
+{
391
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
392
+}
393
+
394
+static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
395
+{
396
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
397
+}
398
+
399
+static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
400
+{
401
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
402
+}
403
+
404
+static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
405
+{
406
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
407
+}
408
+
409
+static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
410
+{
411
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
412
+}
413
+
414
+static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
415
+{
416
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
417
+}
418
+
419
+static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
420
+{
421
+ return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
422
+}
423
+
424
+static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
425
+{
426
+ return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
427
+}
428
+
429
+static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
430
+{
431
+ return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5;
432
+}
433
+
434
+static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
435
+{
436
+ return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
437
+}
438
+
439
+static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
440
+{
441
+ return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0;
442
+}
443
+
444
+/*
445
+ * 64-bit feature tests via id registers.
446
+ */
447
+static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
448
+{
449
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
450
+}
451
+
452
+static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
453
+{
454
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
455
+}
456
+
457
+static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
458
+{
459
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
460
+}
461
+
462
+static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
463
+{
464
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
465
+}
466
+
467
+static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
468
+{
469
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
470
+}
471
+
472
+static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
473
+{
474
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
475
+}
476
+
477
+static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
478
+{
479
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
480
+}
481
+
482
+static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
483
+{
484
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
485
+}
486
+
487
+static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
488
+{
489
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
490
+}
491
+
492
+static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
493
+{
494
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
495
+}
496
+
497
+static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
498
+{
499
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
500
+}
501
+
502
+static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
503
+{
504
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
505
+}
506
+
507
+static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
508
+{
509
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
510
+}
511
+
512
+static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
513
+{
514
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
515
+}
516
+
517
+static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
518
+{
519
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
520
+}
521
+
522
+static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
523
+{
524
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
525
+}
526
+
527
+static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
528
+{
529
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
530
+}
531
+
532
+static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
533
+{
534
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
535
+}
536
+
537
+/*
538
+ * These are the values from APA/API/APA3.
539
+ * In general these must be compared '>=', per the normal Arm ARM
540
+ * treatment of fields in ID registers.
541
+ */
542
+typedef enum {
543
+ PauthFeat_None = 0,
544
+ PauthFeat_1 = 1,
545
+ PauthFeat_EPAC = 2,
546
+ PauthFeat_2 = 3,
547
+ PauthFeat_FPAC = 4,
548
+ PauthFeat_FPACCOMBINED = 5,
549
+} ARMPauthFeature;
550
+
551
+static inline ARMPauthFeature
552
+isar_feature_pauth_feature(const ARMISARegisters *id)
553
+{
554
+ /*
555
+ * Architecturally, only one of {APA,API,APA3} may be active (non-zero)
556
+ * and the other two must be zero. Thus we may avoid conditionals.
557
+ */
558
+ return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) |
559
+ FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) |
560
+ FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3));
561
+}
562
+
563
+static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
564
+{
565
+ /*
566
+ * Return true if any form of pauth is enabled, as this
567
+ * predicate controls migration of the 128-bit keys.
568
+ */
569
+ return isar_feature_pauth_feature(id) != PauthFeat_None;
570
+}
571
+
572
+static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id)
573
+{
574
+ /*
575
+ * Return true if pauth is enabled with the architected QARMA5 algorithm.
576
+ * QEMU will always enable or disable both APA and GPA.
577
+ */
578
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
579
+}
580
+
581
+static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
582
+{
583
+ /*
584
+ * Return true if pauth is enabled with the architected QARMA3 algorithm.
585
+ * QEMU will always enable or disable both APA3 and GPA3.
586
+ */
587
+ return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
588
+}
589
+
590
+static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
591
+{
592
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
593
+}
594
+
595
+static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
596
+{
597
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
598
+}
599
+
600
+static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
601
+{
602
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
603
+}
604
+
605
+static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
606
+{
607
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
608
+}
609
+
610
+static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
611
+{
612
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
613
+}
614
+
615
+static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
616
+{
617
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
618
+}
619
+
620
+static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
621
+{
622
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
623
+}
624
+
625
+static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
626
+{
627
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
628
+}
629
+
630
+static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
631
+{
632
+ /* We always set the AdvSIMD and FP fields identically. */
633
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
634
+}
635
+
636
+static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
637
+{
638
+ /* We always set the AdvSIMD and FP fields identically wrt FP16. */
639
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
640
+}
641
+
642
+static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
643
+{
644
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
645
+}
646
+
647
+static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
648
+{
649
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
650
+}
651
+
652
+static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
653
+{
654
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
655
+}
656
+
657
+static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
658
+{
659
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
660
+}
661
+
662
+static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id)
663
+{
664
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2;
665
+}
666
+
667
+static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
668
+{
669
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
670
+}
671
+
672
+static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
673
+{
674
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
675
+}
676
+
677
+static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
678
+{
679
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
680
+}
681
+
682
+static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
683
+{
684
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
685
+}
686
+
687
+static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
688
+{
689
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
690
+}
691
+
692
+static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
693
+{
694
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
695
+}
696
+
697
+static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
698
+{
699
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
700
+}
701
+
702
+static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
703
+{
704
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
705
+}
706
+
707
+static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
708
+{
709
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
710
+}
711
+
712
+static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
713
+{
714
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
715
+}
716
+
717
+static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
718
+{
719
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
720
+}
721
+
722
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
723
+{
724
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
725
+}
726
+
727
+static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id)
728
+{
729
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0;
730
+}
731
+
732
+static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
733
+{
734
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
735
+}
736
+
737
+static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
738
+{
739
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
740
+}
741
+
742
+static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
743
+{
744
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
745
+}
746
+
747
+static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
748
+{
749
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
750
+}
751
+
752
+static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
753
+{
754
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
755
+}
756
+
757
+static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
758
+{
759
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
760
+}
761
+
762
+static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
763
+{
764
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
765
+}
766
+
767
+static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
768
+{
769
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
770
+}
771
+
772
+static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
773
+{
774
+ return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
775
+ FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
776
+}
777
+
778
+static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
779
+{
780
+ return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
781
+ FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
782
+}
783
+
784
+static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
785
+{
786
+ return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
787
+ FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
788
+}
789
+
790
+static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
791
+{
792
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
793
+}
794
+
795
+static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
796
+{
797
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
798
+}
799
+
800
+static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
801
+{
802
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
803
+}
804
+
805
+static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
806
+{
807
+ return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
808
+}
809
+
810
+static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
811
+{
812
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
813
+}
814
+
815
+static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
816
+{
817
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
818
+ return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
819
+}
820
+
821
+static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
822
+{
823
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
824
+}
825
+
826
+static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
827
+{
828
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
829
+ return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
830
+}
831
+
832
+static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
833
+{
834
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
835
+}
836
+
837
+static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
838
+{
839
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
840
+}
841
+
842
+static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
843
+{
844
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
845
+}
846
+
847
+static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
848
+{
849
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
850
+ return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
851
+}
852
+
853
+static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
854
+{
855
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
856
+ return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
857
+}
858
+
859
+static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
860
+{
861
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
862
+ return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
863
+}
864
+
865
+static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
866
+{
867
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
868
+}
869
+
870
+static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
871
+{
872
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
873
+}
874
+
875
+static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
876
+{
877
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
878
+}
879
+
880
+static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
881
+{
882
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
883
+}
884
+
885
+static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
886
+{
887
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
888
+}
889
+
890
+static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
891
+{
892
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
893
+}
894
+
895
+static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
896
+{
897
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
898
+}
899
+
900
+static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
901
+{
902
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
903
+}
904
+
905
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
906
+{
907
+ int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
908
+ if (key >= 2) {
909
+ return true; /* FEAT_CSV2_2 */
910
+ }
911
+ if (key == 1) {
912
+ key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
913
+ return key >= 2; /* FEAT_CSV2_1p2 */
914
+ }
915
+ return false;
916
+}
917
+
918
+static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
919
+{
920
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
921
+}
922
+
923
+static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
924
+{
925
+ return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
926
+}
927
+
928
+static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
929
+{
930
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
931
+}
932
+
933
+static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
934
+{
935
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
936
+}
937
+
938
+static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
939
+{
940
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
941
+}
942
+
943
+static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
944
+{
945
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
946
+}
947
+
948
+static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
949
+{
950
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
951
+}
952
+
953
+static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
954
+{
955
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
956
+}
957
+
958
+static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
959
+{
960
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
961
+}
962
+
963
+static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
964
+{
965
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
966
+}
967
+
968
+static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
969
+{
970
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
971
+}
972
+
973
+static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
974
+{
975
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
976
+}
977
+
978
+static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
979
+{
980
+ return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64);
981
+}
982
+
983
+static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id)
984
+{
985
+ return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
986
+}
987
+
988
+static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
989
+{
990
+ return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
991
+}
992
+
993
+static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
994
+{
995
+ return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
996
+}
997
+
998
+static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
999
+{
1000
+ return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
1001
+}
1002
+
1003
+/*
1004
+ * Feature tests for "does this exist in either 32-bit or 64-bit?"
1005
+ */
1006
+static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
1007
+{
1008
+ return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
1009
+}
1010
+
1011
+static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
1012
+{
1013
+ return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
1014
+}
1015
+
1016
+static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id)
1017
+{
1018
+ return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id);
1019
+}
1020
+
1021
+static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id)
1022
+{
1023
+ return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id);
1024
+}
1025
+
1026
+static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id)
1027
+{
1028
+ return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id);
1029
+}
1030
+
1031
+static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
1032
+{
1033
+ return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
1034
+}
1035
+
1036
+static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
1037
+{
1038
+ return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
1039
+}
1040
+
1041
+static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
1042
+{
1043
+ return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
1044
+}
1045
+
1046
+static inline bool isar_feature_any_ras(const ARMISARegisters *id)
1047
+{
1048
+ return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
1049
+}
1050
+
1051
+static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
1052
+{
1053
+ return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
1054
+}
1055
+
1056
+static inline bool isar_feature_any_evt(const ARMISARegisters *id)
1057
+{
1058
+ return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
1059
+}
1060
+
1061
+/*
1062
+ * Forward to the above feature tests given an ARMCPU pointer.
1063
+ */
1064
+#define cpu_isar_feature(name, cpu) \
1065
+ ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
1066
+
1067
+#endif
1068
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
1069
index XXXXXXX..XXXXXXX 100644
1070
--- a/target/arm/cpu.h
1071
+++ b/target/arm/cpu.h
1072
@@ -XXX,XX +XXX,XX @@ static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
1073
}
1074
#endif
1075
1076
-/*
1077
- * Naming convention for isar_feature functions:
1078
- * Functions which test 32-bit ID registers should have _aa32_ in
1079
- * their name. Functions which test 64-bit ID registers should have
1080
- * _aa64_ in their name. These must only be used in code where we
1081
- * know for certain that the CPU has AArch32 or AArch64 respectively
1082
- * or where the correct answer for a CPU which doesn't implement that
1083
- * CPU state is "false" (eg when generating A32 or A64 code, if adding
1084
- * system registers that are specific to that CPU state, for "should
1085
- * we let this system register bit be set" tests where the 32-bit
1086
- * flavour of the register doesn't have the bit, and so on).
1087
- * Functions which simply ask "does this feature exist at all" have
1088
- * _any_ in their name, and always return the logical OR of the _aa64_
1089
- * and the _aa32_ function.
1090
- */
1091
-
1092
-/*
1093
- * 32-bit feature tests via id registers.
1094
- */
1095
-static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
1096
-{
1097
- return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
1098
-}
1099
-
1100
-static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
1101
-{
1102
- return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
1103
-}
1104
-
1105
-static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
1106
-{
1107
- /* (M-profile) low-overhead loops and branch future */
1108
- return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
1109
-}
1110
-
1111
-static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
1112
-{
1113
- return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
1114
-}
1115
-
1116
-static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
1117
-{
1118
- return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
1119
-}
1120
-
1121
-static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
1122
-{
1123
- return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
1124
-}
1125
-
1126
-static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
1127
-{
1128
- return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
1129
-}
1130
-
1131
-static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
1132
-{
1133
- return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
1134
-}
1135
-
1136
-static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
1137
-{
1138
- return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
1139
-}
1140
-
1141
-static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
1142
-{
1143
- return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
1144
-}
1145
-
1146
-static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
1147
-{
1148
- return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
1149
-}
1150
-
1151
-static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
1152
-{
1153
- return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
1154
-}
1155
-
1156
-static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
1157
-{
1158
- return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
1159
-}
1160
-
1161
-static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
1162
-{
1163
- return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
1164
-}
1165
-
1166
-static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
1167
-{
1168
- return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
1169
-}
1170
-
1171
-static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
1172
-{
1173
- return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
1174
-}
1175
-
1176
-static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
1177
-{
1178
- return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
1179
-}
1180
-
1181
-static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
1182
-{
1183
- return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
1184
-}
1185
-
1186
-static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
1187
-{
1188
- return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
1189
-}
1190
-
1191
-static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
1192
-{
1193
- return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
1194
-}
1195
-
1196
-static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
1197
-{
1198
- /*
1199
- * Return true if M-profile state handling insns
1200
- * (VSCCLRM, CLRM, FPCTX access insns) are implemented
1201
- */
1202
- return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
1203
-}
1204
-
1205
-static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
1206
-{
1207
- /* Sadly this is encoded differently for A-profile and M-profile */
1208
- if (isar_feature_aa32_mprofile(id)) {
1209
- return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
1210
- } else {
1211
- return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
1212
- }
1213
-}
1214
-
1215
-static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
1216
-{
1217
- /*
1218
- * Return true if MVE is supported (either integer or floating point).
1219
- * We must check for M-profile as the MVFR1 field means something
1220
- * else for A-profile.
1221
- */
1222
- return isar_feature_aa32_mprofile(id) &&
1223
- FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
1224
-}
1225
-
1226
-static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
1227
-{
1228
- /*
1229
- * Return true if MVE is supported (either integer or floating point).
1230
- * We must check for M-profile as the MVFR1 field means something
1231
- * else for A-profile.
1232
- */
1233
- return isar_feature_aa32_mprofile(id) &&
1234
- FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
1235
-}
1236
-
1237
-static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
1238
-{
1239
- /*
1240
- * Return true if either VFP or SIMD is implemented.
1241
- * In this case, a minimum of VFP w/ D0-D15.
1242
- */
1243
- return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
1244
-}
1245
-
1246
-static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
1247
-{
1248
- /* Return true if D16-D31 are implemented */
1249
- return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
1250
-}
1251
-
1252
-static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
1253
-{
1254
- return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
1255
-}
1256
-
1257
-static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
1258
-{
1259
- /* Return true if CPU supports single precision floating point, VFPv2 */
1260
- return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
1261
-}
1262
-
1263
-static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
1264
-{
1265
- /* Return true if CPU supports single precision floating point, VFPv3 */
1266
- return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
1267
-}
1268
-
1269
-static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
1270
-{
1271
- /* Return true if CPU supports double precision floating point, VFPv2 */
1272
- return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
1273
-}
1274
-
1275
-static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
1276
-{
1277
- /* Return true if CPU supports double precision floating point, VFPv3 */
1278
- return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
1279
-}
1280
-
1281
-static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
1282
-{
1283
- return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
1284
-}
1285
-
1286
-/*
1287
- * We always set the FP and SIMD FP16 fields to indicate identical
1288
- * levels of support (assuming SIMD is implemented at all), so
1289
- * we only need one set of accessors.
1290
- */
1291
-static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
1292
-{
1293
- return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
1294
-}
1295
-
1296
-static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
1297
-{
1298
- return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
1299
-}
1300
-
1301
-/*
1302
- * Note that this ID register field covers both VFP and Neon FMAC,
1303
- * so should usually be tested in combination with some other
1304
- * check that confirms the presence of whichever of VFP or Neon is
1305
- * relevant, to avoid accidentally enabling a Neon feature on
1306
- * a VFP-no-Neon core or vice-versa.
1307
- */
1308
-static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
1309
-{
1310
- return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
1311
-}
1312
-
1313
-static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
1314
-{
1315
- return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
1316
-}
1317
-
1318
-static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
1319
-{
1320
- return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
1321
-}
1322
-
1323
-static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
1324
-{
1325
- return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
1326
-}
1327
-
1328
-static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
1329
-{
1330
- return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
1331
-}
1332
-
1333
-static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
1334
-{
1335
- return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
1336
-}
1337
-
1338
-static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
1339
-{
1340
- return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
1341
-}
1342
-
1343
-static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
1344
-{
1345
- return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
1346
-}
1347
-
1348
-static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
1349
-{
1350
- /* 0xf means "non-standard IMPDEF PMU" */
1351
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
1352
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
1353
-}
1354
-
1355
-static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id)
1356
-{
1357
- /* 0xf means "non-standard IMPDEF PMU" */
1358
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
1359
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
1360
-}
1361
-
1362
-static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
1363
-{
1364
- /* 0xf means "non-standard IMPDEF PMU" */
1365
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 &&
1366
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
1367
-}
1368
-
1369
-static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
1370
-{
1371
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
1372
-}
1373
-
1374
-static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
1375
-{
1376
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
1377
-}
1378
-
1379
-static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
1380
-{
1381
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
1382
-}
1383
-
1384
-static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
1385
-{
1386
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
1387
-}
1388
-
1389
-static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
1390
-{
1391
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
1392
-}
1393
-
1394
-static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
1395
-{
1396
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
1397
-}
1398
-
1399
-static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
1400
-{
1401
- return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
1402
-}
1403
-
1404
-static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
1405
-{
1406
- return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
1407
-}
1408
-
1409
-static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
1410
-{
1411
- return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5;
1412
-}
1413
-
1414
-static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
1415
-{
1416
- return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
1417
-}
1418
-
1419
-static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
1420
-{
1421
- return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0;
1422
-}
1423
-
1424
-/*
1425
- * 64-bit feature tests via id registers.
1426
- */
1427
-static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
1428
-{
1429
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
1430
-}
1431
-
1432
-static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
1433
-{
1434
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
1435
-}
1436
-
1437
-static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
1438
-{
1439
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
1440
-}
1441
-
1442
-static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
1443
-{
1444
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
1445
-}
1446
-
1447
-static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
1448
-{
1449
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
1450
-}
1451
-
1452
-static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
1453
-{
1454
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
1455
-}
1456
-
1457
-static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
1458
-{
1459
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
1460
-}
1461
-
1462
-static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
1463
-{
1464
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
1465
-}
1466
-
1467
-static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
1468
-{
1469
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
1470
-}
1471
-
1472
-static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
1473
-{
1474
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
1475
-}
1476
-
1477
-static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
1478
-{
1479
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
1480
-}
1481
-
1482
-static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
1483
-{
1484
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
1485
-}
1486
-
1487
-static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
1488
-{
1489
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
1490
-}
1491
-
1492
-static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
1493
-{
1494
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
1495
-}
1496
-
1497
-static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
1498
-{
1499
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
1500
-}
1501
-
1502
-static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
1503
-{
1504
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
1505
-}
1506
-
1507
-static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
1508
-{
1509
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
1510
-}
1511
-
1512
-static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
1513
-{
1514
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
1515
-}
1516
-
1517
-/*
1518
- * These are the values from APA/API/APA3.
1519
- * In general these must be compared '>=', per the normal Arm ARM
1520
- * treatment of fields in ID registers.
1521
- */
1522
-typedef enum {
1523
- PauthFeat_None = 0,
1524
- PauthFeat_1 = 1,
1525
- PauthFeat_EPAC = 2,
1526
- PauthFeat_2 = 3,
1527
- PauthFeat_FPAC = 4,
1528
- PauthFeat_FPACCOMBINED = 5,
1529
-} ARMPauthFeature;
1530
-
1531
-static inline ARMPauthFeature
1532
-isar_feature_pauth_feature(const ARMISARegisters *id)
1533
-{
1534
- /*
1535
- * Architecturally, only one of {APA,API,APA3} may be active (non-zero)
1536
- * and the other two must be zero. Thus we may avoid conditionals.
1537
- */
1538
- return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) |
1539
- FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) |
1540
- FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3));
1541
-}
1542
-
1543
-static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
1544
-{
1545
- /*
1546
- * Return true if any form of pauth is enabled, as this
1547
- * predicate controls migration of the 128-bit keys.
1548
- */
1549
- return isar_feature_pauth_feature(id) != PauthFeat_None;
1550
-}
1551
-
1552
-static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id)
1553
-{
1554
- /*
1555
- * Return true if pauth is enabled with the architected QARMA5 algorithm.
1556
- * QEMU will always enable or disable both APA and GPA.
1557
- */
1558
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
1559
-}
1560
-
1561
-static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
1562
-{
1563
- /*
1564
- * Return true if pauth is enabled with the architected QARMA3 algorithm.
1565
- * QEMU will always enable or disable both APA3 and GPA3.
1566
- */
1567
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
1568
-}
1569
-
1570
-static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
1571
-{
1572
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
1573
-}
1574
-
1575
-static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
1576
-{
1577
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
1578
-}
1579
-
1580
-static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
1581
-{
1582
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
1583
-}
1584
-
1585
-static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
1586
-{
1587
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
1588
-}
1589
-
1590
-static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
1591
-{
1592
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
1593
-}
1594
-
1595
-static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
1596
-{
1597
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
1598
-}
1599
-
1600
-static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
1601
-{
1602
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
1603
-}
1604
-
1605
-static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
1606
-{
1607
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
1608
-}
1609
-
1610
-static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
1611
-{
1612
- /* We always set the AdvSIMD and FP fields identically. */
1613
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
1614
-}
1615
-
1616
-static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
1617
-{
1618
- /* We always set the AdvSIMD and FP fields identically wrt FP16. */
1619
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
1620
-}
1621
-
1622
-static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
1623
-{
1624
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
1625
-}
1626
-
1627
-static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
1628
-{
1629
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
1630
-}
1631
-
1632
-static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
1633
-{
1634
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
1635
-}
1636
-
1637
-static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
1638
-{
1639
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
1640
-}
1641
-
1642
-static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id)
1643
-{
1644
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2;
1645
-}
1646
-
1647
-static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
1648
-{
1649
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
1650
-}
1651
-
1652
-static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
1653
-{
1654
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
1655
-}
1656
-
1657
-static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
1658
-{
1659
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
1660
-}
1661
-
1662
-static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
1663
-{
1664
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
1665
-}
1666
-
1667
-static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
1668
-{
1669
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
1670
-}
1671
-
1672
-static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
1673
-{
1674
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
1675
-}
1676
-
1677
-static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
1678
-{
1679
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
1680
-}
1681
-
1682
-static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
1683
-{
1684
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
1685
-}
1686
-
1687
-static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
1688
-{
1689
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
1690
-}
1691
-
1692
-static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
1693
-{
1694
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
1695
-}
1696
-
1697
-static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
1698
-{
1699
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
1700
-}
1701
-
1702
-static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
1703
-{
1704
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
1705
-}
1706
-
1707
-static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id)
1708
-{
1709
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0;
1710
-}
1711
-
1712
-static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
1713
-{
1714
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
1715
-}
1716
-
1717
-static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
1718
-{
1719
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
1720
-}
1721
-
1722
-static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
1723
-{
1724
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
1725
-}
1726
-
1727
-static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
1728
-{
1729
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
1730
-}
1731
-
1732
-static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
1733
-{
1734
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
1735
-}
1736
-
1737
-static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
1738
-{
1739
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
1740
-}
1741
-
1742
-static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
1743
-{
1744
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
1745
-}
1746
-
1747
-static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
1748
-{
1749
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
1750
-}
1751
-
1752
-static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
1753
-{
1754
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
1755
- FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
1756
-}
1757
-
1758
-static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
1759
-{
1760
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
1761
- FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
1762
-}
1763
-
1764
-static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
1765
-{
1766
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
1767
- FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
1768
-}
1769
-
1770
-static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
1771
-{
1772
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
1773
-}
1774
-
1775
-static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
1776
-{
1777
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
1778
-}
1779
-
1780
-static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
1781
-{
1782
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
1783
-}
1784
-
1785
-static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
1786
-{
1787
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
1788
-}
1789
-
1790
-static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
1791
-{
1792
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
1793
-}
1794
-
1795
-static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
1796
-{
1797
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
1798
- return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
1799
-}
1800
-
1801
-static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
1802
-{
1803
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
1804
-}
1805
-
1806
-static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
1807
-{
1808
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
1809
- return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
1810
-}
1811
-
1812
-static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
1813
-{
1814
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
1815
-}
1816
-
1817
-static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
1818
-{
1819
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
1820
-}
1821
-
1822
-static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
1823
-{
1824
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
1825
-}
1826
-
1827
-static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
1828
-{
1829
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
1830
- return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
1831
-}
1832
-
1833
-static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
1834
-{
1835
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
1836
- return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
1837
-}
1838
-
1839
-static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
1840
-{
1841
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
1842
- return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
1843
-}
1844
-
1845
-static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
1846
-{
1847
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
1848
-}
1849
-
1850
-static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
1851
-{
1852
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
1853
-}
1854
-
1855
-static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
1856
-{
1857
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
1858
-}
1859
-
1860
-static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
1861
-{
1862
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
1863
-}
1864
-
1865
-static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
1866
-{
1867
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
1868
-}
1869
-
1870
-static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
1871
-{
1872
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
1873
-}
1874
-
1875
-static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
1876
-{
1877
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
1878
-}
1879
-
1880
-static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
1881
-{
1882
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
1883
-}
1884
-
1885
-static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
1886
-{
1887
- int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
1888
- if (key >= 2) {
1889
- return true; /* FEAT_CSV2_2 */
1890
- }
1891
- if (key == 1) {
1892
- key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
1893
- return key >= 2; /* FEAT_CSV2_1p2 */
1894
- }
1895
- return false;
1896
-}
1897
-
1898
-static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
1899
-{
1900
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
1901
-}
1902
-
1903
-static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
1904
-{
1905
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
1906
-}
1907
-
1908
-static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
1909
-{
1910
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
1911
-}
1912
-
1913
-static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
1914
-{
1915
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
1916
-}
1917
-
1918
-static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
1919
-{
1920
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
1921
-}
1922
-
1923
-static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
1924
-{
1925
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
1926
-}
1927
-
1928
-static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
1929
-{
1930
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
1931
-}
1932
-
1933
-static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
1934
-{
1935
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
1936
-}
1937
-
1938
-static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
1939
-{
1940
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
1941
-}
1942
-
1943
-static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
1944
-{
1945
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
1946
-}
1947
-
1948
-static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
1949
-{
1950
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
1951
-}
1952
-
1953
-static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
1954
-{
1955
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
1956
-}
1957
-
1958
-static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
1959
-{
1960
- return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64);
1961
-}
1962
-
1963
-static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id)
1964
-{
1965
- return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
1966
-}
1967
-
1968
-static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
1969
-{
1970
- return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
1971
-}
1972
-
1973
-static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
1974
-{
1975
- return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
1976
-}
1977
-
1978
-static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
1979
-{
1980
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
1981
-}
1982
-
1983
-/*
1984
- * Feature tests for "does this exist in either 32-bit or 64-bit?"
1985
- */
1986
-static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
1987
-{
1988
- return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
1989
-}
1990
-
1991
-static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
1992
-{
1993
- return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
1994
-}
1995
-
1996
-static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id)
1997
-{
1998
- return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id);
1999
-}
2000
-
2001
-static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id)
2002
-{
2003
- return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id);
2004
-}
2005
-
2006
-static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id)
2007
-{
2008
- return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id);
2009
-}
2010
-
2011
-static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
2012
-{
2013
- return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
2014
-}
2015
-
2016
-static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
2017
-{
2018
- return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
2019
-}
2020
-
2021
-static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
2022
-{
2023
- return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
2024
-}
2025
-
2026
-static inline bool isar_feature_any_ras(const ARMISARegisters *id)
2027
-{
2028
- return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
2029
-}
2030
-
2031
-static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
2032
-{
2033
- return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
2034
-}
2035
-
2036
-static inline bool isar_feature_any_evt(const ARMISARegisters *id)
2037
-{
2038
- return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
2039
-}
2040
-
2041
-/*
2042
- * Forward to the above feature tests given an ARMCPU pointer.
2043
- */
2044
-#define cpu_isar_feature(name, cpu) \
2045
- ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
2046
-
2047
#endif
2048
diff --git a/target/arm/internals.h b/target/arm/internals.h
2049
index XXXXXXX..XXXXXXX 100644
2050
--- a/target/arm/internals.h
2051
+++ b/target/arm/internals.h
2052
@@ -XXX,XX +XXX,XX @@
2053
#include "hw/registerfields.h"
2054
#include "tcg/tcg-gvec-desc.h"
2055
#include "syndrome.h"
2056
+#include "cpu-features.h"
2057
2058
/* register banks for CPU modes */
2059
#define BANK_USRSYS 0
2060
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
2061
index XXXXXXX..XXXXXXX 100644
2062
--- a/target/arm/tcg/translate.h
2063
+++ b/target/arm/tcg/translate.h
2064
@@ -XXX,XX +XXX,XX @@
2065
#include "exec/translator.h"
2066
#include "exec/helper-gen.h"
2067
#include "internals.h"
2068
-
2069
+#include "cpu-features.h"
2070
2071
/* internal defines */
2072
2073
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
2074
index XXXXXXX..XXXXXXX 100644
2075
--- a/hw/arm/armv7m.c
2076
+++ b/hw/arm/armv7m.c
2077
@@ -XXX,XX +XXX,XX @@
2078
#include "qemu/module.h"
2079
#include "qemu/log.h"
2080
#include "target/arm/idau.h"
2081
+#include "target/arm/cpu-features.h"
2082
#include "migration/vmstate.h"
2083
2084
/* Bitbanded IO. Each word corresponds to a single bit. */
2085
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
2086
index XXXXXXX..XXXXXXX 100644
2087
--- a/hw/intc/armv7m_nvic.c
2088
+++ b/hw/intc/armv7m_nvic.c
2089
@@ -XXX,XX +XXX,XX @@
2090
#include "sysemu/tcg.h"
2091
#include "sysemu/runstate.h"
2092
#include "target/arm/cpu.h"
2093
+#include "target/arm/cpu-features.h"
2094
#include "exec/exec-all.h"
2095
#include "exec/memop.h"
2096
#include "qemu/log.h"
2097
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
2098
index XXXXXXX..XXXXXXX 100644
2099
--- a/linux-user/aarch64/cpu_loop.c
2100
+++ b/linux-user/aarch64/cpu_loop.c
2101
@@ -XXX,XX +XXX,XX @@
2102
#include "qemu/guest-random.h"
2103
#include "semihosting/common-semi.h"
2104
#include "target/arm/syndrome.h"
2105
+#include "target/arm/cpu-features.h"
2106
2107
#define get_user_code_u32(x, gaddr, env) \
2108
({ abi_long __r = get_user_u32((x), (gaddr)); \
2109
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
2110
index XXXXXXX..XXXXXXX 100644
2111
--- a/linux-user/aarch64/signal.c
2112
+++ b/linux-user/aarch64/signal.c
2113
@@ -XXX,XX +XXX,XX @@
2114
#include "user-internals.h"
2115
#include "signal-common.h"
2116
#include "linux-user/trace.h"
2117
+#include "target/arm/cpu-features.h"
2118
2119
struct target_sigcontext {
2120
uint64_t fault_address;
2121
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
2122
index XXXXXXX..XXXXXXX 100644
2123
--- a/linux-user/arm/signal.c
2124
+++ b/linux-user/arm/signal.c
2125
@@ -XXX,XX +XXX,XX @@
2126
#include "user-internals.h"
2127
#include "signal-common.h"
2128
#include "linux-user/trace.h"
2129
+#include "target/arm/cpu-features.h"
2130
2131
struct target_sigcontext {
2132
abi_ulong trap_no;
2133
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
2134
index XXXXXXX..XXXXXXX 100644
2135
--- a/linux-user/elfload.c
2136
+++ b/linux-user/elfload.c
2137
@@ -XXX,XX +XXX,XX @@
2138
#include "target_signal.h"
2139
#include "accel/tcg/debuginfo.h"
2140
2141
+#ifdef TARGET_ARM
2142
+#include "target/arm/cpu-features.h"
2143
+#endif
2144
+
2145
#ifdef _ARCH_PPC64
2146
#undef ARCH_DLINFO
2147
#undef ELF_PLATFORM
2148
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
2149
index XXXXXXX..XXXXXXX 100644
2150
--- a/linux-user/mmap.c
2151
+++ b/linux-user/mmap.c
2152
@@ -XXX,XX +XXX,XX @@
2153
#include "target_mman.h"
2154
#include "qemu/interval-tree.h"
2155
2156
+#ifdef TARGET_ARM
2157
+#include "target/arm/cpu-features.h"
2158
+#endif
2159
+
2160
static pthread_mutex_t mmap_mutex = PTHREAD_MUTEX_INITIALIZER;
2161
static __thread int mmap_lock_count;
2162
2163
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
2164
index XXXXXXX..XXXXXXX 100644
2165
--- a/target/arm/arch_dump.c
2166
+++ b/target/arm/arch_dump.c
2167
@@ -XXX,XX +XXX,XX @@
2168
#include "cpu.h"
2169
#include "elf.h"
2170
#include "sysemu/dump.h"
2171
+#include "cpu-features.h"
2172
2173
/* struct user_pt_regs from arch/arm64/include/uapi/asm/ptrace.h */
2174
struct aarch64_user_regs {
2175
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
2176
index XXXXXXX..XXXXXXX 100644
2177
--- a/target/arm/cpu.c
2178
+++ b/target/arm/cpu.c
2179
@@ -XXX,XX +XXX,XX @@
2180
#include "hw/core/tcg-cpu-ops.h"
2181
#endif /* CONFIG_TCG */
2182
#include "internals.h"
2183
+#include "cpu-features.h"
2184
#include "exec/exec-all.h"
2185
#include "hw/qdev-properties.h"
2186
#if !defined(CONFIG_USER_ONLY)
2187
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
2188
index XXXXXXX..XXXXXXX 100644
2189
--- a/target/arm/cpu64.c
2190
+++ b/target/arm/cpu64.c
2191
@@ -XXX,XX +XXX,XX @@
2192
#include "qapi/visitor.h"
2193
#include "hw/qdev-properties.h"
2194
#include "internals.h"
2195
+#include "cpu-features.h"
2196
#include "cpregs.h"
2197
2198
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
2199
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
2200
index XXXXXXX..XXXXXXX 100644
2201
--- a/target/arm/debug_helper.c
2202
+++ b/target/arm/debug_helper.c
2203
@@ -XXX,XX +XXX,XX @@
2204
#include "qemu/log.h"
2205
#include "cpu.h"
2206
#include "internals.h"
2207
+#include "cpu-features.h"
2208
#include "cpregs.h"
2209
#include "exec/exec-all.h"
2210
#include "exec/helper-proto.h"
2211
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
2212
index XXXXXXX..XXXXXXX 100644
2213
--- a/target/arm/gdbstub.c
2214
+++ b/target/arm/gdbstub.c
2215
@@ -XXX,XX +XXX,XX @@
2216
#include "gdbstub/helpers.h"
2217
#include "sysemu/tcg.h"
2218
#include "internals.h"
2219
+#include "cpu-features.h"
2220
#include "cpregs.h"
2221
2222
typedef struct RegisterSysregXmlParam {
2223
diff --git a/target/arm/helper.c b/target/arm/helper.c
2224
index XXXXXXX..XXXXXXX 100644
2225
--- a/target/arm/helper.c
2226
+++ b/target/arm/helper.c
2227
@@ -XXX,XX +XXX,XX @@
2228
#include "trace.h"
2229
#include "cpu.h"
2230
#include "internals.h"
2231
+#include "cpu-features.h"
2232
#include "exec/helper-proto.h"
2233
#include "qemu/main-loop.h"
2234
#include "qemu/timer.h"
2235
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
2236
index XXXXXXX..XXXXXXX 100644
2237
--- a/target/arm/kvm64.c
2238
+++ b/target/arm/kvm64.c
2239
@@ -XXX,XX +XXX,XX @@
2240
#include "sysemu/kvm_int.h"
2241
#include "kvm_arm.h"
2242
#include "internals.h"
2243
+#include "cpu-features.h"
2244
#include "hw/acpi/acpi.h"
2245
#include "hw/acpi/ghes.h"
2246
2247
diff --git a/target/arm/machine.c b/target/arm/machine.c
2248
index XXXXXXX..XXXXXXX 100644
2249
--- a/target/arm/machine.c
2250
+++ b/target/arm/machine.c
2251
@@ -XXX,XX +XXX,XX @@
2252
#include "sysemu/tcg.h"
2253
#include "kvm_arm.h"
2254
#include "internals.h"
2255
+#include "cpu-features.h"
2256
#include "migration/cpu.h"
2257
2258
static bool vfp_needed(void *opaque)
2259
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
2260
index XXXXXXX..XXXXXXX 100644
2261
--- a/target/arm/ptw.c
2262
+++ b/target/arm/ptw.c
2263
@@ -XXX,XX +XXX,XX @@
2264
#include "exec/exec-all.h"
2265
#include "cpu.h"
2266
#include "internals.h"
2267
+#include "cpu-features.h"
2268
#include "idau.h"
2269
#ifdef CONFIG_TCG
2270
# include "tcg/oversized-guest.h"
2271
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
2272
index XXXXXXX..XXXXXXX 100644
2273
--- a/target/arm/tcg/cpu64.c
2274
+++ b/target/arm/tcg/cpu64.c
2275
@@ -XXX,XX +XXX,XX @@
2276
#include "hw/qdev-properties.h"
2277
#include "qemu/units.h"
2278
#include "internals.h"
2279
+#include "cpu-features.h"
2280
#include "cpregs.h"
2281
2282
static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
2283
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
2284
index XXXXXXX..XXXXXXX 100644
2285
--- a/target/arm/tcg/hflags.c
2286
+++ b/target/arm/tcg/hflags.c
2287
@@ -XXX,XX +XXX,XX @@
2288
#include "qemu/osdep.h"
2289
#include "cpu.h"
2290
#include "internals.h"
2291
+#include "cpu-features.h"
2292
#include "exec/helper-proto.h"
2293
#include "cpregs.h"
2294
2295
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
2296
index XXXXXXX..XXXXXXX 100644
2297
--- a/target/arm/tcg/m_helper.c
2298
+++ b/target/arm/tcg/m_helper.c
2299
@@ -XXX,XX +XXX,XX @@
2300
#include "qemu/osdep.h"
2301
#include "cpu.h"
2302
#include "internals.h"
2303
+#include "cpu-features.h"
2304
#include "gdbstub/helpers.h"
2305
#include "exec/helper-proto.h"
2306
#include "qemu/main-loop.h"
2307
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
2308
index XXXXXXX..XXXXXXX 100644
2309
--- a/target/arm/tcg/op_helper.c
2310
+++ b/target/arm/tcg/op_helper.c
2311
@@ -XXX,XX +XXX,XX @@
2312
#include "cpu.h"
2313
#include "exec/helper-proto.h"
2314
#include "internals.h"
2315
+#include "cpu-features.h"
2316
#include "exec/exec-all.h"
2317
#include "exec/cpu_ldst.h"
2318
#include "cpregs.h"
2319
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
2320
index XXXXXXX..XXXXXXX 100644
2321
--- a/target/arm/tcg/pauth_helper.c
2322
+++ b/target/arm/tcg/pauth_helper.c
2323
@@ -XXX,XX +XXX,XX @@
2324
#include "qemu/osdep.h"
2325
#include "cpu.h"
2326
#include "internals.h"
2327
+#include "cpu-features.h"
2328
#include "exec/exec-all.h"
2329
#include "exec/cpu_ldst.h"
2330
#include "exec/helper-proto.h"
2331
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
2332
index XXXXXXX..XXXXXXX 100644
2333
--- a/target/arm/tcg/tlb_helper.c
2334
+++ b/target/arm/tcg/tlb_helper.c
2335
@@ -XXX,XX +XXX,XX @@
2336
#include "qemu/osdep.h"
2337
#include "cpu.h"
2338
#include "internals.h"
2339
+#include "cpu-features.h"
2340
#include "exec/exec-all.h"
2341
#include "exec/helper-proto.h"
2342
2343
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
2344
index XXXXXXX..XXXXXXX 100644
2345
--- a/target/arm/vfp_helper.c
2346
+++ b/target/arm/vfp_helper.c
2347
@@ -XXX,XX +XXX,XX @@
2348
#include "cpu.h"
2349
#include "exec/helper-proto.h"
2350
#include "internals.h"
2351
+#include "cpu-features.h"
2352
#ifdef CONFIG_TCG
2353
#include "qemu/log.h"
2354
#include "fpu/softfloat.h"
2355
--
2356
2.34.1
2357
2358
diff view generated by jsdifflib
New patch
[PULL 04/41] target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together
1
Our list of isar_feature functions is not in any particular order,
2
but tests on fields of the same ID register tend to be grouped
3
together. A few functions that are tests of fields in ID_AA64MMFR1
4
and ID_AA64MMFR2 are not in the same place as the rest; move them
5
into their groups.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20231024163510.2972081-3-peter.maydell@linaro.org
11
---
12
target/arm/cpu-features.h | 60 +++++++++++++++++++--------------------
13
1 file changed, 30 insertions(+), 30 deletions(-)
14
15
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu-features.h
18
+++ b/target/arm/cpu-features.h
19
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
20
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
21
}
22
23
+static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
24
+{
25
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
26
+}
27
+
28
+static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
29
+{
30
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
31
+}
32
+
33
+static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
34
+{
35
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
36
+}
37
+
38
static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
39
{
40
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
41
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
42
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
43
}
44
45
+static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
46
+{
47
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
48
+}
49
+
50
+static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
51
+{
52
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
53
+}
54
+
55
+static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
56
+{
57
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
58
+}
59
+
60
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
61
{
62
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
63
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
64
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
65
}
66
67
-static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
68
-{
69
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
70
-}
71
-
72
-static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
73
-{
74
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
75
-}
76
-
77
-static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
78
-{
79
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
80
-}
81
-
82
-static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
83
-{
84
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
85
-}
86
-
87
-static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
88
-{
89
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
90
-}
91
-
92
-static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
93
-{
94
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
95
-}
96
-
97
static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
98
{
99
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
100
--
101
2.34.1
102
103
diff view generated by jsdifflib
New patch
[PULL 05/41] target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2
1
Move the ID_AA64MMFR0 feature test functions up so they are
2
before the ones for ID_AA64MMFR1 and ID_AA64MMFR2.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20231024163510.2972081-4-peter.maydell@linaro.org
8
---
9
target/arm/cpu-features.h | 120 +++++++++++++++++++-------------------
10
1 file changed, 60 insertions(+), 60 deletions(-)
11
12
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu-features.h
15
+++ b/target/arm/cpu-features.h
16
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
17
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
18
}
19
20
+static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
21
+{
22
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
23
+}
24
+
25
+static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
26
+{
27
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
28
+ return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
29
+}
30
+
31
+static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
32
+{
33
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
34
+}
35
+
36
+static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
37
+{
38
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
39
+ return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
40
+}
41
+
42
+static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
43
+{
44
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
45
+}
46
+
47
+static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
48
+{
49
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
50
+}
51
+
52
+static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
53
+{
54
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
55
+}
56
+
57
+static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
58
+{
59
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
60
+ return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
61
+}
62
+
63
+static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
64
+{
65
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
66
+ return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
67
+}
68
+
69
+static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
70
+{
71
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
72
+ return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
73
+}
74
+
75
+static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
76
+{
77
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
78
+}
79
+
80
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
81
{
82
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
83
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
84
return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
85
}
86
87
-static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
88
-{
89
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
90
-}
91
-
92
-static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
93
-{
94
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
95
- return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
96
-}
97
-
98
-static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
99
-{
100
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
101
-}
102
-
103
-static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
104
-{
105
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
106
- return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
107
-}
108
-
109
-static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
110
-{
111
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
112
-}
113
-
114
-static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
115
-{
116
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
117
-}
118
-
119
-static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
120
-{
121
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
122
-}
123
-
124
-static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
125
-{
126
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
127
- return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
128
-}
129
-
130
-static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
131
-{
132
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
133
- return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
134
-}
135
-
136
-static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
137
-{
138
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
139
- return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
140
-}
141
-
142
-static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
143
-{
144
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
145
-}
146
-
147
static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
148
{
149
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
150
--
151
2.34.1
152
153
diff view generated by jsdifflib
New patch
[PULL 06/41] target/arm: Move ID_AA64ISAR* test functions together
1
Move the feature test functions that test ID_AA64ISAR* fields
2
together.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20231024163510.2972081-5-peter.maydell@linaro.org
8
---
9
target/arm/cpu-features.h | 70 +++++++++++++++++++--------------------
10
1 file changed, 35 insertions(+), 35 deletions(-)
11
12
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu-features.h
15
+++ b/target/arm/cpu-features.h
16
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
17
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
18
}
19
20
+static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
21
+{
22
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
23
+}
24
+
25
+static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
26
+{
27
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
28
+}
29
+
30
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
31
{
32
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
33
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
34
return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
35
}
36
37
-static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
38
-{
39
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
40
-}
41
-
42
-static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
43
-{
44
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
45
-}
46
-
47
static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
48
{
49
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
50
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
51
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
52
}
53
54
+static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
55
+{
56
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
57
+}
58
+
59
+static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
60
+{
61
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
62
+}
63
+
64
+static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
65
+{
66
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
67
+}
68
+
69
+static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
70
+{
71
+ return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
72
+}
73
+
74
+static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
75
+{
76
+ return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
77
+}
78
+
79
static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
80
{
81
/* We always set the AdvSIMD and FP fields identically. */
82
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
83
FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
84
}
85
86
-static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
87
-{
88
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
89
-}
90
-
91
-static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
92
-{
93
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
94
-}
95
-
96
-static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
97
-{
98
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
99
-}
100
-
101
-static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
102
-{
103
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
104
-}
105
-
106
static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
107
{
108
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
109
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
110
return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
111
}
112
113
-static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
114
-{
115
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
116
-}
117
-
118
/*
119
* Feature tests for "does this exist in either 32-bit or 64-bit?"
120
*/
121
--
122
2.34.1
123
124
diff view generated by jsdifflib
New patch
[PULL 07/41] target/arm: Move ID_AA64PFR* tests together
1
Move all the ID_AA64PFR* feature test functions together.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20231024163510.2972081-6-peter.maydell@linaro.org
7
---
8
target/arm/cpu-features.h | 86 +++++++++++++++++++--------------------
9
1 file changed, 43 insertions(+), 43 deletions(-)
10
11
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/cpu-features.h
14
+++ b/target/arm/cpu-features.h
15
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
16
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
17
}
18
19
+static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
20
+{
21
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
22
+}
23
+
24
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
25
+{
26
+ int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
27
+ if (key >= 2) {
28
+ return true; /* FEAT_CSV2_2 */
29
+ }
30
+ if (key == 1) {
31
+ key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
32
+ return key >= 2; /* FEAT_CSV2_1p2 */
33
+ }
34
+ return false;
35
+}
36
+
37
+static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
38
+{
39
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
40
+}
41
+
42
+static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
43
+{
44
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
45
+}
46
+
47
+static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
48
+{
49
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
50
+}
51
+
52
+static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
53
+{
54
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
55
+}
56
+
57
+static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
58
+{
59
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
60
+}
61
+
62
static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
63
{
64
return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
65
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
66
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
67
}
68
69
-static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
70
-{
71
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
72
-}
73
-
74
-static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
75
-{
76
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
77
-}
78
-
79
-static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
80
-{
81
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
82
-}
83
-
84
-static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
85
-{
86
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
87
-}
88
-
89
static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
90
{
91
return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
92
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
93
FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
94
}
95
96
-static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
97
-{
98
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
99
-}
100
-
101
-static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
102
-{
103
- int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
104
- if (key >= 2) {
105
- return true; /* FEAT_CSV2_2 */
106
- }
107
- if (key == 1) {
108
- key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
109
- return key >= 2; /* FEAT_CSV2_1p2 */
110
- }
111
- return false;
112
-}
113
-
114
-static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
115
-{
116
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
117
-}
118
-
119
static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
120
{
121
return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
122
--
123
2.34.1
124
125
diff view generated by jsdifflib
New patch
[PULL 08/41] target/arm: Move ID_AA64DFR* feature tests together
1
Move all the ID_AA64DFR* feature test functions together.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20231024163510.2972081-7-peter.maydell@linaro.org
7
---
8
target/arm/cpu-features.h | 10 +++++-----
9
1 file changed, 5 insertions(+), 5 deletions(-)
10
11
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/cpu-features.h
14
+++ b/target/arm/cpu-features.h
15
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
16
return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
17
}
18
19
+static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
20
+{
21
+ return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
22
+}
23
+
24
static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
25
{
26
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
27
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
28
return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
29
}
30
31
-static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
32
-{
33
- return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
34
-}
35
-
36
/*
37
* Feature tests for "does this exist in either 32-bit or 64-bit?"
38
*/
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 09/41] target/arm: Fix syndrome for FGT traps on ERET
1
In commit 442c9d682c94fc2 when we converted the ERET, ERETAA, ERETAB
2
instructions to decodetree, the conversion accidentally lost the
3
correct setting of the syndrome register when taking a trap because
4
of the FEAT_FGT HFGITR_EL1.ERET bit. Instead of reporting a correct
5
full syndrome value with the EC and IL bits, we only reported the low
6
two bits of the syndrome, because the call to syn_erettrap() got
7
dropped.
1
8
9
Fix the syndrome values for these traps by reinstating the
10
syn_erettrap() calls.
11
12
Fixes: 442c9d682c94fc2 ("target/arm: Convert ERET, ERETAA, ERETAB to decodetree")
13
Cc: qemu-stable@nongnu.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20231024172438.2990945-1-peter.maydell@linaro.org
17
---
18
target/arm/tcg/translate-a64.c | 4 ++--
19
1 file changed, 2 insertions(+), 2 deletions(-)
20
21
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/tcg/translate-a64.c
24
+++ b/target/arm/tcg/translate-a64.c
25
@@ -XXX,XX +XXX,XX @@ static bool trans_ERET(DisasContext *s, arg_ERET *a)
26
return false;
27
}
28
if (s->fgt_eret) {
29
- gen_exception_insn_el(s, 0, EXCP_UDEF, 0, 2);
30
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(0), 2);
31
return true;
32
}
33
dst = tcg_temp_new_i64();
34
@@ -XXX,XX +XXX,XX @@ static bool trans_ERETA(DisasContext *s, arg_reta *a)
35
}
36
/* The FGT trap takes precedence over an auth trap. */
37
if (s->fgt_eret) {
38
- gen_exception_insn_el(s, 0, EXCP_UDEF, a->m ? 3 : 2, 2);
39
+ gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(a->m ? 3 : 2), 2);
40
return true;
41
}
42
dst = tcg_temp_new_i64();
43
--
44
2.34.1
diff view generated by jsdifflib
New patch
[PULL 10/41] hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
"hw/arm/boot.h" is only required on the source file.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@amd.com>
8
Message-id: 20231025065316.56817-2-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/allwinner-a10.h | 1 -
12
hw/arm/cubieboard.c | 1 +
13
2 files changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/allwinner-a10.h
18
+++ b/include/hw/arm/allwinner-a10.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef HW_ARM_ALLWINNER_A10_H
21
#define HW_ARM_ALLWINNER_A10_H
22
23
-#include "hw/arm/boot.h"
24
#include "hw/timer/allwinner-a10-pit.h"
25
#include "hw/intc/allwinner-a10-pic.h"
26
#include "hw/net/allwinner_emac.h"
27
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/cubieboard.c
30
+++ b/hw/arm/cubieboard.c
31
@@ -XXX,XX +XXX,XX @@
32
#include "hw/boards.h"
33
#include "hw/qdev-properties.h"
34
#include "hw/arm/allwinner-a10.h"
35
+#include "hw/arm/boot.h"
36
#include "hw/i2c/i2c.h"
37
38
static struct arm_boot_info cubieboard_binfo = {
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 11/41] hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
"hw/arm/boot.h" is only required on the source file.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@amd.com>
8
Message-id: 20231025065316.56817-3-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/allwinner-h3.h | 1 -
12
hw/arm/orangepi.c | 1 +
13
2 files changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/allwinner-h3.h
18
+++ b/include/hw/arm/allwinner-h3.h
19
@@ -XXX,XX +XXX,XX @@
20
#define HW_ARM_ALLWINNER_H3_H
21
22
#include "qom/object.h"
23
-#include "hw/arm/boot.h"
24
#include "hw/timer/allwinner-a10-pit.h"
25
#include "hw/intc/arm_gic.h"
26
#include "hw/misc/allwinner-h3-ccu.h"
27
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/orangepi.c
30
+++ b/hw/arm/orangepi.c
31
@@ -XXX,XX +XXX,XX @@
32
#include "hw/boards.h"
33
#include "hw/qdev-properties.h"
34
#include "hw/arm/allwinner-h3.h"
35
+#include "hw/arm/boot.h"
36
37
static struct arm_boot_info orangepi_binfo;
38
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 12/41] hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
"hw/arm/boot.h" is only required on the source file.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@amd.com>
8
Message-id: 20231025065316.56817-4-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/allwinner-r40.h | 1 -
12
hw/arm/bananapi_m2u.c | 1 +
13
2 files changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/allwinner-r40.h
18
+++ b/include/hw/arm/allwinner-r40.h
19
@@ -XXX,XX +XXX,XX @@
20
#define HW_ARM_ALLWINNER_R40_H
21
22
#include "qom/object.h"
23
-#include "hw/arm/boot.h"
24
#include "hw/timer/allwinner-a10-pit.h"
25
#include "hw/intc/arm_gic.h"
26
#include "hw/sd/allwinner-sdhost.h"
27
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/bananapi_m2u.c
30
+++ b/hw/arm/bananapi_m2u.c
31
@@ -XXX,XX +XXX,XX @@
32
#include "hw/i2c/i2c.h"
33
#include "hw/qdev-properties.h"
34
#include "hw/arm/allwinner-r40.h"
35
+#include "hw/arm/boot.h"
36
37
static struct arm_boot_info bpim2u_binfo;
38
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 13/41] hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
"hw/arm/boot.h" is only required on the source file.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@amd.com>
8
Message-id: 20231025065316.56817-5-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx25.h | 1 -
12
hw/arm/imx25_pdk.c | 1 +
13
2 files changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx25.h
18
+++ b/include/hw/arm/fsl-imx25.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef FSL_IMX25_H
21
#define FSL_IMX25_H
22
23
-#include "hw/arm/boot.h"
24
#include "hw/intc/imx_avic.h"
25
#include "hw/misc/imx25_ccm.h"
26
#include "hw/char/imx_serial.h"
27
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/imx25_pdk.c
30
+++ b/hw/arm/imx25_pdk.c
31
@@ -XXX,XX +XXX,XX @@
32
#include "qapi/error.h"
33
#include "hw/qdev-properties.h"
34
#include "hw/arm/fsl-imx25.h"
35
+#include "hw/arm/boot.h"
36
#include "hw/boards.h"
37
#include "qemu/error-report.h"
38
#include "sysemu/qtest.h"
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 14/41] hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
"hw/arm/boot.h" is only required on the source file.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@amd.com>
8
Message-id: 20231025065316.56817-6-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx31.h | 1 -
12
hw/arm/kzm.c | 1 +
13
2 files changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx31.h
18
+++ b/include/hw/arm/fsl-imx31.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef FSL_IMX31_H
21
#define FSL_IMX31_H
22
23
-#include "hw/arm/boot.h"
24
#include "hw/intc/imx_avic.h"
25
#include "hw/misc/imx31_ccm.h"
26
#include "hw/char/imx_serial.h"
27
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/kzm.c
30
+++ b/hw/arm/kzm.c
31
@@ -XXX,XX +XXX,XX @@
32
#include "qemu/osdep.h"
33
#include "qapi/error.h"
34
#include "hw/arm/fsl-imx31.h"
35
+#include "hw/arm/boot.h"
36
#include "hw/boards.h"
37
#include "qemu/error-report.h"
38
#include "exec/address-spaces.h"
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 15/41] hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
"hw/arm/boot.h" is only required on the source file.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@amd.com>
8
Message-id: 20231025065316.56817-7-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx6.h | 1 -
12
hw/arm/sabrelite.c | 1 +
13
2 files changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx6.h
18
+++ b/include/hw/arm/fsl-imx6.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef FSL_IMX6_H
21
#define FSL_IMX6_H
22
23
-#include "hw/arm/boot.h"
24
#include "hw/cpu/a9mpcore.h"
25
#include "hw/misc/imx6_ccm.h"
26
#include "hw/misc/imx6_src.h"
27
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/sabrelite.c
30
+++ b/hw/arm/sabrelite.c
31
@@ -XXX,XX +XXX,XX @@
32
#include "qemu/osdep.h"
33
#include "qapi/error.h"
34
#include "hw/arm/fsl-imx6.h"
35
+#include "hw/arm/boot.h"
36
#include "hw/boards.h"
37
#include "hw/qdev-properties.h"
38
#include "qemu/error-report.h"
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 16/41] hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
"hw/arm/boot.h" is only required on the source file.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@amd.com>
8
Message-id: 20231025065316.56817-8-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx6ul.h | 1 -
12
hw/arm/mcimx6ul-evk.c | 1 +
13
2 files changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx6ul.h
18
+++ b/include/hw/arm/fsl-imx6ul.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef FSL_IMX6UL_H
21
#define FSL_IMX6UL_H
22
23
-#include "hw/arm/boot.h"
24
#include "hw/cpu/a15mpcore.h"
25
#include "hw/misc/imx6ul_ccm.h"
26
#include "hw/misc/imx6_src.h"
27
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/mcimx6ul-evk.c
30
+++ b/hw/arm/mcimx6ul-evk.c
31
@@ -XXX,XX +XXX,XX @@
32
#include "qemu/osdep.h"
33
#include "qapi/error.h"
34
#include "hw/arm/fsl-imx6ul.h"
35
+#include "hw/arm/boot.h"
36
#include "hw/boards.h"
37
#include "hw/qdev-properties.h"
38
#include "qemu/error-report.h"
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 17/41] hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
"hw/arm/boot.h" is only required on the source file.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@amd.com>
8
Message-id: 20231025065316.56817-9-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx7.h | 1 -
12
hw/arm/mcimx7d-sabre.c | 1 +
13
2 files changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx7.h
18
+++ b/include/hw/arm/fsl-imx7.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef FSL_IMX7_H
21
#define FSL_IMX7_H
22
23
-#include "hw/arm/boot.h"
24
#include "hw/cpu/a15mpcore.h"
25
#include "hw/intc/imx_gpcv2.h"
26
#include "hw/misc/imx7_ccm.h"
27
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/mcimx7d-sabre.c
30
+++ b/hw/arm/mcimx7d-sabre.c
31
@@ -XXX,XX +XXX,XX @@
32
#include "qemu/osdep.h"
33
#include "qapi/error.h"
34
#include "hw/arm/fsl-imx7.h"
35
+#include "hw/arm/boot.h"
36
#include "hw/boards.h"
37
#include "hw/qdev-properties.h"
38
#include "qemu/error-report.h"
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 18/41] hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
"hw/arm/boot.h" is only required on the source file.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@amd.com>
8
Message-id: 20231025065316.56817-10-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/xlnx-versal.h | 1 -
12
hw/arm/xlnx-versal-virt.c | 1 +
13
2 files changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/xlnx-versal.h
18
+++ b/include/hw/arm/xlnx-versal.h
19
@@ -XXX,XX +XXX,XX @@
20
#define XLNX_VERSAL_H
21
22
#include "hw/sysbus.h"
23
-#include "hw/arm/boot.h"
24
#include "hw/cpu/cluster.h"
25
#include "hw/or-irq.h"
26
#include "hw/sd/sdhci.h"
27
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/xlnx-versal-virt.c
30
+++ b/hw/arm/xlnx-versal-virt.c
31
@@ -XXX,XX +XXX,XX @@
32
#include "cpu.h"
33
#include "hw/qdev-properties.h"
34
#include "hw/arm/xlnx-versal.h"
35
+#include "hw/arm/boot.h"
36
#include "qom/object.h"
37
38
#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 19/41] hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
"hw/arm/boot.h" is only required on the source file.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@amd.com>
8
Message-id: 20231025065316.56817-11-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/xlnx-zynqmp.h | 1 -
12
hw/arm/xlnx-zcu102.c | 1 +
13
2 files changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/xlnx-zynqmp.h
18
+++ b/include/hw/arm/xlnx-zynqmp.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef XLNX_ZYNQMP_H
21
#define XLNX_ZYNQMP_H
22
23
-#include "hw/arm/boot.h"
24
#include "hw/intc/arm_gic.h"
25
#include "hw/net/cadence_gem.h"
26
#include "hw/char/cadence_uart.h"
27
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/xlnx-zcu102.c
30
+++ b/hw/arm/xlnx-zcu102.c
31
@@ -XXX,XX +XXX,XX @@
32
#include "qemu/osdep.h"
33
#include "qapi/error.h"
34
#include "hw/arm/xlnx-zynqmp.h"
35
+#include "hw/arm/boot.h"
36
#include "hw/boards.h"
37
#include "qemu/error-report.h"
38
#include "qemu/log.h"
39
--
40
2.34.1
41
42
diff view generated by jsdifflib
New patch
[PULL 20/41] hw/sd/pxa2xx: Realize sysbus device before accessing it
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
sysbus_mmio_map() and sysbus_connect_irq() should not be
4
called on unrealized device.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Thomas Huth <thuth@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20231020130331.50048-2-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/sd/pxa2xx_mmci.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/sd/pxa2xx_mmci.c
18
+++ b/hw/sd/pxa2xx_mmci.c
19
@@ -XXX,XX +XXX,XX @@ PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
20
21
dev = qdev_new(TYPE_PXA2XX_MMCI);
22
sbd = SYS_BUS_DEVICE(dev);
23
+ sysbus_realize_and_unref(sbd, &error_fatal);
24
sysbus_mmio_map(sbd, 0, base);
25
sysbus_connect_irq(sbd, 0, irq);
26
qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
27
qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
28
- sysbus_realize_and_unref(sbd, &error_fatal);
29
30
return PXA2XX_MMCI(dev);
31
}
32
--
33
2.34.1
34
35
diff view generated by jsdifflib
New patch
[PULL 21/41] hw/sd/pxa2xx: Do not open-code sysbus_create_simple()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Thomas Huth <thuth@redhat.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20231020130331.50048-3-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/sd/pxa2xx_mmci.c | 7 +------
10
1 file changed, 1 insertion(+), 6 deletions(-)
11
12
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/sd/pxa2xx_mmci.c
15
+++ b/hw/sd/pxa2xx_mmci.c
16
@@ -XXX,XX +XXX,XX @@ PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
17
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
18
{
19
DeviceState *dev;
20
- SysBusDevice *sbd;
21
22
- dev = qdev_new(TYPE_PXA2XX_MMCI);
23
- sbd = SYS_BUS_DEVICE(dev);
24
- sysbus_realize_and_unref(sbd, &error_fatal);
25
- sysbus_mmio_map(sbd, 0, base);
26
- sysbus_connect_irq(sbd, 0, irq);
27
+ dev = sysbus_create_simple(TYPE_PXA2XX_MMCI, base, irq);
28
qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
29
qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
30
31
--
32
2.34.1
33
34
diff view generated by jsdifflib
New patch
[PULL 22/41] hw/pcmcia/pxa2xx: Realize sysbus device before accessing it
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
sysbus_mmio_map() should not be called on unrealized device.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Thomas Huth <thuth@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20231020130331.50048-4-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/pcmcia/pxa2xx.c | 7 ++-----
12
1 file changed, 2 insertions(+), 5 deletions(-)
13
14
diff --git a/hw/pcmcia/pxa2xx.c b/hw/pcmcia/pxa2xx.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/pcmcia/pxa2xx.c
17
+++ b/hw/pcmcia/pxa2xx.c
18
@@ -XXX,XX +XXX,XX @@ PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
19
hwaddr base)
20
{
21
DeviceState *dev;
22
- PXA2xxPCMCIAState *s;
23
24
dev = qdev_new(TYPE_PXA2XX_PCMCIA);
25
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
26
- s = PXA2XX_PCMCIA(dev);
27
-
28
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
29
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
30
31
- return s;
32
+ return PXA2XX_PCMCIA(dev);
33
}
34
35
static void pxa2xx_pcmcia_initfn(Object *obj)
36
--
37
2.34.1
38
39
diff view generated by jsdifflib
New patch
[PULL 23/41] hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Reviewed-by: Thomas Huth <thuth@redhat.com>
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20231020130331.50048-5-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/pcmcia/pxa2xx.c | 4 +---
10
1 file changed, 1 insertion(+), 3 deletions(-)
11
12
diff --git a/hw/pcmcia/pxa2xx.c b/hw/pcmcia/pxa2xx.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/pcmcia/pxa2xx.c
15
+++ b/hw/pcmcia/pxa2xx.c
16
@@ -XXX,XX +XXX,XX @@ PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
17
{
18
DeviceState *dev;
19
20
- dev = qdev_new(TYPE_PXA2XX_PCMCIA);
21
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
22
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
23
+ dev = sysbus_create_simple(TYPE_PXA2XX_PCMCIA, base, NULL);
24
25
return PXA2XX_PCMCIA(dev);
26
}
27
--
28
2.34.1
29
30
diff view generated by jsdifflib
New patch
[PULL 24/41] hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Reviewed-by: Thomas Huth <thuth@redhat.com>
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20231020130331.50048-6-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
include/hw/arm/pxa.h | 2 --
10
hw/arm/pxa2xx.c | 12 ++++++++----
11
hw/pcmcia/pxa2xx.c | 10 ----------
12
3 files changed, 8 insertions(+), 16 deletions(-)
13
14
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/arm/pxa.h
17
+++ b/include/hw/arm/pxa.h
18
@@ -XXX,XX +XXX,XX @@ void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
19
#define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia"
20
OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPCMCIAState, PXA2XX_PCMCIA)
21
22
-PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
23
- hwaddr base);
24
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
25
int pxa2xx_pcmcia_detach(void *opaque);
26
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
27
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/arm/pxa2xx.c
30
+++ b/hw/arm/pxa2xx.c
31
@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *cpu_type)
32
sysbus_create_simple("sysbus-ohci", 0x4c000000,
33
qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
34
35
- s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
36
- s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
37
+ s->pcmcia[0] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA,
38
+ 0x20000000, NULL));
39
+ s->pcmcia[1] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA,
40
+ 0x30000000, NULL));
41
42
sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
43
qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
44
@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
45
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
46
}
47
48
- s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
49
- s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
50
+ s->pcmcia[0] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA,
51
+ 0x20000000, NULL));
52
+ s->pcmcia[1] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA,
53
+ 0x30000000, NULL));
54
55
sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000,
56
qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
57
diff --git a/hw/pcmcia/pxa2xx.c b/hw/pcmcia/pxa2xx.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/pcmcia/pxa2xx.c
60
+++ b/hw/pcmcia/pxa2xx.c
61
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level)
62
qemu_set_irq(s->irq, level);
63
}
64
65
-PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
66
- hwaddr base)
67
-{
68
- DeviceState *dev;
69
-
70
- dev = sysbus_create_simple(TYPE_PXA2XX_PCMCIA, base, NULL);
71
-
72
- return PXA2XX_PCMCIA(dev);
73
-}
74
-
75
static void pxa2xx_pcmcia_initfn(Object *obj)
76
{
77
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
78
--
79
2.34.1
80
81
diff view generated by jsdifflib
New patch
[PULL 25/41] hw/intc/pxa2xx: Convert to Resettable interface
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Factor reset code out of the DeviceRealize() handler.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Thomas Huth <thuth@redhat.com>
8
Message-id: 20231020130331.50048-7-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/pxa2xx_pic.c | 17 ++++++++++++-----
12
1 file changed, 12 insertions(+), 5 deletions(-)
13
14
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/pxa2xx_pic.c
17
+++ b/hw/arm/pxa2xx_pic.c
18
@@ -XXX,XX +XXX,XX @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
19
return 0;
20
}
21
22
-DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
23
+static void pxa2xx_pic_reset_hold(Object *obj)
24
{
25
- DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
26
- PXA2xxPICState *s = PXA2XX_PIC(dev);
27
-
28
- s->cpu = cpu;
29
+ PXA2xxPICState *s = PXA2XX_PIC(obj);
30
31
s->int_pending[0] = 0;
32
s->int_pending[1] = 0;
33
@@ -XXX,XX +XXX,XX @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
34
s->int_enabled[1] = 0;
35
s->is_fiq[0] = 0;
36
s->is_fiq[1] = 0;
37
+}
38
+
39
+DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
40
+{
41
+ DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
42
+ PXA2xxPICState *s = PXA2XX_PIC(dev);
43
+
44
+ s->cpu = cpu;
45
46
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
47
48
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pxa2xx_pic_regs = {
49
static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
50
{
51
DeviceClass *dc = DEVICE_CLASS(klass);
52
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
53
54
dc->desc = "PXA2xx PIC";
55
dc->vmsd = &vmstate_pxa2xx_pic_regs;
56
+ rc->phases.hold = pxa2xx_pic_reset_hold;
57
}
58
59
static const TypeInfo pxa2xx_pic_info = {
60
--
61
2.34.1
62
63
diff view generated by jsdifflib
New patch
[PULL 26/41] hw/intc/pxa2xx: Pass CPU reference using QOM link property
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
QOM objects shouldn't access each other internals fields
4
except using the QOM API.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Thomas Huth <thuth@redhat.com>
9
Message-id: 20231020130331.50048-8-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/pxa2xx_pic.c | 11 ++++++++++-
13
1 file changed, 10 insertions(+), 1 deletion(-)
14
15
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/pxa2xx_pic.c
18
+++ b/hw/arm/pxa2xx_pic.c
19
@@ -XXX,XX +XXX,XX @@
20
#include "cpu.h"
21
#include "hw/arm/pxa.h"
22
#include "hw/sysbus.h"
23
+#include "hw/qdev-properties.h"
24
#include "migration/vmstate.h"
25
#include "qom/object.h"
26
#include "target/arm/cpregs.h"
27
@@ -XXX,XX +XXX,XX @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
28
DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
29
PXA2xxPICState *s = PXA2XX_PIC(dev);
30
31
- s->cpu = cpu;
32
+ object_property_set_link(OBJECT(dev), "arm-cpu",
33
+ OBJECT(cpu), &error_abort);
34
35
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
36
37
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pxa2xx_pic_regs = {
38
},
39
};
40
41
+static Property pxa2xx_pic_properties[] = {
42
+ DEFINE_PROP_LINK("arm-cpu", PXA2xxPICState, cpu,
43
+ TYPE_ARM_CPU, ARMCPU *),
44
+ DEFINE_PROP_END_OF_LIST(),
45
+};
46
+
47
static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
48
{
49
DeviceClass *dc = DEVICE_CLASS(klass);
50
ResettableClass *rc = RESETTABLE_CLASS(klass);
51
52
+ device_class_set_props(dc, pxa2xx_pic_properties);
53
dc->desc = "PXA2xx PIC";
54
dc->vmsd = &vmstate_pxa2xx_pic_regs;
55
rc->phases.hold = pxa2xx_pic_reset_hold;
56
--
57
2.34.1
58
59
diff view generated by jsdifflib
New patch
[PULL 27/41] hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Thomas Huth <thuth@redhat.com>
6
Message-id: 20231020130331.50048-9-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/arm/pxa2xx_pic.c | 16 ++++++++++------
10
1 file changed, 10 insertions(+), 6 deletions(-)
11
12
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/arm/pxa2xx_pic.c
15
+++ b/hw/arm/pxa2xx_pic.c
16
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pic_reset_hold(Object *obj)
17
DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
18
{
19
DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC);
20
- PXA2xxPICState *s = PXA2XX_PIC(dev);
21
22
object_property_set_link(OBJECT(dev), "arm-cpu",
23
OBJECT(cpu), &error_abort);
24
-
25
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
26
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
27
+
28
+ return dev;
29
+}
30
+
31
+static void pxa2xx_pic_realize(DeviceState *dev, Error **errp)
32
+{
33
+ PXA2xxPICState *s = PXA2XX_PIC(dev);
34
35
qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
36
37
@@ -XXX,XX +XXX,XX @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu)
38
memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s,
39
"pxa2xx-pic", 0x00100000);
40
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
41
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
42
43
/* Enable IC coprocessor access. */
44
- define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s);
45
-
46
- return dev;
47
+ define_arm_cp_regs_with_opaque(s->cpu, pxa_pic_cp_reginfo, s);
48
}
49
50
static const VMStateDescription vmstate_pxa2xx_pic_regs = {
51
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pic_class_init(ObjectClass *klass, void *data)
52
ResettableClass *rc = RESETTABLE_CLASS(klass);
53
54
device_class_set_props(dc, pxa2xx_pic_properties);
55
+ dc->realize = pxa2xx_pic_realize;
56
dc->desc = "PXA2xx PIC";
57
dc->vmsd = &vmstate_pxa2xx_pic_regs;
58
rc->phases.hold = pxa2xx_pic_reset_hold;
59
--
60
2.34.1
61
62
diff view generated by jsdifflib
New patch
[PULL 28/41] hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
qbus_new(), called in i2c_init_bus(), should not be called
4
on unrealized device.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Thomas Huth <thuth@redhat.com>
9
Message-id: 20231020130331.50048-10-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/pxa2xx.c | 5 +++--
13
1 file changed, 3 insertions(+), 2 deletions(-)
14
15
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/pxa2xx.c
18
+++ b/hw/arm/pxa2xx.c
19
@@ -XXX,XX +XXX,XX @@ PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
20
qdev_prop_set_uint32(dev, "size", region_size + 1);
21
qdev_prop_set_uint32(dev, "offset", base & region_size);
22
23
+ /* FIXME: Should the slave device really be on a separate bus? */
24
+ i2cbus = i2c_init_bus(dev, "dummy");
25
+
26
i2c_dev = SYS_BUS_DEVICE(dev);
27
sysbus_realize_and_unref(i2c_dev, &error_fatal);
28
sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
29
sysbus_connect_irq(i2c_dev, 0, irq);
30
31
s = PXA2XX_I2C(i2c_dev);
32
- /* FIXME: Should the slave device really be on a separate bus? */
33
- i2cbus = i2c_init_bus(dev, "dummy");
34
s->slave = PXA2XX_I2C_SLAVE(i2c_slave_create_simple(i2cbus,
35
TYPE_PXA2XX_I2C_SLAVE,
36
0));
37
--
38
2.34.1
39
40
diff view generated by jsdifflib
New patch
[PULL 29/41] hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Prefer using a well known local first CPU rather than a global one.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20231025065909.57344-1-philmd@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/bananapi_m2u.c | 2 +-
11
hw/arm/exynos4_boards.c | 7 ++++---
12
hw/arm/orangepi.c | 2 +-
13
hw/arm/realview.c | 2 +-
14
hw/arm/xilinx_zynq.c | 2 +-
15
5 files changed, 8 insertions(+), 7 deletions(-)
16
17
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/bananapi_m2u.c
20
+++ b/hw/arm/bananapi_m2u.c
21
@@ -XXX,XX +XXX,XX @@ static void bpim2u_init(MachineState *machine)
22
bpim2u_binfo.loader_start = r40->memmap[AW_R40_DEV_SDRAM];
23
bpim2u_binfo.ram_size = machine->ram_size;
24
bpim2u_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
25
- arm_load_kernel(ARM_CPU(first_cpu), machine, &bpim2u_binfo);
26
+ arm_load_kernel(&r40->cpus[0], machine, &bpim2u_binfo);
27
}
28
29
static void bpim2u_machine_init(MachineClass *mc)
30
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/exynos4_boards.c
33
+++ b/hw/arm/exynos4_boards.c
34
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
35
36
static void nuri_init(MachineState *machine)
37
{
38
- exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI);
39
+ Exynos4BoardState *s = exynos4_boards_init_common(machine,
40
+ EXYNOS4_BOARD_NURI);
41
42
- arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo);
43
+ arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo);
44
}
45
46
static void smdkc210_init(MachineState *machine)
47
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
48
49
lan9215_init(SMDK_LAN9118_BASE_ADDR,
50
qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
51
- arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo);
52
+ arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo);
53
}
54
55
static void nuri_class_init(ObjectClass *oc, void *data)
56
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/arm/orangepi.c
59
+++ b/hw/arm/orangepi.c
60
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
61
orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM];
62
orangepi_binfo.ram_size = machine->ram_size;
63
orangepi_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC;
64
- arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
65
+ arm_load_kernel(&h3->cpus[0], machine, &orangepi_binfo);
66
}
67
68
static void orangepi_machine_init(MachineClass *mc)
69
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/arm/realview.c
72
+++ b/hw/arm/realview.c
73
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
74
realview_binfo.ram_size = ram_size;
75
realview_binfo.board_id = realview_board_id[board_type];
76
realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
77
- arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo);
78
+ arm_load_kernel(cpu, machine, &realview_binfo);
79
}
80
81
static void realview_eb_init(MachineState *machine)
82
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/arm/xilinx_zynq.c
85
+++ b/hw/arm/xilinx_zynq.c
86
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
87
zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
88
zynq_binfo.write_board_setup = zynq_write_board_setup;
89
90
- arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo);
91
+ arm_load_kernel(cpu, machine, &zynq_binfo);
92
}
93
94
static void zynq_machine_class_init(ObjectClass *oc, void *data)
95
--
96
2.34.1
97
98
diff view generated by jsdifflib
New patch
[PULL 30/41] misc/led: LED state is set opposite of what is expected
1
From: Glenn Miles <milesg@linux.vnet.ibm.com>
1
2
3
Testing of the LED state showed that when the LED polarity was
4
set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on
5
the input GPIO of the LED, the LED was being turn off when it was
6
expected to be turned on.
7
8
Fixes: ddb67f6402 ("hw/misc/led: Allow connecting from GPIO output")
9
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
12
Message-id: 20231024191945.4135036-1-milesg@linux.vnet.ibm.com
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/misc/led.c | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
18
19
diff --git a/hw/misc/led.c b/hw/misc/led.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/misc/led.c
22
+++ b/hw/misc/led.c
23
@@ -XXX,XX +XXX,XX @@ static void led_set_state_gpio_handler(void *opaque, int line, int new_state)
24
LEDState *s = LED(opaque);
25
26
assert(line == 0);
27
- led_set_state(s, !!new_state != s->gpio_active_high);
28
+ led_set_state(s, !!new_state == s->gpio_active_high);
29
}
30
31
static void led_reset(DeviceState *dev)
32
--
33
2.34.1
34
35
diff view generated by jsdifflib
New patch
[PULL 31/41] hw/net/cadence_gem: use REG32 macro for register definitions
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
Replace register defines with the REG32 macro from registerfields.h in
4
the Cadence GEM device.
5
6
Signed-off-by: Luc Michel <luc.michel@amd.com>
7
Reviewed-by: sai.pavan.boddu@amd.com
8
Message-id: 20231017194422.4124691-2-luc.michel@amd.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/net/cadence_gem.c | 527 +++++++++++++++++++++----------------------
12
1 file changed, 261 insertions(+), 266 deletions(-)
13
14
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/cadence_gem.c
17
+++ b/hw/net/cadence_gem.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/irq.h"
20
#include "hw/net/cadence_gem.h"
21
#include "hw/qdev-properties.h"
22
+#include "hw/registerfields.h"
23
#include "migration/vmstate.h"
24
#include "qapi/error.h"
25
#include "qemu/log.h"
26
@@ -XXX,XX +XXX,XX @@
27
} \
28
} while (0)
29
30
-#define GEM_NWCTRL (0x00000000 / 4) /* Network Control reg */
31
-#define GEM_NWCFG (0x00000004 / 4) /* Network Config reg */
32
-#define GEM_NWSTATUS (0x00000008 / 4) /* Network Status reg */
33
-#define GEM_USERIO (0x0000000C / 4) /* User IO reg */
34
-#define GEM_DMACFG (0x00000010 / 4) /* DMA Control reg */
35
-#define GEM_TXSTATUS (0x00000014 / 4) /* TX Status reg */
36
-#define GEM_RXQBASE (0x00000018 / 4) /* RX Q Base address reg */
37
-#define GEM_TXQBASE (0x0000001C / 4) /* TX Q Base address reg */
38
-#define GEM_RXSTATUS (0x00000020 / 4) /* RX Status reg */
39
-#define GEM_ISR (0x00000024 / 4) /* Interrupt Status reg */
40
-#define GEM_IER (0x00000028 / 4) /* Interrupt Enable reg */
41
-#define GEM_IDR (0x0000002C / 4) /* Interrupt Disable reg */
42
-#define GEM_IMR (0x00000030 / 4) /* Interrupt Mask reg */
43
-#define GEM_PHYMNTNC (0x00000034 / 4) /* Phy Maintenance reg */
44
-#define GEM_RXPAUSE (0x00000038 / 4) /* RX Pause Time reg */
45
-#define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */
46
-#define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and Forward */
47
-#define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and Forward */
48
-#define GEM_JUMBO_MAX_LEN (0x00000048 / 4) /* Max Jumbo Frame Size */
49
-#define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */
50
-#define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */
51
-#define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */
52
-#define GEM_SPADDR1HI (0x0000008C / 4) /* Specific addr 1 high reg */
53
-#define GEM_SPADDR2LO (0x00000090 / 4) /* Specific addr 2 low reg */
54
-#define GEM_SPADDR2HI (0x00000094 / 4) /* Specific addr 2 high reg */
55
-#define GEM_SPADDR3LO (0x00000098 / 4) /* Specific addr 3 low reg */
56
-#define GEM_SPADDR3HI (0x0000009C / 4) /* Specific addr 3 high reg */
57
-#define GEM_SPADDR4LO (0x000000A0 / 4) /* Specific addr 4 low reg */
58
-#define GEM_SPADDR4HI (0x000000A4 / 4) /* Specific addr 4 high reg */
59
-#define GEM_TIDMATCH1 (0x000000A8 / 4) /* Type ID1 Match reg */
60
-#define GEM_TIDMATCH2 (0x000000AC / 4) /* Type ID2 Match reg */
61
-#define GEM_TIDMATCH3 (0x000000B0 / 4) /* Type ID3 Match reg */
62
-#define GEM_TIDMATCH4 (0x000000B4 / 4) /* Type ID4 Match reg */
63
-#define GEM_WOLAN (0x000000B8 / 4) /* Wake on LAN reg */
64
-#define GEM_IPGSTRETCH (0x000000BC / 4) /* IPG Stretch reg */
65
-#define GEM_SVLAN (0x000000C0 / 4) /* Stacked VLAN reg */
66
-#define GEM_MODID (0x000000FC / 4) /* Module ID reg */
67
-#define GEM_OCTTXLO (0x00000100 / 4) /* Octets transmitted Low reg */
68
-#define GEM_OCTTXHI (0x00000104 / 4) /* Octets transmitted High reg */
69
-#define GEM_TXCNT (0x00000108 / 4) /* Error-free Frames transmitted */
70
-#define GEM_TXBCNT (0x0000010C / 4) /* Error-free Broadcast Frames */
71
-#define GEM_TXMCNT (0x00000110 / 4) /* Error-free Multicast Frame */
72
-#define GEM_TXPAUSECNT (0x00000114 / 4) /* Pause Frames Transmitted */
73
-#define GEM_TX64CNT (0x00000118 / 4) /* Error-free 64 TX */
74
-#define GEM_TX65CNT (0x0000011C / 4) /* Error-free 65-127 TX */
75
-#define GEM_TX128CNT (0x00000120 / 4) /* Error-free 128-255 TX */
76
-#define GEM_TX256CNT (0x00000124 / 4) /* Error-free 256-511 */
77
-#define GEM_TX512CNT (0x00000128 / 4) /* Error-free 512-1023 TX */
78
-#define GEM_TX1024CNT (0x0000012C / 4) /* Error-free 1024-1518 TX */
79
-#define GEM_TX1519CNT (0x00000130 / 4) /* Error-free larger than 1519 TX */
80
-#define GEM_TXURUNCNT (0x00000134 / 4) /* TX under run error counter */
81
-#define GEM_SINGLECOLLCNT (0x00000138 / 4) /* Single Collision Frames */
82
-#define GEM_MULTCOLLCNT (0x0000013C / 4) /* Multiple Collision Frames */
83
-#define GEM_EXCESSCOLLCNT (0x00000140 / 4) /* Excessive Collision Frames */
84
-#define GEM_LATECOLLCNT (0x00000144 / 4) /* Late Collision Frames */
85
-#define GEM_DEFERTXCNT (0x00000148 / 4) /* Deferred Transmission Frames */
86
-#define GEM_CSENSECNT (0x0000014C / 4) /* Carrier Sense Error Counter */
87
-#define GEM_OCTRXLO (0x00000150 / 4) /* Octets Received register Low */
88
-#define GEM_OCTRXHI (0x00000154 / 4) /* Octets Received register High */
89
-#define GEM_RXCNT (0x00000158 / 4) /* Error-free Frames Received */
90
-#define GEM_RXBROADCNT (0x0000015C / 4) /* Error-free Broadcast Frames RX */
91
-#define GEM_RXMULTICNT (0x00000160 / 4) /* Error-free Multicast Frames RX */
92
-#define GEM_RXPAUSECNT (0x00000164 / 4) /* Pause Frames Received Counter */
93
-#define GEM_RX64CNT (0x00000168 / 4) /* Error-free 64 byte Frames RX */
94
-#define GEM_RX65CNT (0x0000016C / 4) /* Error-free 65-127B Frames RX */
95
-#define GEM_RX128CNT (0x00000170 / 4) /* Error-free 128-255B Frames RX */
96
-#define GEM_RX256CNT (0x00000174 / 4) /* Error-free 256-512B Frames RX */
97
-#define GEM_RX512CNT (0x00000178 / 4) /* Error-free 512-1023B Frames RX */
98
-#define GEM_RX1024CNT (0x0000017C / 4) /* Error-free 1024-1518B Frames RX */
99
-#define GEM_RX1519CNT (0x00000180 / 4) /* Error-free 1519-max Frames RX */
100
-#define GEM_RXUNDERCNT (0x00000184 / 4) /* Undersize Frames Received */
101
-#define GEM_RXOVERCNT (0x00000188 / 4) /* Oversize Frames Received */
102
-#define GEM_RXJABCNT (0x0000018C / 4) /* Jabbers Received Counter */
103
-#define GEM_RXFCSCNT (0x00000190 / 4) /* Frame Check seq. Error Counter */
104
-#define GEM_RXLENERRCNT (0x00000194 / 4) /* Length Field Error Counter */
105
-#define GEM_RXSYMERRCNT (0x00000198 / 4) /* Symbol Error Counter */
106
-#define GEM_RXALIGNERRCNT (0x0000019C / 4) /* Alignment Error Counter */
107
-#define GEM_RXRSCERRCNT (0x000001A0 / 4) /* Receive Resource Error Counter */
108
-#define GEM_RXORUNCNT (0x000001A4 / 4) /* Receive Overrun Counter */
109
-#define GEM_RXIPCSERRCNT (0x000001A8 / 4) /* IP header Checksum Err Counter */
110
-#define GEM_RXTCPCCNT (0x000001AC / 4) /* TCP Checksum Error Counter */
111
-#define GEM_RXUDPCCNT (0x000001B0 / 4) /* UDP Checksum Error Counter */
112
+REG32(NWCTRL, 0x0) /* Network Control reg */
113
+REG32(NWCFG, 0x4) /* Network Config reg */
114
+REG32(NWSTATUS, 0x8) /* Network Status reg */
115
+REG32(USERIO, 0xc) /* User IO reg */
116
+REG32(DMACFG, 0x10) /* DMA Control reg */
117
+REG32(TXSTATUS, 0x14) /* TX Status reg */
118
+REG32(RXQBASE, 0x18) /* RX Q Base address reg */
119
+REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
120
+REG32(RXSTATUS, 0x20) /* RX Status reg */
121
+REG32(ISR, 0x24) /* Interrupt Status reg */
122
+REG32(IER, 0x28) /* Interrupt Enable reg */
123
+REG32(IDR, 0x2c) /* Interrupt Disable reg */
124
+REG32(IMR, 0x30) /* Interrupt Mask reg */
125
+REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
126
+REG32(RXPAUSE, 0x38) /* RX Pause Time reg */
127
+REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
128
+REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
129
+REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */
130
+REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */
131
+REG32(HASHLO, 0x80) /* Hash Low address reg */
132
+REG32(HASHHI, 0x84) /* Hash High address reg */
133
+REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */
134
+REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */
135
+REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */
136
+REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */
137
+REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */
138
+REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */
139
+REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */
140
+REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */
141
+REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */
142
+REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */
143
+REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */
144
+REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */
145
+REG32(WOLAN, 0xb8) /* Wake on LAN reg */
146
+REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */
147
+REG32(SVLAN, 0xc0) /* Stacked VLAN reg */
148
+REG32(MODID, 0xfc) /* Module ID reg */
149
+REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */
150
+REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */
151
+REG32(TXCNT, 0x108) /* Error-free Frames transmitted */
152
+REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */
153
+REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */
154
+REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */
155
+REG32(TX64CNT, 0x118) /* Error-free 64 TX */
156
+REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */
157
+REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */
158
+REG32(TX256CNT, 0x124) /* Error-free 256-511 */
159
+REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */
160
+REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */
161
+REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */
162
+REG32(TXURUNCNT, 0x134) /* TX under run error counter */
163
+REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */
164
+REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */
165
+REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */
166
+REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */
167
+REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */
168
+REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */
169
+REG32(OCTRXLO, 0x150) /* Octects Received register Low */
170
+REG32(OCTRXHI, 0x154) /* Octects Received register High */
171
+REG32(RXCNT, 0x158) /* Error-free Frames Received */
172
+REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */
173
+REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */
174
+REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */
175
+REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */
176
+REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */
177
+REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */
178
+REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */
179
+REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */
180
+REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */
181
+REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */
182
+REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */
183
+REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */
184
+REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */
185
+REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */
186
+REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */
187
+REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */
188
+REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */
189
+REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */
190
+REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */
191
+REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */
192
+REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */
193
+REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */
194
195
-#define GEM_1588S (0x000001D0 / 4) /* 1588 Timer Seconds */
196
-#define GEM_1588NS (0x000001D4 / 4) /* 1588 Timer Nanoseconds */
197
-#define GEM_1588ADJ (0x000001D8 / 4) /* 1588 Timer Adjust */
198
-#define GEM_1588INC (0x000001DC / 4) /* 1588 Timer Increment */
199
-#define GEM_PTPETXS (0x000001E0 / 4) /* PTP Event Frame Transmitted (s) */
200
-#define GEM_PTPETXNS (0x000001E4 / 4) /*
201
- * PTP Event Frame Transmitted (ns)
202
- */
203
-#define GEM_PTPERXS (0x000001E8 / 4) /* PTP Event Frame Received (s) */
204
-#define GEM_PTPERXNS (0x000001EC / 4) /* PTP Event Frame Received (ns) */
205
-#define GEM_PTPPTXS (0x000001E0 / 4) /* PTP Peer Frame Transmitted (s) */
206
-#define GEM_PTPPTXNS (0x000001E4 / 4) /* PTP Peer Frame Transmitted (ns) */
207
-#define GEM_PTPPRXS (0x000001E8 / 4) /* PTP Peer Frame Received (s) */
208
-#define GEM_PTPPRXNS (0x000001EC / 4) /* PTP Peer Frame Received (ns) */
209
+REG32(1588S, 0x1d0) /* 1588 Timer Seconds */
210
+REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */
211
+REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */
212
+REG32(1588INC, 0x1dc) /* 1588 Timer Increment */
213
+REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */
214
+REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */
215
+REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */
216
+REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */
217
+REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */
218
+REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */
219
+REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */
220
+REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */
221
222
/* Design Configuration Registers */
223
-#define GEM_DESCONF (0x00000280 / 4)
224
-#define GEM_DESCONF2 (0x00000284 / 4)
225
-#define GEM_DESCONF3 (0x00000288 / 4)
226
-#define GEM_DESCONF4 (0x0000028C / 4)
227
-#define GEM_DESCONF5 (0x00000290 / 4)
228
-#define GEM_DESCONF6 (0x00000294 / 4)
229
+REG32(DESCONF, 0x280)
230
+REG32(DESCONF2, 0x284)
231
+REG32(DESCONF3, 0x288)
232
+REG32(DESCONF4, 0x28c)
233
+REG32(DESCONF5, 0x290)
234
+REG32(DESCONF6, 0x294)
235
#define GEM_DESCONF6_64B_MASK (1U << 23)
236
-#define GEM_DESCONF7 (0x00000298 / 4)
237
+REG32(DESCONF7, 0x298)
238
239
-#define GEM_INT_Q1_STATUS (0x00000400 / 4)
240
-#define GEM_INT_Q1_MASK (0x00000640 / 4)
241
+REG32(INT_Q1_STATUS, 0x400)
242
+REG32(INT_Q1_MASK, 0x640)
243
244
-#define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4)
245
-#define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6)
246
+REG32(TRANSMIT_Q1_PTR, 0x440)
247
+REG32(TRANSMIT_Q7_PTR, 0x458)
248
249
-#define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
250
-#define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
251
+REG32(RECEIVE_Q1_PTR, 0x480)
252
+REG32(RECEIVE_Q7_PTR, 0x498)
253
254
-#define GEM_TBQPH (0x000004C8 / 4)
255
-#define GEM_RBQPH (0x000004D4 / 4)
256
+REG32(TBQPH, 0x4c8)
257
+REG32(RBQPH, 0x4d4)
258
259
-#define GEM_INT_Q1_ENABLE (0x00000600 / 4)
260
-#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
261
+REG32(INT_Q1_ENABLE, 0x600)
262
+REG32(INT_Q7_ENABLE, 0x618)
263
264
-#define GEM_INT_Q1_DISABLE (0x00000620 / 4)
265
-#define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6)
266
+REG32(INT_Q1_DISABLE, 0x620)
267
+REG32(INT_Q7_DISABLE, 0x638)
268
269
-#define GEM_INT_Q1_MASK (0x00000640 / 4)
270
-#define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6)
271
-
272
-#define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4)
273
+REG32(SCREENING_TYPE1_REG0, 0x500)
274
275
#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
276
#define GEM_ST1R_DSTC_ENABLE (1 << 28)
277
@@ -XXX,XX +XXX,XX @@
278
#define GEM_ST1R_QUEUE_SHIFT (0)
279
#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
280
281
-#define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4)
282
+REG32(SCREENING_TYPE2_REG0, 0x540)
283
284
#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
285
#define GEM_ST2R_COMPARE_A_SHIFT (13)
286
@@ -XXX,XX +XXX,XX @@
287
#define GEM_ST2R_QUEUE_SHIFT (0)
288
#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
289
290
-#define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4)
291
-#define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4)
292
+REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0)
293
+REG32(TYPE2_COMPARE_0_WORD_0, 0x700)
294
295
#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
296
#define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
297
@@ -XXX,XX +XXX,XX @@ static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
298
{
299
uint64_t ret = desc[0];
300
301
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
302
+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
303
ret |= (uint64_t)desc[2] << 32;
304
}
305
return ret;
306
@@ -XXX,XX +XXX,XX @@ static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
307
{
308
uint64_t ret = desc[0] & ~0x3UL;
309
310
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
311
+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
312
ret |= (uint64_t)desc[2] << 32;
313
}
314
return ret;
315
@@ -XXX,XX +XXX,XX @@ static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx)
316
{
317
int ret = 2;
318
319
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
320
+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
321
ret += 2;
322
}
323
- if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
324
+ if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
325
: GEM_DMACFG_TX_BD_EXT)) {
326
ret += 2;
327
}
328
@@ -XXX,XX +XXX,XX @@ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
329
static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx)
330
{
331
uint32_t size;
332
- if (s->regs[GEM_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
333
- size = s->regs[GEM_JUMBO_MAX_LEN];
334
+ if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
335
+ size = s->regs[R_JUMBO_MAX_LEN];
336
if (size > s->jumbo_max_len) {
337
size = s->jumbo_max_len;
338
qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be"
339
@@ -XXX,XX +XXX,XX @@ static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx)
340
} else if (tx) {
341
size = 1518;
342
} else {
343
- size = s->regs[GEM_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
344
+ size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
345
}
346
return size;
347
}
348
@@ -XXX,XX +XXX,XX @@ static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx)
349
static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag)
350
{
351
if (q == 0) {
352
- s->regs[GEM_ISR] |= flag & ~(s->regs[GEM_IMR]);
353
+ s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]);
354
} else {
355
- s->regs[GEM_INT_Q1_STATUS + q - 1] |= flag &
356
- ~(s->regs[GEM_INT_Q1_MASK + q - 1]);
357
+ s->regs[R_INT_Q1_STATUS + q - 1] |= flag &
358
+ ~(s->regs[R_INT_Q1_MASK + q - 1]);
359
}
360
}
361
362
@@ -XXX,XX +XXX,XX @@ static void gem_init_register_masks(CadenceGEMState *s)
363
unsigned int i;
364
/* Mask of register bits which are read only */
365
memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
366
- s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
367
- s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
368
- s->regs_ro[GEM_DMACFG] = 0x8E00F000;
369
- s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
370
- s->regs_ro[GEM_RXQBASE] = 0x00000003;
371
- s->regs_ro[GEM_TXQBASE] = 0x00000003;
372
- s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
373
- s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
374
- s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
375
- s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
376
+ s->regs_ro[R_NWCTRL] = 0xFFF80000;
377
+ s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF;
378
+ s->regs_ro[R_DMACFG] = 0x8E00F000;
379
+ s->regs_ro[R_TXSTATUS] = 0xFFFFFE08;
380
+ s->regs_ro[R_RXQBASE] = 0x00000003;
381
+ s->regs_ro[R_TXQBASE] = 0x00000003;
382
+ s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0;
383
+ s->regs_ro[R_ISR] = 0xFFFFFFFF;
384
+ s->regs_ro[R_IMR] = 0xFFFFFFFF;
385
+ s->regs_ro[R_MODID] = 0xFFFFFFFF;
386
for (i = 0; i < s->num_priority_queues; i++) {
387
- s->regs_ro[GEM_INT_Q1_STATUS + i] = 0xFFFFFFFF;
388
- s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xFFFFF319;
389
- s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xFFFFF319;
390
- s->regs_ro[GEM_INT_Q1_MASK + i] = 0xFFFFFFFF;
391
+ s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF;
392
+ s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319;
393
+ s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319;
394
+ s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF;
395
}
396
397
/* Mask of register bits which are clear on read */
398
memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
399
- s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
400
+ s->regs_rtc[R_ISR] = 0xFFFFFFFF;
401
for (i = 0; i < s->num_priority_queues; i++) {
402
- s->regs_rtc[GEM_INT_Q1_STATUS + i] = 0x00000CE6;
403
+ s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6;
404
}
405
406
/* Mask of register bits which are write 1 to clear */
407
memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
408
- s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
409
- s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
410
+ s->regs_w1c[R_TXSTATUS] = 0x000001F7;
411
+ s->regs_w1c[R_RXSTATUS] = 0x0000000F;
412
413
/* Mask of register bits which are write only */
414
memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
415
- s->regs_wo[GEM_NWCTRL] = 0x00073E60;
416
- s->regs_wo[GEM_IER] = 0x07FFFFFF;
417
- s->regs_wo[GEM_IDR] = 0x07FFFFFF;
418
+ s->regs_wo[R_NWCTRL] = 0x00073E60;
419
+ s->regs_wo[R_IER] = 0x07FFFFFF;
420
+ s->regs_wo[R_IDR] = 0x07FFFFFF;
421
for (i = 0; i < s->num_priority_queues; i++) {
422
- s->regs_wo[GEM_INT_Q1_ENABLE + i] = 0x00000CE6;
423
- s->regs_wo[GEM_INT_Q1_DISABLE + i] = 0x00000CE6;
424
+ s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6;
425
+ s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6;
426
}
427
}
428
429
@@ -XXX,XX +XXX,XX @@ static bool gem_can_receive(NetClientState *nc)
430
s = qemu_get_nic_opaque(nc);
431
432
/* Do nothing if receive is not enabled. */
433
- if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
434
+ if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) {
435
if (s->can_rx_state != 1) {
436
s->can_rx_state = 1;
437
DB_PRINT("can't receive - no enable\n");
438
@@ -XXX,XX +XXX,XX @@ static void gem_update_int_status(CadenceGEMState *s)
439
{
440
int i;
441
442
- qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]);
443
+ qemu_set_irq(s->irq[0], !!s->regs[R_ISR]);
444
445
for (i = 1; i < s->num_priority_queues; ++i) {
446
- qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]);
447
+ qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]);
448
}
449
}
450
451
@@ -XXX,XX +XXX,XX @@ static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
452
uint64_t octets;
453
454
/* Total octets (bytes) received */
455
- octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
456
- s->regs[GEM_OCTRXHI];
457
+ octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) |
458
+ s->regs[R_OCTRXHI];
459
octets += bytes;
460
- s->regs[GEM_OCTRXLO] = octets >> 32;
461
- s->regs[GEM_OCTRXHI] = octets;
462
+ s->regs[R_OCTRXLO] = octets >> 32;
463
+ s->regs[R_OCTRXHI] = octets;
464
465
/* Error-free Frames received */
466
- s->regs[GEM_RXCNT]++;
467
+ s->regs[R_RXCNT]++;
468
469
/* Error-free Broadcast Frames counter */
470
if (!memcmp(packet, broadcast_addr, 6)) {
471
- s->regs[GEM_RXBROADCNT]++;
472
+ s->regs[R_RXBROADCNT]++;
473
}
474
475
/* Error-free Multicast Frames counter */
476
if (packet[0] == 0x01) {
477
- s->regs[GEM_RXMULTICNT]++;
478
+ s->regs[R_RXMULTICNT]++;
479
}
480
481
if (bytes <= 64) {
482
- s->regs[GEM_RX64CNT]++;
483
+ s->regs[R_RX64CNT]++;
484
} else if (bytes <= 127) {
485
- s->regs[GEM_RX65CNT]++;
486
+ s->regs[R_RX65CNT]++;
487
} else if (bytes <= 255) {
488
- s->regs[GEM_RX128CNT]++;
489
+ s->regs[R_RX128CNT]++;
490
} else if (bytes <= 511) {
491
- s->regs[GEM_RX256CNT]++;
492
+ s->regs[R_RX256CNT]++;
493
} else if (bytes <= 1023) {
494
- s->regs[GEM_RX512CNT]++;
495
+ s->regs[R_RX512CNT]++;
496
} else if (bytes <= 1518) {
497
- s->regs[GEM_RX1024CNT]++;
498
+ s->regs[R_RX1024CNT]++;
499
} else {
500
- s->regs[GEM_RX1519CNT]++;
501
+ s->regs[R_RX1519CNT]++;
502
}
503
}
504
505
@@ -XXX,XX +XXX,XX @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
506
int i, is_mc;
507
508
/* Promiscuous mode? */
509
- if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
510
+ if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) {
511
return GEM_RX_PROMISCUOUS_ACCEPT;
512
}
513
514
if (!memcmp(packet, broadcast_addr, 6)) {
515
/* Reject broadcast packets? */
516
- if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
517
+ if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) {
518
return GEM_RX_REJECT;
519
}
520
return GEM_RX_BROADCAST_ACCEPT;
521
@@ -XXX,XX +XXX,XX @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
522
523
/* Accept packets -w- hash match? */
524
is_mc = is_multicast_ether_addr(packet);
525
- if ((is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
526
- (!is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
527
+ if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
528
+ (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
529
uint64_t buckets;
530
unsigned hash_index;
531
532
hash_index = calc_mac_hash(packet);
533
- buckets = ((uint64_t)s->regs[GEM_HASHHI] << 32) | s->regs[GEM_HASHLO];
534
+ buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO];
535
if ((buckets >> hash_index) & 1) {
536
return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT
537
: GEM_RX_UNICAST_HASH_ACCEPT;
538
@@ -XXX,XX +XXX,XX @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
539
}
540
541
/* Check all 4 specific addresses */
542
- gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
543
+ gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]);
544
for (i = 3; i >= 0; i--) {
545
if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
546
return GEM_RX_SAR_ACCEPT + i;
547
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
548
int i, j;
549
550
for (i = 0; i < s->num_type1_screeners; i++) {
551
- reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
552
+ reg = s->regs[R_SCREENING_TYPE1_REG0 + i];
553
matched = false;
554
mismatched = false;
555
556
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
557
}
558
559
for (i = 0; i < s->num_type2_screeners; i++) {
560
- reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
561
+ reg = s->regs[R_SCREENING_TYPE2_REG0 + i];
562
matched = false;
563
mismatched = false;
564
565
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
566
qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
567
"register index: %d\n", et_idx);
568
}
569
- if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
570
+ if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 +
571
et_idx]) {
572
matched = true;
573
} else {
574
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
575
"register index: %d\n", cr_idx);
576
}
577
578
- cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
579
- cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
580
+ cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
581
+ cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
582
offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
583
GEM_T2CW1_OFFSET_VALUE_WIDTH);
584
585
@@ -XXX,XX +XXX,XX @@ static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q)
586
587
switch (q) {
588
case 0:
589
- base_addr = s->regs[tx ? GEM_TXQBASE : GEM_RXQBASE];
590
+ base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE];
591
break;
592
case 1 ... (MAX_PRIORITY_QUEUES - 1):
593
- base_addr = s->regs[(tx ? GEM_TRANSMIT_Q1_PTR :
594
- GEM_RECEIVE_Q1_PTR) + q - 1];
595
+ base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR :
596
+ R_RECEIVE_Q1_PTR) + q - 1];
597
break;
598
default:
599
g_assert_not_reached();
600
@@ -XXX,XX +XXX,XX @@ static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
601
{
602
hwaddr desc_addr = 0;
603
604
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
605
- desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH];
606
+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
607
+ desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH];
608
}
609
desc_addr <<= 32;
610
desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q];
611
@@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
612
/* Descriptor owned by software ? */
613
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
614
DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
615
- s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
616
+ s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
617
gem_set_isr(s, q, GEM_INT_RXUSED);
618
/* Handle interrupt consequences */
619
gem_update_int_status(s);
620
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
621
}
622
623
/* Discard packets with receive length error enabled ? */
624
- if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
625
+ if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) {
626
unsigned type_len;
627
628
/* Fish the ethertype / length field out of the RX packet */
629
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
630
/*
631
* Determine configured receive buffer offset (probably 0)
632
*/
633
- rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
634
+ rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
635
GEM_NWCFG_BUFF_OFST_S;
636
637
/* The configure size of each receive buffer. Determines how many
638
* buffers needed to hold this packet.
639
*/
640
- rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
641
+ rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
642
GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
643
bytes_to_copy = size;
644
645
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
646
}
647
648
/* Strip of FCS field ? (usually yes) */
649
- if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
650
+ if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) {
651
rxbuf_ptr = (void *)buf;
652
} else {
653
unsigned crc_val;
654
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
655
/* Count it */
656
gem_receive_updatestats(s, buf, size);
657
658
- s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
659
+ s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
660
gem_set_isr(s, q, GEM_INT_RXCMPL);
661
662
/* Handle interrupt consequences */
663
@@ -XXX,XX +XXX,XX @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
664
uint64_t octets;
665
666
/* Total octets (bytes) transmitted */
667
- octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
668
- s->regs[GEM_OCTTXHI];
669
+ octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) |
670
+ s->regs[R_OCTTXHI];
671
octets += bytes;
672
- s->regs[GEM_OCTTXLO] = octets >> 32;
673
- s->regs[GEM_OCTTXHI] = octets;
674
+ s->regs[R_OCTTXLO] = octets >> 32;
675
+ s->regs[R_OCTTXHI] = octets;
676
677
/* Error-free Frames transmitted */
678
- s->regs[GEM_TXCNT]++;
679
+ s->regs[R_TXCNT]++;
680
681
/* Error-free Broadcast Frames counter */
682
if (!memcmp(packet, broadcast_addr, 6)) {
683
- s->regs[GEM_TXBCNT]++;
684
+ s->regs[R_TXBCNT]++;
685
}
686
687
/* Error-free Multicast Frames counter */
688
if (packet[0] == 0x01) {
689
- s->regs[GEM_TXMCNT]++;
690
+ s->regs[R_TXMCNT]++;
691
}
692
693
if (bytes <= 64) {
694
- s->regs[GEM_TX64CNT]++;
695
+ s->regs[R_TX64CNT]++;
696
} else if (bytes <= 127) {
697
- s->regs[GEM_TX65CNT]++;
698
+ s->regs[R_TX65CNT]++;
699
} else if (bytes <= 255) {
700
- s->regs[GEM_TX128CNT]++;
701
+ s->regs[R_TX128CNT]++;
702
} else if (bytes <= 511) {
703
- s->regs[GEM_TX256CNT]++;
704
+ s->regs[R_TX256CNT]++;
705
} else if (bytes <= 1023) {
706
- s->regs[GEM_TX512CNT]++;
707
+ s->regs[R_TX512CNT]++;
708
} else if (bytes <= 1518) {
709
- s->regs[GEM_TX1024CNT]++;
710
+ s->regs[R_TX1024CNT]++;
711
} else {
712
- s->regs[GEM_TX1519CNT]++;
713
+ s->regs[R_TX1519CNT]++;
714
}
715
}
716
717
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
718
int q = 0;
719
720
/* Do nothing if transmit is not enabled. */
721
- if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
722
+ if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
723
return;
724
}
725
726
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
727
while (tx_desc_get_used(desc) == 0) {
728
729
/* Do nothing if transmit is not enabled. */
730
- if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
731
+ if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
732
return;
733
}
734
print_gem_tx_desc(desc, q);
735
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
736
}
737
DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
738
739
- s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
740
+ s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
741
gem_set_isr(s, q, GEM_INT_TXCMPL);
742
743
/* Handle interrupt consequences */
744
gem_update_int_status(s);
745
746
/* Is checksum offload enabled? */
747
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
748
+ if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
749
net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL);
750
}
751
752
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
753
gem_transmit_updatestats(s, s->tx_packet, total_bytes);
754
755
/* Send the packet somewhere */
756
- if (s->phy_loop || (s->regs[GEM_NWCTRL] &
757
+ if (s->phy_loop || (s->regs[R_NWCTRL] &
758
GEM_NWCTRL_LOCALLOOP)) {
759
qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet,
760
total_bytes);
761
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
762
763
/* read next descriptor */
764
if (tx_desc_get_wrap(desc)) {
765
-
766
- if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
767
- packet_desc_addr = s->regs[GEM_TBQPH];
768
+ if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
769
+ packet_desc_addr = s->regs[R_TBQPH];
770
packet_desc_addr <<= 32;
771
} else {
772
packet_desc_addr = 0;
773
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
774
}
775
776
if (tx_desc_get_used(desc)) {
777
- s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
778
+ s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED;
779
/* IRQ TXUSED is defined only for queue 0 */
780
if (q == 0) {
781
gem_set_isr(s, 0, GEM_INT_TXUSED);
782
@@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d)
783
784
/* Set post reset register values */
785
memset(&s->regs[0], 0, sizeof(s->regs));
786
- s->regs[GEM_NWCFG] = 0x00080000;
787
- s->regs[GEM_NWSTATUS] = 0x00000006;
788
- s->regs[GEM_DMACFG] = 0x00020784;
789
- s->regs[GEM_IMR] = 0x07ffffff;
790
- s->regs[GEM_TXPAUSE] = 0x0000ffff;
791
- s->regs[GEM_TXPARTIALSF] = 0x000003ff;
792
- s->regs[GEM_RXPARTIALSF] = 0x000003ff;
793
- s->regs[GEM_MODID] = s->revision;
794
- s->regs[GEM_DESCONF] = 0x02D00111;
795
- s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
796
- s->regs[GEM_DESCONF5] = 0x002f2045;
797
- s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
798
- s->regs[GEM_INT_Q1_MASK] = 0x00000CE6;
799
- s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len;
800
+ s->regs[R_NWCFG] = 0x00080000;
801
+ s->regs[R_NWSTATUS] = 0x00000006;
802
+ s->regs[R_DMACFG] = 0x00020784;
803
+ s->regs[R_IMR] = 0x07ffffff;
804
+ s->regs[R_TXPAUSE] = 0x0000ffff;
805
+ s->regs[R_TXPARTIALSF] = 0x000003ff;
806
+ s->regs[R_RXPARTIALSF] = 0x000003ff;
807
+ s->regs[R_MODID] = s->revision;
808
+ s->regs[R_DESCONF] = 0x02D00111;
809
+ s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
810
+ s->regs[R_DESCONF5] = 0x002f2045;
811
+ s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK;
812
+ s->regs[R_INT_Q1_MASK] = 0x00000CE6;
813
+ s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len;
814
815
if (s->num_priority_queues > 1) {
816
queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
817
- s->regs[GEM_DESCONF6] |= queues_mask;
818
+ s->regs[R_DESCONF6] |= queues_mask;
819
}
820
821
/* Set MAC address */
822
a = &s->conf.macaddr.a[0];
823
- s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
824
- s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
825
+ s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
826
+ s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8);
827
828
for (i = 0; i < 4; i++) {
829
s->sar_active[i] = false;
830
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
831
DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
832
833
switch (offset) {
834
- case GEM_ISR:
835
+ case R_ISR:
836
DB_PRINT("lowering irqs on ISR read\n");
837
/* The interrupts get updated at the end of the function. */
838
break;
839
- case GEM_PHYMNTNC:
840
+ case R_PHYMNTNC:
841
if (retval & GEM_PHYMNTNC_OP_R) {
842
uint32_t phy_addr, reg_num;
843
844
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
845
846
/* Handle register write side effects */
847
switch (offset) {
848
- case GEM_NWCTRL:
849
+ case R_NWCTRL:
850
if (val & GEM_NWCTRL_RXENA) {
851
for (i = 0; i < s->num_priority_queues; ++i) {
852
gem_get_rx_desc(s, i);
853
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
854
}
855
break;
856
857
- case GEM_TXSTATUS:
858
+ case R_TXSTATUS:
859
gem_update_int_status(s);
860
break;
861
- case GEM_RXQBASE:
862
+ case R_RXQBASE:
863
s->rx_desc_addr[0] = val;
864
break;
865
- case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR:
866
- s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
867
+ case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR:
868
+ s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val;
869
break;
870
- case GEM_TXQBASE:
871
+ case R_TXQBASE:
872
s->tx_desc_addr[0] = val;
873
break;
874
- case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR:
875
- s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
876
+ case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR:
877
+ s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val;
878
break;
879
- case GEM_RXSTATUS:
880
+ case R_RXSTATUS:
881
gem_update_int_status(s);
882
break;
883
- case GEM_IER:
884
- s->regs[GEM_IMR] &= ~val;
885
+ case R_IER:
886
+ s->regs[R_IMR] &= ~val;
887
gem_update_int_status(s);
888
break;
889
- case GEM_JUMBO_MAX_LEN:
890
- s->regs[GEM_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK;
891
+ case R_JUMBO_MAX_LEN:
892
+ s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK;
893
break;
894
- case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
895
- s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
896
+ case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE:
897
+ s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val;
898
gem_update_int_status(s);
899
break;
900
- case GEM_IDR:
901
- s->regs[GEM_IMR] |= val;
902
+ case R_IDR:
903
+ s->regs[R_IMR] |= val;
904
gem_update_int_status(s);
905
break;
906
- case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
907
- s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
908
+ case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE:
909
+ s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val;
910
gem_update_int_status(s);
911
break;
912
- case GEM_SPADDR1LO:
913
- case GEM_SPADDR2LO:
914
- case GEM_SPADDR3LO:
915
- case GEM_SPADDR4LO:
916
- s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
917
+ case R_SPADDR1LO:
918
+ case R_SPADDR2LO:
919
+ case R_SPADDR3LO:
920
+ case R_SPADDR4LO:
921
+ s->sar_active[(offset - R_SPADDR1LO) / 2] = false;
922
break;
923
- case GEM_SPADDR1HI:
924
- case GEM_SPADDR2HI:
925
- case GEM_SPADDR3HI:
926
- case GEM_SPADDR4HI:
927
- s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
928
+ case R_SPADDR1HI:
929
+ case R_SPADDR2HI:
930
+ case R_SPADDR3HI:
931
+ case R_SPADDR4HI:
932
+ s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
933
break;
934
- case GEM_PHYMNTNC:
935
+ case R_PHYMNTNC:
936
if (val & GEM_PHYMNTNC_OP_W) {
937
uint32_t phy_addr, reg_num;
938
939
--
940
2.34.1
diff view generated by jsdifflib
New patch
[PULL 32/41] hw/net/cadence_gem: use FIELD for screening registers
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
Describe screening registers fields using the FIELD macros.
4
5
Signed-off-by: Luc Michel <luc.michel@amd.com>
6
Reviewed-by: sai.pavan.boddu@amd.com
7
Message-id: 20231017194422.4124691-3-luc.michel@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/net/cadence_gem.c | 94 ++++++++++++++++++++++----------------------
11
1 file changed, 48 insertions(+), 46 deletions(-)
12
13
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/net/cadence_gem.c
16
+++ b/hw/net/cadence_gem.c
17
@@ -XXX,XX +XXX,XX @@ REG32(INT_Q1_DISABLE, 0x620)
18
REG32(INT_Q7_DISABLE, 0x638)
19
20
REG32(SCREENING_TYPE1_REG0, 0x500)
21
-
22
-#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
23
-#define GEM_ST1R_DSTC_ENABLE (1 << 28)
24
-#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
25
-#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
26
-#define GEM_ST1R_DSTC_MATCH_SHIFT (4)
27
-#define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
28
-#define GEM_ST1R_QUEUE_SHIFT (0)
29
-#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
30
+ FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4)
31
+ FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8)
32
+ FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16)
33
+ FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1)
34
+ FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1)
35
+ FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1)
36
37
REG32(SCREENING_TYPE2_REG0, 0x540)
38
-
39
-#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
40
-#define GEM_ST2R_COMPARE_A_SHIFT (13)
41
-#define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
42
-#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
43
-#define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9)
44
-#define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
45
- + 1)
46
-#define GEM_ST2R_QUEUE_SHIFT (0)
47
-#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
48
+ FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4)
49
+ FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3)
50
+ FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1)
51
+ FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3)
52
+ FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1)
53
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5)
54
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1)
55
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5)
56
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1)
57
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5)
58
+ FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1)
59
+ FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1)
60
61
REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0)
62
-REG32(TYPE2_COMPARE_0_WORD_0, 0x700)
63
64
-#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
65
-#define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
66
-#define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
67
-#define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
68
+REG32(TYPE2_COMPARE_0_WORD_0, 0x700)
69
+ FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16)
70
+ FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16)
71
+
72
+REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
73
+ FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7)
74
+ FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2)
75
+ FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1)
76
+ FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
77
78
/*****************************************/
79
#define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
80
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
81
mismatched = false;
82
83
/* Screening is based on UDP Port */
84
- if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
85
+ if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) {
86
uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
87
- if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
88
- GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
89
+ if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) {
90
matched = true;
91
} else {
92
mismatched = true;
93
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
94
}
95
96
/* Screening is based on DS/TC */
97
- if (reg & GEM_ST1R_DSTC_ENABLE) {
98
+ if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) {
99
uint8_t dscp = rxbuf_ptr[14 + 1];
100
- if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
101
- GEM_ST1R_DSTC_MATCH_WIDTH)) {
102
+ if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) {
103
matched = true;
104
} else {
105
mismatched = true;
106
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
107
}
108
109
if (matched && !mismatched) {
110
- return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
111
+ return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM);
112
}
113
}
114
115
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
116
matched = false;
117
mismatched = false;
118
119
- if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
120
+ if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) {
121
uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
122
- int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
123
- GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
124
+ int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0,
125
+ ETHERTYPE_REG_INDEX);
126
127
if (et_idx > s->num_type2_screeners) {
128
qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
129
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
130
131
/* Compare A, B, C */
132
for (j = 0; j < 3; j++) {
133
- uint32_t cr0, cr1, mask;
134
+ uint32_t cr0, cr1, mask, compare;
135
uint16_t rx_cmp;
136
int offset;
137
- int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
138
- GEM_ST2R_COMPARE_WIDTH);
139
+ int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6,
140
+ R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH);
141
142
- if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
143
+ if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6,
144
+ R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) {
145
continue;
146
}
147
+
148
if (cr_idx > s->num_type2_screeners) {
149
qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
150
"register index: %d\n", cr_idx);
151
}
152
153
cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
154
- cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
155
- offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
156
- GEM_T2CW1_OFFSET_VALUE_WIDTH);
157
+ cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2];
158
+ offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE);
159
160
- switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
161
- GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
162
+ switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) {
163
case 3: /* Skip UDP header */
164
qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
165
"unimplemented - assuming UDP\n");
166
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
167
}
168
169
rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
170
- mask = extract32(cr0, 0, 16);
171
+ mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE);
172
+ compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE);
173
174
- if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
175
+ if ((rx_cmp & mask) == (compare & mask)) {
176
matched = true;
177
} else {
178
mismatched = true;
179
@@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
180
}
181
182
if (matched && !mismatched) {
183
- return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
184
+ return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM);
185
}
186
}
187
188
--
189
2.34.1
diff view generated by jsdifflib
New patch
[PULL 33/41] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
Use the FIELD macro to describe the NWCTRL register fields.
4
5
Signed-off-by: Luc Michel <luc.michel@amd.com>
6
Reviewed-by: sai.pavan.boddu@amd.com
7
Message-id: 20231017194422.4124691-4-luc.michel@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/net/cadence_gem.c | 53 +++++++++++++++++++++++++++++++++-----------
11
1 file changed, 40 insertions(+), 13 deletions(-)
12
13
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/net/cadence_gem.c
16
+++ b/hw/net/cadence_gem.c
17
@@ -XXX,XX +XXX,XX @@
18
} while (0)
19
20
REG32(NWCTRL, 0x0) /* Network Control reg */
21
+ FIELD(NWCTRL, LOOPBACK , 0, 1)
22
+ FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1)
23
+ FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1)
24
+ FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1)
25
+ FIELD(NWCTRL, MAN_PORT_EN , 4, 1)
26
+ FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1)
27
+ FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1)
28
+ FIELD(NWCTRL, STATS_WRITE_EN, 7, 1)
29
+ FIELD(NWCTRL, BACK_PRESSURE, 8, 1)
30
+ FIELD(NWCTRL, TRANSMIT_START , 9, 1)
31
+ FIELD(NWCTRL, TRANSMIT_HALT, 10, 1)
32
+ FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1)
33
+ FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1)
34
+ FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1)
35
+ FIELD(NWCTRL, STATS_READ_SNAP, 14, 1)
36
+ FIELD(NWCTRL, STORE_RX_TS, 15, 1)
37
+ FIELD(NWCTRL, PFC_ENABLE, 16, 1)
38
+ FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1)
39
+ FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1)
40
+ FIELD(NWCTRL, TX_LPI_EN, 19, 1)
41
+ FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1)
42
+ FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1)
43
+ FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1)
44
+ FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1)
45
+ FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1)
46
+ FIELD(NWCTRL, PFC_CTRL , 25, 1)
47
+ FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1)
48
+ FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1)
49
+ FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1)
50
+ FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1)
51
+ FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1)
52
+
53
REG32(NWCFG, 0x4) /* Network Config reg */
54
REG32(NWSTATUS, 0x8) /* Network Status reg */
55
REG32(USERIO, 0xc) /* User IO reg */
56
@@ -XXX,XX +XXX,XX @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
57
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
58
59
/*****************************************/
60
-#define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
61
-#define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
62
-#define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
63
-#define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */
64
-
65
#define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
66
#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
67
#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
68
@@ -XXX,XX +XXX,XX @@ static bool gem_can_receive(NetClientState *nc)
69
s = qemu_get_nic_opaque(nc);
70
71
/* Do nothing if receive is not enabled. */
72
- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) {
73
+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) {
74
if (s->can_rx_state != 1) {
75
s->can_rx_state = 1;
76
DB_PRINT("can't receive - no enable\n");
77
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
78
int q = 0;
79
80
/* Do nothing if transmit is not enabled. */
81
- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
82
+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) {
83
return;
84
}
85
86
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
87
while (tx_desc_get_used(desc) == 0) {
88
89
/* Do nothing if transmit is not enabled. */
90
- if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) {
91
+ if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) {
92
return;
93
}
94
print_gem_tx_desc(desc, q);
95
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
96
gem_transmit_updatestats(s, s->tx_packet, total_bytes);
97
98
/* Send the packet somewhere */
99
- if (s->phy_loop || (s->regs[R_NWCTRL] &
100
- GEM_NWCTRL_LOCALLOOP)) {
101
+ if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL,
102
+ LOOPBACK_LOCAL)) {
103
qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet,
104
total_bytes);
105
} else {
106
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
107
/* Handle register write side effects */
108
switch (offset) {
109
case R_NWCTRL:
110
- if (val & GEM_NWCTRL_RXENA) {
111
+ if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) {
112
for (i = 0; i < s->num_priority_queues; ++i) {
113
gem_get_rx_desc(s, i);
114
}
115
}
116
- if (val & GEM_NWCTRL_TXSTART) {
117
+ if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) {
118
gem_transmit(s);
119
}
120
- if (!(val & GEM_NWCTRL_TXENA)) {
121
+ if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) {
122
/* Reset to start of Q when transmit disabled. */
123
for (i = 0; i < s->num_priority_queues; i++) {
124
s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i);
125
--
126
2.34.1
diff view generated by jsdifflib
New patch
[PULL 34/41] hw/net/cadence_gem: use FIELD to describe NWCFG register fields
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
Use de FIELD macro to describe the NWCFG register fields.
4
5
Signed-off-by: Luc Michel <luc.michel@amd.com>
6
Reviewed-by: sai.pavan.boddu@amd.com
7
Message-id: 20231017194422.4124691-5-luc.michel@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/net/cadence_gem.c | 60 ++++++++++++++++++++++++++++----------------
11
1 file changed, 39 insertions(+), 21 deletions(-)
12
13
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/net/cadence_gem.c
16
+++ b/hw/net/cadence_gem.c
17
@@ -XXX,XX +XXX,XX @@ REG32(NWCTRL, 0x0) /* Network Control reg */
18
FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1)
19
20
REG32(NWCFG, 0x4) /* Network Config reg */
21
+ FIELD(NWCFG, SPEED, 0, 1)
22
+ FIELD(NWCFG, FULL_DUPLEX, 1, 1)
23
+ FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1)
24
+ FIELD(NWCFG, JUMBO_FRAMES, 3, 1)
25
+ FIELD(NWCFG, PROMISC, 4, 1)
26
+ FIELD(NWCFG, NO_BROADCAST, 5, 1)
27
+ FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1)
28
+ FIELD(NWCFG, UNICAST_HASH_EN, 7, 1)
29
+ FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1)
30
+ FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1)
31
+ FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1)
32
+ FIELD(NWCFG, PCS_SELECT, 11, 1)
33
+ FIELD(NWCFG, RETRY_TEST, 12, 1)
34
+ FIELD(NWCFG, PAUSE_ENABLE, 13, 1)
35
+ FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2)
36
+ FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1)
37
+ FIELD(NWCFG, FCS_REMOVE, 17, 1)
38
+ FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3)
39
+ FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2)
40
+ FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1)
41
+ FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1)
42
+ FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1)
43
+ FIELD(NWCFG, IGNORE_RX_FCS, 26, 1)
44
+ FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1)
45
+ FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1)
46
+ FIELD(NWCFG, NSP_ACCEPT, 29, 1)
47
+ FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1)
48
+ FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1)
49
+
50
REG32(NWSTATUS, 0x8) /* Network Status reg */
51
REG32(USERIO, 0xc) /* User IO reg */
52
REG32(DMACFG, 0x10) /* DMA Control reg */
53
@@ -XXX,XX +XXX,XX @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
54
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
55
56
/*****************************************/
57
-#define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
58
-#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
59
-#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
60
-#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
61
-#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */
62
-#define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */
63
-#define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */
64
-#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
65
-#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
66
-#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */
67
-
68
#define GEM_DMACFG_ADDR_64B (1U << 30)
69
#define GEM_DMACFG_TX_BD_EXT (1U << 29)
70
#define GEM_DMACFG_RX_BD_EXT (1U << 28)
71
@@ -XXX,XX +XXX,XX @@ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
72
static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx)
73
{
74
uint32_t size;
75
- if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) {
76
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) {
77
size = s->regs[R_JUMBO_MAX_LEN];
78
if (size > s->jumbo_max_len) {
79
size = s->jumbo_max_len;
80
@@ -XXX,XX +XXX,XX @@ static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx)
81
} else if (tx) {
82
size = 1518;
83
} else {
84
- size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518;
85
+ size = FIELD_EX32(s->regs[R_NWCFG],
86
+ NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518;
87
}
88
return size;
89
}
90
@@ -XXX,XX +XXX,XX @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
91
int i, is_mc;
92
93
/* Promiscuous mode? */
94
- if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) {
95
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) {
96
return GEM_RX_PROMISCUOUS_ACCEPT;
97
}
98
99
if (!memcmp(packet, broadcast_addr, 6)) {
100
/* Reject broadcast packets? */
101
- if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) {
102
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) {
103
return GEM_RX_REJECT;
104
}
105
return GEM_RX_BROADCAST_ACCEPT;
106
@@ -XXX,XX +XXX,XX @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
107
108
/* Accept packets -w- hash match? */
109
is_mc = is_multicast_ether_addr(packet);
110
- if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
111
- (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
112
+ if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) ||
113
+ (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) {
114
uint64_t buckets;
115
unsigned hash_index;
116
117
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
118
}
119
120
/* Discard packets with receive length error enabled ? */
121
- if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) {
122
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) {
123
unsigned type_len;
124
125
/* Fish the ethertype / length field out of the RX packet */
126
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
127
/*
128
* Determine configured receive buffer offset (probably 0)
129
*/
130
- rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
131
- GEM_NWCFG_BUFF_OFST_S;
132
+ rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET);
133
134
/* The configure size of each receive buffer. Determines how many
135
* buffers needed to hold this packet.
136
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
137
}
138
139
/* Strip of FCS field ? (usually yes) */
140
- if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) {
141
+ if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
142
rxbuf_ptr = (void *)buf;
143
} else {
144
unsigned crc_val;
145
--
146
2.34.1
diff view generated by jsdifflib
New patch
[PULL 35/41] hw/net/cadence_gem: use FIELD to describe DMACFG register fields
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
Use de FIELD macro to describe the DMACFG register fields.
4
5
Signed-off-by: Luc Michel <luc.michel@amd.com>
6
Reviewed-by: sai.pavan.boddu@amd.com
7
Message-id: 20231017194422.4124691-6-luc.michel@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/net/cadence_gem.c | 48 ++++++++++++++++++++++++++++----------------
11
1 file changed, 31 insertions(+), 17 deletions(-)
12
13
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/net/cadence_gem.c
16
+++ b/hw/net/cadence_gem.c
17
@@ -XXX,XX +XXX,XX @@ REG32(NWCFG, 0x4) /* Network Config reg */
18
19
REG32(NWSTATUS, 0x8) /* Network Status reg */
20
REG32(USERIO, 0xc) /* User IO reg */
21
+
22
REG32(DMACFG, 0x10) /* DMA Control reg */
23
+ FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1)
24
+ FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1)
25
+ FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1)
26
+ FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1)
27
+ FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1)
28
+ FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1)
29
+ FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1)
30
+ FIELD(DMACFG, RX_BUF_SIZE, 16, 8)
31
+ FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1)
32
+ FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1)
33
+ FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1)
34
+ FIELD(DMACFG, TX_PBUF_SIZE, 10, 1)
35
+ FIELD(DMACFG, RX_PBUF_SIZE, 8, 2)
36
+ FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1)
37
+ FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1)
38
+ FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1)
39
+ FIELD(DMACFG, AMBA_BURST_LEN , 0, 5)
40
+#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
41
+
42
REG32(TXSTATUS, 0x14) /* TX Status reg */
43
REG32(RXQBASE, 0x18) /* RX Q Base address reg */
44
REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
45
@@ -XXX,XX +XXX,XX @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
46
FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1)
47
48
/*****************************************/
49
-#define GEM_DMACFG_ADDR_64B (1U << 30)
50
-#define GEM_DMACFG_TX_BD_EXT (1U << 29)
51
-#define GEM_DMACFG_RX_BD_EXT (1U << 28)
52
-#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
53
-#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
54
-#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
55
-#define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
56
57
#define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
58
#define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */
59
@@ -XXX,XX +XXX,XX @@ static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
60
{
61
uint64_t ret = desc[0];
62
63
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
64
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
65
ret |= (uint64_t)desc[2] << 32;
66
}
67
return ret;
68
@@ -XXX,XX +XXX,XX @@ static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
69
{
70
uint64_t ret = desc[0] & ~0x3UL;
71
72
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
73
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
74
ret |= (uint64_t)desc[2] << 32;
75
}
76
return ret;
77
@@ -XXX,XX +XXX,XX @@ static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx)
78
{
79
int ret = 2;
80
81
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
82
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
83
ret += 2;
84
}
85
- if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
86
- : GEM_DMACFG_TX_BD_EXT)) {
87
+ if (s->regs[R_DMACFG] & (rx_n_tx ? R_DMACFG_RX_BD_EXT_MODE_EN_MASK
88
+ : R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) {
89
ret += 2;
90
}
91
92
@@ -XXX,XX +XXX,XX @@ static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
93
{
94
hwaddr desc_addr = 0;
95
96
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
97
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
98
desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH];
99
}
100
desc_addr <<= 32;
101
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
102
/* The configure size of each receive buffer. Determines how many
103
* buffers needed to hold this packet.
104
*/
105
- rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
106
- GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
107
+ rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE);
108
+ rxbufsize *= GEM_DMACFG_RBUFSZ_MUL;
109
+
110
bytes_to_copy = size;
111
112
/* Hardware allows a zero value here but warns against it. To avoid QEMU
113
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
114
gem_update_int_status(s);
115
116
/* Is checksum offload enabled? */
117
- if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
118
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, TX_PBUF_CSUM_OFFLOAD)) {
119
net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL);
120
}
121
122
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
123
124
/* read next descriptor */
125
if (tx_desc_get_wrap(desc)) {
126
- if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) {
127
+ if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) {
128
packet_desc_addr = s->regs[R_TBQPH];
129
packet_desc_addr <<= 32;
130
} else {
131
--
132
2.34.1
diff view generated by jsdifflib
New patch
[PULL 36/41] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register
4
fields.
5
6
Signed-off-by: Luc Michel <luc.michel@amd.com>
7
Reviewed-by: sai.pavan.boddu@amd.com
8
Message-id: 20231017194422.4124691-7-luc.michel@amd.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/net/cadence_gem.c | 34 +++++++++++++++++++++++++---------
12
1 file changed, 25 insertions(+), 9 deletions(-)
13
14
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/cadence_gem.c
17
+++ b/hw/net/cadence_gem.c
18
@@ -XXX,XX +XXX,XX @@ REG32(DMACFG, 0x10) /* DMA Control reg */
19
#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
20
21
REG32(TXSTATUS, 0x14) /* TX Status reg */
22
+ FIELD(TXSTATUS, TX_USED_BIT_READ_MIDFRAME, 12, 1)
23
+ FIELD(TXSTATUS, TX_FRAME_TOO_LARGE, 11, 1)
24
+ FIELD(TXSTATUS, TX_DMA_LOCKUP, 10, 1)
25
+ FIELD(TXSTATUS, TX_MAC_LOCKUP, 9, 1)
26
+ FIELD(TXSTATUS, RESP_NOT_OK, 8, 1)
27
+ FIELD(TXSTATUS, LATE_COLLISION, 7, 1)
28
+ FIELD(TXSTATUS, TRANSMIT_UNDER_RUN, 6, 1)
29
+ FIELD(TXSTATUS, TRANSMIT_COMPLETE, 5, 1)
30
+ FIELD(TXSTATUS, AMBA_ERROR, 4, 1)
31
+ FIELD(TXSTATUS, TRANSMIT_GO, 3, 1)
32
+ FIELD(TXSTATUS, RETRY_LIMIT, 2, 1)
33
+ FIELD(TXSTATUS, COLLISION, 1, 1)
34
+ FIELD(TXSTATUS, USED_BIT_READ, 0, 1)
35
+
36
REG32(RXQBASE, 0x18) /* RX Q Base address reg */
37
REG32(TXQBASE, 0x1c) /* TX Q Base address reg */
38
REG32(RXSTATUS, 0x20) /* RX Status reg */
39
+ FIELD(RXSTATUS, RX_DMA_LOCKUP, 5, 1)
40
+ FIELD(RXSTATUS, RX_MAC_LOCKUP, 4, 1)
41
+ FIELD(RXSTATUS, RESP_NOT_OK, 3, 1)
42
+ FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1)
43
+ FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1)
44
+ FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
45
+
46
REG32(ISR, 0x24) /* Interrupt Status reg */
47
REG32(IER, 0x28) /* Interrupt Enable reg */
48
REG32(IDR, 0x2c) /* Interrupt Disable reg */
49
@@ -XXX,XX +XXX,XX @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
50
51
/*****************************************/
52
53
-#define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
54
-#define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */
55
-
56
-#define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
57
-#define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */
58
59
/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
60
#define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
61
@@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
62
/* Descriptor owned by software ? */
63
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
64
DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
65
- s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
66
+ s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
67
gem_set_isr(s, q, GEM_INT_RXUSED);
68
/* Handle interrupt consequences */
69
gem_update_int_status(s);
70
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
71
/* Count it */
72
gem_receive_updatestats(s, buf, size);
73
74
- s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
75
+ s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK;
76
gem_set_isr(s, q, GEM_INT_RXCMPL);
77
78
/* Handle interrupt consequences */
79
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
80
}
81
DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
82
83
- s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
84
+ s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK;
85
gem_set_isr(s, q, GEM_INT_TXCMPL);
86
87
/* Handle interrupt consequences */
88
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
89
}
90
91
if (tx_desc_get_used(desc)) {
92
- s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED;
93
+ s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK;
94
/* IRQ TXUSED is defined only for queue 0 */
95
if (q == 0) {
96
gem_set_isr(s, 0, GEM_INT_TXUSED);
97
--
98
2.34.1
diff view generated by jsdifflib
New patch
[PULL 37/41] hw/net/cadence_gem: use FIELD to describe IRQ register fields
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
Use de FIELD macro to describe the IRQ related register fields.
4
5
Signed-off-by: Luc Michel <luc.michel@amd.com>
6
Reviewed-by: sai.pavan.boddu@amd.com
7
Message-id: 20231017194422.4124691-8-luc.michel@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/net/cadence_gem.c | 51 +++++++++++++++++++++++++++++++++-----------
11
1 file changed, 39 insertions(+), 12 deletions(-)
12
13
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/net/cadence_gem.c
16
+++ b/hw/net/cadence_gem.c
17
@@ -XXX,XX +XXX,XX @@ REG32(RXSTATUS, 0x20) /* RX Status reg */
18
FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1)
19
20
REG32(ISR, 0x24) /* Interrupt Status reg */
21
+ FIELD(ISR, TX_LOCKUP, 31, 1)
22
+ FIELD(ISR, RX_LOCKUP, 30, 1)
23
+ FIELD(ISR, TSU_TIMER, 29, 1)
24
+ FIELD(ISR, WOL, 28, 1)
25
+ FIELD(ISR, RECV_LPI, 27, 1)
26
+ FIELD(ISR, TSU_SEC_INCR, 26, 1)
27
+ FIELD(ISR, PTP_PDELAY_RESP_XMIT, 25, 1)
28
+ FIELD(ISR, PTP_PDELAY_REQ_XMIT, 24, 1)
29
+ FIELD(ISR, PTP_PDELAY_RESP_RECV, 23, 1)
30
+ FIELD(ISR, PTP_PDELAY_REQ_RECV, 22, 1)
31
+ FIELD(ISR, PTP_SYNC_XMIT, 21, 1)
32
+ FIELD(ISR, PTP_DELAY_REQ_XMIT, 20, 1)
33
+ FIELD(ISR, PTP_SYNC_RECV, 19, 1)
34
+ FIELD(ISR, PTP_DELAY_REQ_RECV, 18, 1)
35
+ FIELD(ISR, PCS_LP_PAGE_RECV, 17, 1)
36
+ FIELD(ISR, PCS_AN_COMPLETE, 16, 1)
37
+ FIELD(ISR, EXT_IRQ, 15, 1)
38
+ FIELD(ISR, PAUSE_FRAME_XMIT, 14, 1)
39
+ FIELD(ISR, PAUSE_TIME_ELAPSED, 13, 1)
40
+ FIELD(ISR, PAUSE_FRAME_RECV, 12, 1)
41
+ FIELD(ISR, RESP_NOT_OK, 11, 1)
42
+ FIELD(ISR, RECV_OVERRUN, 10, 1)
43
+ FIELD(ISR, LINK_CHANGE, 9, 1)
44
+ FIELD(ISR, USXGMII_INT, 8, 1)
45
+ FIELD(ISR, XMIT_COMPLETE, 7, 1)
46
+ FIELD(ISR, AMBA_ERROR, 6, 1)
47
+ FIELD(ISR, RETRY_EXCEEDED, 5, 1)
48
+ FIELD(ISR, XMIT_UNDER_RUN, 4, 1)
49
+ FIELD(ISR, TX_USED, 3, 1)
50
+ FIELD(ISR, RX_USED, 2, 1)
51
+ FIELD(ISR, RECV_COMPLETE, 1, 1)
52
+ FIELD(ISR, MGNT_FRAME_SENT, 0, 1)
53
REG32(IER, 0x28) /* Interrupt Enable reg */
54
REG32(IDR, 0x2c) /* Interrupt Disable reg */
55
REG32(IMR, 0x30) /* Interrupt Mask reg */
56
+
57
REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
58
REG32(RXPAUSE, 0x38) /* RX Pause Time reg */
59
REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
60
@@ -XXX,XX +XXX,XX @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
61
/*****************************************/
62
63
64
-/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
65
-#define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
66
-#define GEM_INT_AMBA_ERR 0x00000040
67
-#define GEM_INT_TXUSED 0x00000008
68
-#define GEM_INT_RXUSED 0x00000004
69
-#define GEM_INT_RXCMPL 0x00000002
70
71
#define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
72
#define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
73
@@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
74
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
75
DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
76
s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK;
77
- gem_set_isr(s, q, GEM_INT_RXUSED);
78
+ gem_set_isr(s, q, R_ISR_RX_USED_MASK);
79
/* Handle interrupt consequences */
80
gem_update_int_status(s);
81
}
82
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
83
84
if (size > gem_get_max_buf_len(s, false)) {
85
qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n");
86
- gem_set_isr(s, q, GEM_INT_AMBA_ERR);
87
+ gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
88
return -1;
89
}
90
91
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
92
gem_receive_updatestats(s, buf, size);
93
94
s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK;
95
- gem_set_isr(s, q, GEM_INT_RXCMPL);
96
+ gem_set_isr(s, q, R_ISR_RECV_COMPLETE_MASK);
97
98
/* Handle interrupt consequences */
99
gem_update_int_status(s);
100
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
101
HWADDR_PRIx " too large: size 0x%x space 0x%zx\n",
102
packet_desc_addr, tx_desc_get_length(desc),
103
gem_get_max_buf_len(s, true) - (p - s->tx_packet));
104
- gem_set_isr(s, q, GEM_INT_AMBA_ERR);
105
+ gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK);
106
break;
107
}
108
109
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
110
DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
111
112
s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK;
113
- gem_set_isr(s, q, GEM_INT_TXCMPL);
114
+ gem_set_isr(s, q, R_ISR_XMIT_COMPLETE_MASK);
115
116
/* Handle interrupt consequences */
117
gem_update_int_status(s);
118
@@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s)
119
s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK;
120
/* IRQ TXUSED is defined only for queue 0 */
121
if (q == 0) {
122
- gem_set_isr(s, 0, GEM_INT_TXUSED);
123
+ gem_set_isr(s, 0, R_ISR_TX_USED_MASK);
124
}
125
gem_update_int_status(s);
126
}
127
--
128
2.34.1
diff view generated by jsdifflib
New patch
[PULL 38/41] hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
Use the FIELD macro to describe the DESCONF6 register fields.
4
5
Signed-off-by: Luc Michel <luc.michel@amd.com>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20231017194422.4124691-9-luc.michel@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/net/cadence_gem.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/net/cadence_gem.c
16
+++ b/hw/net/cadence_gem.c
17
@@ -XXX,XX +XXX,XX @@ REG32(DESCONF3, 0x288)
18
REG32(DESCONF4, 0x28c)
19
REG32(DESCONF5, 0x290)
20
REG32(DESCONF6, 0x294)
21
-#define GEM_DESCONF6_64B_MASK (1U << 23)
22
+ FIELD(DESCONF6, DMA_ADDR_64B, 23, 1)
23
REG32(DESCONF7, 0x298)
24
25
REG32(INT_Q1_STATUS, 0x400)
26
@@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d)
27
s->regs[R_DESCONF] = 0x02D00111;
28
s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
29
s->regs[R_DESCONF5] = 0x002f2045;
30
- s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK;
31
+ s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK;
32
s->regs[R_INT_Q1_MASK] = 0x00000CE6;
33
s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len;
34
35
--
36
2.34.1
37
38
diff view generated by jsdifflib
New patch
[PULL 39/41] hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
Use the FIELD macro to describe the PHYMNTNC register fields.
4
5
Signed-off-by: Luc Michel <luc.michel@amd.com>
6
Reviewed-by: sai.pavan.boddu@amd.com
7
Message-id: 20231017194422.4124691-10-luc.michel@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/net/cadence_gem.c | 27 ++++++++++++++-------------
11
1 file changed, 14 insertions(+), 13 deletions(-)
12
13
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/net/cadence_gem.c
16
+++ b/hw/net/cadence_gem.c
17
@@ -XXX,XX +XXX,XX @@ REG32(IDR, 0x2c) /* Interrupt Disable reg */
18
REG32(IMR, 0x30) /* Interrupt Mask reg */
19
20
REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */
21
+ FIELD(PHYMNTNC, DATA, 0, 16)
22
+ FIELD(PHYMNTNC, REG_ADDR, 18, 5)
23
+ FIELD(PHYMNTNC, PHY_ADDR, 23, 5)
24
+ FIELD(PHYMNTNC, OP, 28, 2)
25
+ FIELD(PHYMNTNC, ST, 30, 2)
26
+#define MDIO_OP_READ 0x3
27
+#define MDIO_OP_WRITE 0x2
28
+
29
REG32(RXPAUSE, 0x38) /* RX Pause Time reg */
30
REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */
31
REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */
32
@@ -XXX,XX +XXX,XX @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704)
33
34
35
36
-#define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
37
-#define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
38
-#define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
39
-#define GEM_PHYMNTNC_ADDR_SHFT 23
40
-#define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */
41
-#define GEM_PHYMNTNC_REG_SHIFT 18
42
-
43
/* Marvell PHY definitions */
44
#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */
45
46
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
47
/* The interrupts get updated at the end of the function. */
48
break;
49
case R_PHYMNTNC:
50
- if (retval & GEM_PHYMNTNC_OP_R) {
51
+ if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) {
52
uint32_t phy_addr, reg_num;
53
54
- phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
55
+ phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR);
56
if (phy_addr == s->phy_addr) {
57
- reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
58
+ reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR);
59
retval &= 0xFFFF0000;
60
retval |= gem_phy_read(s, reg_num);
61
} else {
62
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
63
s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
64
break;
65
case R_PHYMNTNC:
66
- if (val & GEM_PHYMNTNC_OP_W) {
67
+ if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) {
68
uint32_t phy_addr, reg_num;
69
70
- phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
71
+ phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
72
if (phy_addr == s->phy_addr) {
73
- reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
74
+ reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
75
gem_phy_write(s, reg_num, val);
76
}
77
}
78
--
79
2.34.1
diff view generated by jsdifflib
New patch
[PULL 40/41] hw/net/cadence_gem: perform PHY access on write only
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
The MDIO access is done only on a write to the PHYMNTNC register. A
4
subsequent read is used to retrieve the result but does not trigger an
5
MDIO access by itself.
6
7
Refactor the PHY access logic to perform all accesses (MDIO reads and
8
writes) at PHYMNTNC write time.
9
10
Signed-off-by: Luc Michel <luc.michel@amd.com>
11
Reviewed-by: sai.pavan.boddu@amd.com
12
Message-id: 20231017194422.4124691-11-luc.michel@amd.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/net/cadence_gem.c | 56 ++++++++++++++++++++++++++------------------
16
1 file changed, 33 insertions(+), 23 deletions(-)
17
18
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/net/cadence_gem.c
21
+++ b/hw/net/cadence_gem.c
22
@@ -XXX,XX +XXX,XX @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
23
s->phy_regs[reg_num] = val;
24
}
25
26
+static void gem_handle_phy_access(CadenceGEMState *s)
27
+{
28
+ uint32_t val = s->regs[R_PHYMNTNC];
29
+ uint32_t phy_addr, reg_num;
30
+
31
+ phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
32
+
33
+ if (phy_addr != s->phy_addr) {
34
+ /* no phy at this address */
35
+ if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_READ) {
36
+ s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, 0xffff);
37
+ }
38
+ return;
39
+ }
40
+
41
+ reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
42
+
43
+ switch (FIELD_EX32(val, PHYMNTNC, OP)) {
44
+ case MDIO_OP_READ:
45
+ s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA,
46
+ gem_phy_read(s, reg_num));
47
+ break;
48
+
49
+ case MDIO_OP_WRITE:
50
+ gem_phy_write(s, reg_num, val);
51
+ break;
52
+
53
+ default:
54
+ break; /* only clause 22 operations are supported */
55
+ }
56
+}
57
+
58
/*
59
* gem_read32:
60
* Read a GEM register.
61
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
62
DB_PRINT("lowering irqs on ISR read\n");
63
/* The interrupts get updated at the end of the function. */
64
break;
65
- case R_PHYMNTNC:
66
- if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) {
67
- uint32_t phy_addr, reg_num;
68
-
69
- phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR);
70
- if (phy_addr == s->phy_addr) {
71
- reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR);
72
- retval &= 0xFFFF0000;
73
- retval |= gem_phy_read(s, reg_num);
74
- } else {
75
- retval |= 0xFFFF; /* No device at this address */
76
- }
77
- }
78
- break;
79
}
80
81
/* Squash read to clear bits */
82
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
83
s->sar_active[(offset - R_SPADDR1HI) / 2] = true;
84
break;
85
case R_PHYMNTNC:
86
- if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) {
87
- uint32_t phy_addr, reg_num;
88
-
89
- phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
90
- if (phy_addr == s->phy_addr) {
91
- reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
92
- gem_phy_write(s, reg_num, val);
93
- }
94
- }
95
+ gem_handle_phy_access(s);
96
break;
97
}
98
99
--
100
2.34.1
diff view generated by jsdifflib
New patch
[PULL 41/41] hw/net/cadence_gem: enforce 32 bits variable size for CRC
1
From: Luc Michel <luc.michel@amd.com>
1
2
3
The CRC was stored in an unsigned variable in gem_receive. Change it for
4
a uint32_t to ensure we have the correct variable size here.
5
6
Signed-off-by: Luc Michel <luc.michel@amd.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: sai.pavan.boddu@amd.com
9
Message-id: 20231017194422.4124691-12-luc.michel@amd.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/net/cadence_gem.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/net/cadence_gem.c
18
+++ b/hw/net/cadence_gem.c
19
@@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
20
if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) {
21
rxbuf_ptr = (void *)buf;
22
} else {
23
- unsigned crc_val;
24
+ uint32_t crc_val;
25
26
if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
27
size = MAX_FRAME_SIZE - sizeof(crc_val);
28
--
29
2.34.1
30
31
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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