[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 00/24] target-arm queue
1
v2: dropped a couple of cadence_gem changes to ID regs that
1
Hi; here's a queue of arm patches (plus a few elf2dmp changes);
2
caused new clang sanitizer warnings.
2
mostly these are minor cleanups and bugfixes.
3
3
4
thanks
4
-- PMM
5
-- PMM
5
6
6
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
7
The following changes since commit deaca3fd30d3a8829160f8d3705d65ad83176800:
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8
8
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
9
Merge tag 'pull-vfio-20231018' of https://github.com/legoater/qemu into staging (2023-10-18 06:21:15 -0400)
9
10
10
are available in the Git repository at:
11
are available in the Git repository at:
11
12
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231019
13
14
14
for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
15
for you to fetch changes up to 2a052b4ee01b3c413cef2ef49cb780cde17d4ba1:
15
16
16
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
17
contrib/elf2dmp: Use g_malloc(), g_new() and g_free() (2023-10-19 14:32:13 +0100)
17
18
18
----------------------------------------------------------------
19
----------------------------------------------------------------
19
target-arm queue:
20
target-arm queue:
20
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
21
* hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
21
* target/arm: Fix aarch64_sve_change_el wrt EL0
22
* hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot'
22
* target/arm: Define fields of ISAR registers
23
* xlnx devices: remove deprecated device reset
23
* target/arm: Align cortex-r5 id_isar0
24
* xlnx-bbram: hw/nvram: Use dot in device type name
24
* target/arm: Fix cortex-a7 id_isar0
25
* elf2dmp: fix coverity issues
25
* net/cadence_gem: Fix various bugs, add support for new
26
* elf2dmp: convert to g_malloc, g_new and g_free
26
features that will be used by the Xilinx Versal board
27
* target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
27
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
28
* hw/arm: refactor virt PPI logic
28
* target/arm: Add the Cortex-A72
29
* arm/kvm: convert to kvm_set_one_reg, kvm_get_one_reg
29
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
30
* target/arm: Permit T32 LDM with single register
30
* target/arm: Mask PMOVSR writes based on supported counters
31
* smmuv3: Advertise SMMUv3.1-XNX
31
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
32
* target/arm: Implement FEAT_HPMN0
32
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
33
* Remove some unnecessary include lines
34
* target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
35
* hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
33
36
34
----------------------------------------------------------------
37
----------------------------------------------------------------
35
Aaron Lindsay (2):
38
Chris Rauer (1):
36
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
39
hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
37
target/arm: Mask PMOVSR writes based on supported counters
38
40
39
Edgar E. Iglesias (8):
41
Cornelia Huck (2):
40
net: cadence_gem: Disable TSU feature bit
42
arm/kvm: convert to kvm_set_one_reg
41
net: cadence_gem: Use uint32_t for 32bit descriptor words
43
arm/kvm: convert to kvm_get_one_reg
42
net: cadence_gem: Add macro with max number of descriptor words
43
net: cadence_gem: Add support for extended descriptors
44
net: cadence_gem: Add support for selecting the DMA MemoryRegion
45
net: cadence_gem: Implement support for 64bit descriptor addresses
46
target-arm: powerctl: Enable HVC when starting CPUs to EL2
47
target/arm: Add the Cortex-A72
48
44
49
Jerome Forissier (1):
45
Leif Lindholm (3):
50
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
46
{include/}hw/arm: refactor virt PPI logic
47
include/hw/arm: move BSA definitions to bsa.h
48
hw/arm/sbsa-ref: use bsa.h for PPI definitions
51
49
52
Peter Maydell (2):
50
Michal Orzel (1):
53
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
51
target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
54
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
55
52
56
Richard Henderson (4):
53
Peter Maydell (8):
57
target/arm: Fix aarch64_sve_change_el wrt EL0
54
target/arm: Permit T32 LDM with single register
58
target/arm: Define fields of ISAR registers
55
hw/arm/smmuv3: Update ID register bit field definitions
59
target/arm: Align cortex-r5 id_isar0
56
hw/arm/smmuv3: Sort ID register setting into field order
60
target/arm: Fix cortex-a7 id_isar0
57
hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature
58
target/arm: Implement FEAT_HPMN0
59
target/arm/kvm64.c: Remove unused include
60
target/arm/common-semi-target.h: Remove unnecessary boot.h include
61
target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
61
62
62
include/hw/net/cadence_gem.h | 7 +-
63
Philippe Mathieu-Daudé (1):
63
target/arm/cpu.h | 95 ++++++++++++++-
64
hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h'
64
hw/arm/virt.c | 4 +
65
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
66
target/arm/arm-powerctl.c | 10 ++
67
target/arm/cpu.c | 7 +-
68
target/arm/cpu64.c | 66 +++++++++-
69
target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
71
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
72
10 files changed, 402 insertions(+), 70 deletions(-)
73
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
74
65
66
Suraj Shirvankar (1):
67
contrib/elf2dmp: Use g_malloc(), g_new() and g_free()
68
69
Thomas Huth (1):
70
hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
71
72
Tong Ho (4):
73
xlnx-bbram: hw/nvram: Remove deprecated device reset
74
xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device reset
75
xlnx-versal-efuse: hw/nvram: Remove deprecated device reset
76
xlnx-bbram: hw/nvram: Use dot in device type name
77
78
Viktor Prutyanov (2):
79
elf2dmp: limit print length for sign_rsds
80
elf2dmp: check array bounds in pdb_get_file_size
81
82
MAINTAINERS | 2 +-
83
docs/system/arm/emulation.rst | 1 +
84
hw/arm/smmuv3-internal.h | 38 ++++++++
85
include/hw/arm/bsa.h | 35 +++++++
86
include/hw/arm/exynos4210.h | 2 +-
87
include/hw/{misc => arm}/raspberrypi-fw-defs.h | 0
88
include/hw/arm/virt.h | 12 +--
89
include/hw/nvram/xlnx-bbram.h | 2 +-
90
target/arm/common-semi-target.h | 4 +-
91
target/arm/cpu-qom.h | 2 -
92
target/arm/cpu.h | 22 +++++
93
contrib/elf2dmp/addrspace.c | 7 +-
94
contrib/elf2dmp/main.c | 11 +--
95
contrib/elf2dmp/pdb.c | 32 ++++---
96
contrib/elf2dmp/qemu_elf.c | 7 +-
97
hw/arm/boot.c | 95 +++++--------------
98
hw/arm/sbsa-ref.c | 21 ++---
99
hw/arm/smmuv3.c | 8 +-
100
hw/arm/virt-acpi-build.c | 12 +--
101
hw/arm/virt.c | 24 +++--
102
hw/misc/bcm2835_property.c | 2 +-
103
hw/nvram/xlnx-bbram.c | 8 +-
104
hw/nvram/xlnx-versal-efuse-ctrl.c | 8 +-
105
hw/nvram/xlnx-zynqmp-efuse.c | 8 +-
106
hw/timer/npcm7xx_timer.c | 3 +
107
target/arm/arm-powerctl.c | 53 +----------
108
target/arm/cpu.c | 95 +++++++++++++++++++
109
target/arm/helper.c | 19 +---
110
target/arm/kvm.c | 28 ++----
111
target/arm/kvm64.c | 124 +++++++------------------
112
target/arm/tcg/cpu32.c | 4 +
113
target/arm/tcg/cpu64.c | 1 +
114
target/arm/tcg/translate.c | 37 +++++---
115
33 files changed, 368 insertions(+), 359 deletions(-)
116
create mode 100644 include/hw/arm/bsa.h
117
rename include/hw/{misc => arm}/raspberrypi-fw-defs.h (100%)
118
diff view generated by jsdifflib
New patch
[PULL 01/24] hw/arm: Move raspberrypi-fw-defs.h to the include/hw/arm/ folder
1
From: Thomas Huth <thuth@redhat.com>
1
2
3
The file is obviously related to the raspberrypi machine, so
4
it should reside in hw/arm/ instead of hw/misc/. And while we're
5
at it, also adjust the wildcard in MAINTAINERS so that it covers
6
this file, too.
7
8
Signed-off-by: Thomas Huth <thuth@redhat.com>
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20231012073458.860187-1-thuth@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
MAINTAINERS | 2 +-
15
include/hw/{misc => arm}/raspberrypi-fw-defs.h | 0
16
hw/misc/bcm2835_property.c | 2 +-
17
3 files changed, 2 insertions(+), 2 deletions(-)
18
rename include/hw/{misc => arm}/raspberrypi-fw-defs.h (100%)
19
20
diff --git a/MAINTAINERS b/MAINTAINERS
21
index XXXXXXX..XXXXXXX 100644
22
--- a/MAINTAINERS
23
+++ b/MAINTAINERS
24
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
25
F: hw/arm/raspi.c
26
F: hw/arm/raspi_platform.h
27
F: hw/*/bcm283*
28
-F: include/hw/arm/raspi*
29
+F: include/hw/arm/rasp*
30
F: include/hw/*/bcm283*
31
F: docs/system/arm/raspi.rst
32
33
diff --git a/include/hw/misc/raspberrypi-fw-defs.h b/include/hw/arm/raspberrypi-fw-defs.h
34
similarity index 100%
35
rename from include/hw/misc/raspberrypi-fw-defs.h
36
rename to include/hw/arm/raspberrypi-fw-defs.h
37
diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/misc/bcm2835_property.c
40
+++ b/hw/misc/bcm2835_property.c
41
@@ -XXX,XX +XXX,XX @@
42
#include "migration/vmstate.h"
43
#include "hw/irq.h"
44
#include "hw/misc/bcm2835_mbox_defs.h"
45
-#include "hw/misc/raspberrypi-fw-defs.h"
46
+#include "hw/arm/raspberrypi-fw-defs.h"
47
#include "sysemu/dma.h"
48
#include "qemu/log.h"
49
#include "qemu/module.h"
50
--
51
2.34.1
52
53
diff view generated by jsdifflib
New patch
[PULL 02/24] hw/arm/exynos4210: Get arm_boot_info declaration from 'hw/arm/boot.h'
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
struct arm_boot_info is declared in "hw/arm/boot.h".
4
By including the correct header we don't need to declare
5
it again in "target/arm/cpu-qom.h".
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20231013130214.95742-1-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/exynos4210.h | 2 +-
13
target/arm/cpu-qom.h | 2 --
14
2 files changed, 1 insertion(+), 3 deletions(-)
15
16
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/exynos4210.h
19
+++ b/include/hw/arm/exynos4210.h
20
@@ -XXX,XX +XXX,XX @@
21
#include "hw/intc/exynos4210_gic.h"
22
#include "hw/intc/exynos4210_combiner.h"
23
#include "hw/core/split-irq.h"
24
-#include "target/arm/cpu-qom.h"
25
+#include "hw/arm/boot.h"
26
#include "qom/object.h"
27
28
#define EXYNOS4210_NCPUS 2
29
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/cpu-qom.h
32
+++ b/target/arm/cpu-qom.h
33
@@ -XXX,XX +XXX,XX @@
34
#include "hw/core/cpu.h"
35
#include "qom/object.h"
36
37
-struct arm_boot_info;
38
-
39
#define TYPE_ARM_CPU "arm-cpu"
40
41
OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU)
42
--
43
2.34.1
44
45
diff view generated by jsdifflib
New patch
[PULL 03/24] xlnx-bbram: hw/nvram: Remove deprecated device reset
1
From: Tong Ho <tong.ho@amd.com>
1
2
3
This change implements the ResettableClass interface for the device.
4
5
Signed-off-by: Tong Ho <tong.ho@amd.com>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20231003052345.199725-1-tong.ho@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/nvram/xlnx-bbram.c | 8 +++++---
11
1 file changed, 5 insertions(+), 3 deletions(-)
12
13
diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/nvram/xlnx-bbram.c
16
+++ b/hw/nvram/xlnx-bbram.c
17
@@ -XXX,XX +XXX,XX @@
18
* QEMU model of the Xilinx BBRAM Battery Backed RAM
19
*
20
* Copyright (c) 2014-2021 Xilinx Inc.
21
+ * Copyright (c) 2023 Advanced Micro Devices, Inc.
22
*
23
* Permission is hereby granted, free of charge, to any person obtaining a copy
24
* of this software and associated documentation files (the "Software"), to deal
25
@@ -XXX,XX +XXX,XX @@ static RegisterAccessInfo bbram_ctrl_regs_info[] = {
26
}
27
};
28
29
-static void bbram_ctrl_reset(DeviceState *dev)
30
+static void bbram_ctrl_reset_hold(Object *obj)
31
{
32
- XlnxBBRam *s = XLNX_BBRAM(dev);
33
+ XlnxBBRam *s = XLNX_BBRAM(obj);
34
unsigned int i;
35
36
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
37
@@ -XXX,XX +XXX,XX @@ static Property bbram_ctrl_props[] = {
38
static void bbram_ctrl_class_init(ObjectClass *klass, void *data)
39
{
40
DeviceClass *dc = DEVICE_CLASS(klass);
41
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
42
43
- dc->reset = bbram_ctrl_reset;
44
+ rc->phases.hold = bbram_ctrl_reset_hold;
45
dc->realize = bbram_ctrl_realize;
46
dc->vmsd = &vmstate_bbram_ctrl;
47
device_class_set_props(dc, bbram_ctrl_props);
48
--
49
2.34.1
50
51
diff view generated by jsdifflib
New patch
[PULL 04/24] xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device reset
1
From: Tong Ho <tong.ho@amd.com>
1
2
3
This change implements the ResettableClass interface for the device.
4
5
Signed-off-by: Tong Ho <tong.ho@amd.com>
6
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Message-id: 20231004055713.324009-1-tong.ho@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/nvram/xlnx-zynqmp-efuse.c | 8 +++++---
11
1 file changed, 5 insertions(+), 3 deletions(-)
12
13
diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/nvram/xlnx-zynqmp-efuse.c
16
+++ b/hw/nvram/xlnx-zynqmp-efuse.c
17
@@ -XXX,XX +XXX,XX @@
18
* QEMU model of the ZynqMP eFuse
19
*
20
* Copyright (c) 2015 Xilinx Inc.
21
+ * Copyright (c) 2023 Advanced Micro Devices, Inc.
22
*
23
* Written by Edgar E. Iglesias <edgari@xilinx.com>
24
*
25
@@ -XXX,XX +XXX,XX @@ static void zynqmp_efuse_register_reset(RegisterInfo *reg)
26
register_reset(reg);
27
}
28
29
-static void zynqmp_efuse_reset(DeviceState *dev)
30
+static void zynqmp_efuse_reset_hold(Object *obj)
31
{
32
- XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
33
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
34
unsigned int i;
35
36
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
37
@@ -XXX,XX +XXX,XX @@ static Property zynqmp_efuse_props[] = {
38
static void zynqmp_efuse_class_init(ObjectClass *klass, void *data)
39
{
40
DeviceClass *dc = DEVICE_CLASS(klass);
41
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
42
43
- dc->reset = zynqmp_efuse_reset;
44
+ rc->phases.hold = zynqmp_efuse_reset_hold;
45
dc->realize = zynqmp_efuse_realize;
46
dc->vmsd = &vmstate_efuse;
47
device_class_set_props(dc, zynqmp_efuse_props);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 05/24] xlnx-versal-efuse: hw/nvram: Remove deprecated device reset
1
From: Tong Ho <tong.ho@amd.com>
1
2
3
This change implements the ResettableClass interface for the device.
4
5
Signed-off-by: Tong Ho <tong.ho@amd.com>
6
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Message-id: 20231004055339.323833-1-tong.ho@amd.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/nvram/xlnx-versal-efuse-ctrl.c | 8 +++++---
11
1 file changed, 5 insertions(+), 3 deletions(-)
12
13
diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/nvram/xlnx-versal-efuse-ctrl.c
16
+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
17
@@ -XXX,XX +XXX,XX @@
18
* QEMU model of the Versal eFuse controller
19
*
20
* Copyright (c) 2020 Xilinx Inc.
21
+ * Copyright (c) 2023 Advanced Micro Devices, Inc.
22
*
23
* Permission is hereby granted, free of charge, to any person obtaining a copy
24
* of this software and associated documentation files (the "Software"), to deal
25
@@ -XXX,XX +XXX,XX @@ static void efuse_ctrl_register_reset(RegisterInfo *reg)
26
register_reset(reg);
27
}
28
29
-static void efuse_ctrl_reset(DeviceState *dev)
30
+static void efuse_ctrl_reset_hold(Object *obj)
31
{
32
- XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
33
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
34
unsigned int i;
35
36
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
37
@@ -XXX,XX +XXX,XX @@ static Property efuse_ctrl_props[] = {
38
static void efuse_ctrl_class_init(ObjectClass *klass, void *data)
39
{
40
DeviceClass *dc = DEVICE_CLASS(klass);
41
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
42
43
- dc->reset = efuse_ctrl_reset;
44
+ rc->phases.hold = efuse_ctrl_reset_hold;
45
dc->realize = efuse_ctrl_realize;
46
dc->vmsd = &vmstate_efuse_ctrl;
47
device_class_set_props(dc, efuse_ctrl_props);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 06/24] xlnx-bbram: hw/nvram: Use dot in device type name
1
From: Tong Ho <tong.ho@amd.com>
1
2
3
This replaces the comma (,) to dot (.) in the device type name
4
so the name can be used with the 'driver=' command line option.
5
6
Signed-off-by: Tong Ho <tong.ho@amd.com>
7
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
8
Message-id: 20231003052139.199665-1-tong.ho@amd.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/nvram/xlnx-bbram.h | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/nvram/xlnx-bbram.h
17
+++ b/include/hw/nvram/xlnx-bbram.h
18
@@ -XXX,XX +XXX,XX @@
19
20
#define RMAX_XLNX_BBRAM ((0x4c / 4) + 1)
21
22
-#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl"
23
+#define TYPE_XLNX_BBRAM "xlnx.bbram-ctrl"
24
OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM);
25
26
struct XlnxBBRam {
27
--
28
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/24] elf2dmp: limit print length for sign_rsds
1
From: Viktor Prutyanov <viktor@daynix.com>
1
2
3
String sign_rsds isn't terminated, so the print length must be limited.
4
5
Fixes: Coverity CID 1521598
6
Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
7
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
8
Message-id: 20230930235317.11469-2-viktor@daynix.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
contrib/elf2dmp/main.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/contrib/elf2dmp/main.c
17
+++ b/contrib/elf2dmp/main.c
18
@@ -XXX,XX +XXX,XX @@ static bool pe_check_pdb_name(uint64_t base, void *start_addr,
19
}
20
21
if (memcmp(&rsds->Signature, sign_rsds, sizeof(sign_rsds))) {
22
- eprintf("CodeView signature is \'%.4s\', \'%s\' expected\n",
23
+ eprintf("CodeView signature is \'%.4s\', \'%.4s\' expected\n",
24
rsds->Signature, sign_rsds);
25
return false;
26
}
27
--
28
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/24] elf2dmp: check array bounds in pdb_get_file_size
1
From: Viktor Prutyanov <viktor@daynix.com>
1
2
3
Index in file_size array must be checked against num_files, because the
4
entries we are looking for may be absent in the PDB.
5
6
Fixes: Coverity CID 1521597
7
Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
8
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20230930235317.11469-3-viktor@daynix.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
contrib/elf2dmp/pdb.c | 13 +++++++++----
14
1 file changed, 9 insertions(+), 4 deletions(-)
15
16
diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/contrib/elf2dmp/pdb.c
19
+++ b/contrib/elf2dmp/pdb.c
20
@@ -XXX,XX +XXX,XX @@
21
22
static uint32_t pdb_get_file_size(const struct pdb_reader *r, unsigned idx)
23
{
24
+ if (idx >= r->ds.toc->num_files) {
25
+ return 0;
26
+ }
27
+
28
return r->ds.toc->file_size[idx];
29
}
30
31
@@ -XXX,XX +XXX,XX @@ static void *pdb_ds_read_file(struct pdb_reader* r, uint32_t file_number)
32
33
static int pdb_init_segments(struct pdb_reader *r)
34
{
35
- char *segs;
36
unsigned stream_idx = r->segments;
37
38
- segs = pdb_ds_read_file(r, stream_idx);
39
- if (!segs) {
40
+ r->segs = pdb_ds_read_file(r, stream_idx);
41
+ if (!r->segs) {
42
return 1;
43
}
44
45
- r->segs = segs;
46
r->segs_size = pdb_get_file_size(r, stream_idx);
47
+ if (!r->segs_size) {
48
+ return 1;
49
+ }
50
51
return 0;
52
}
53
--
54
2.34.1
55
56
diff view generated by jsdifflib
New patch
[PULL 09/24] target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0
1
From: Michal Orzel <michal.orzel@amd.com>
1
2
3
On an attempt to access CNTPCT_EL0 from EL0 using a guest running on top
4
of Xen, a trap from EL2 was observed which is something not reproducible
5
on HW (also, Xen does not trap accesses to physical counter).
6
7
This is because gt_counter_access() checks for an incorrect bit (1
8
instead of 0) of CNTHCTL_EL2 if HCR_EL2.E2H is 0 and access is made to
9
physical counter. Refer ARM ARM DDI 0487J.a, D19.12.2:
10
When HCR_EL2.E2H is 0:
11
- EL1PCTEN, bit [0]: refers to physical counter
12
- EL1PCEN, bit [1]: refers to physical timer registers
13
14
Drop entire block "if (hcr & HCR_E2H) {...} else {...}" from EL0 case
15
and fall through to EL1 case, given that after fixing checking for the
16
correct bit, the handling is the same.
17
18
Fixes: 5bc8437136fb ("target/arm: Update timer access for VHE")
19
Signed-off-by: Michal Orzel <michal.orzel@amd.com>
20
Tested-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
21
Message-id: 20230928094404.20802-1-michal.orzel@amd.com
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
target/arm/helper.c | 17 +----------------
26
1 file changed, 1 insertion(+), 16 deletions(-)
27
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/helper.c
31
+++ b/target/arm/helper.c
32
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
33
if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
34
return CP_ACCESS_TRAP;
35
}
36
-
37
- /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
38
- if (hcr & HCR_E2H) {
39
- if (timeridx == GTIMER_PHYS &&
40
- !extract32(env->cp15.cnthctl_el2, 10, 1)) {
41
- return CP_ACCESS_TRAP_EL2;
42
- }
43
- } else {
44
- /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
45
- if (has_el2 && timeridx == GTIMER_PHYS &&
46
- !extract32(env->cp15.cnthctl_el2, 1, 1)) {
47
- return CP_ACCESS_TRAP_EL2;
48
- }
49
- }
50
- break;
51
-
52
+ /* fall through */
53
case 1:
54
/* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
55
if (has_el2 && timeridx == GTIMER_PHYS &&
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 10/24] {include/}hw/arm: refactor virt PPI logic
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
2
3
GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31.
4
As in, PPI0 is INTID16 .. PPI15 is INTID31.
5
Arm's Base System Architecture specification (BSA) lists the mandated and
6
recommended private interrupt IDs by INTID, not by PPI index. But current
7
definitions in virt define them by PPI index, complicating cross
8
referencing.
9
10
Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value,
11
converting a PPI index to an INTID.
12
13
Resolve this by redefining the BSA-allocated PPIs by their INTIDs,
14
and replacing the PPI(x) macro with an INTID_TO_PPI(x) one where required.
15
16
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
17
Message-id: 20230919090229.188092-2-quic_llindhol@quicinc.com
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
include/hw/arm/virt.h | 14 +++++++-------
22
hw/arm/virt-acpi-build.c | 12 ++++++------
23
hw/arm/virt.c | 24 ++++++++++++++----------
24
3 files changed, 27 insertions(+), 23 deletions(-)
25
26
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/virt.h
29
+++ b/include/hw/arm/virt.h
30
@@ -XXX,XX +XXX,XX @@
31
#define NUM_VIRTIO_TRANSPORTS 32
32
#define NUM_SMMU_IRQS 4
33
34
-#define ARCH_GIC_MAINT_IRQ 9
35
+#define ARCH_GIC_MAINT_IRQ 25
36
37
-#define ARCH_TIMER_VIRT_IRQ 11
38
-#define ARCH_TIMER_S_EL1_IRQ 13
39
-#define ARCH_TIMER_NS_EL1_IRQ 14
40
-#define ARCH_TIMER_NS_EL2_IRQ 10
41
+#define ARCH_TIMER_VIRT_IRQ 27
42
+#define ARCH_TIMER_S_EL1_IRQ 29
43
+#define ARCH_TIMER_NS_EL1_IRQ 30
44
+#define ARCH_TIMER_NS_EL2_IRQ 26
45
46
-#define VIRTUAL_PMU_IRQ 7
47
+#define VIRTUAL_PMU_IRQ 23
48
49
-#define PPI(irq) ((irq) + 16)
50
+#define INTID_TO_PPI(irq) ((irq) - 16)
51
52
/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
53
#define PVTIME_SIZE_PER_CPU 64
54
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/virt-acpi-build.c
57
+++ b/hw/arm/virt-acpi-build.c
58
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
59
* The interrupt values are the same with the device tree when adding 16
60
*/
61
/* Secure EL1 timer GSIV */
62
- build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4);
63
+ build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ, 4);
64
/* Secure EL1 timer Flags */
65
build_append_int_noprefix(table_data, irqflags, 4);
66
/* Non-Secure EL1 timer GSIV */
67
- build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4);
68
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ, 4);
69
/* Non-Secure EL1 timer Flags */
70
build_append_int_noprefix(table_data, irqflags |
71
1UL << 2, /* Always-on Capability */
72
4);
73
/* Virtual timer GSIV */
74
- build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4);
75
+ build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ, 4);
76
/* Virtual Timer Flags */
77
build_append_int_noprefix(table_data, irqflags, 4);
78
/* Non-Secure EL2 timer GSIV */
79
- build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4);
80
+ build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ, 4);
81
/* Non-Secure EL2 timer Flags */
82
build_append_int_noprefix(table_data, irqflags, 4);
83
/* CntReadBase Physical address */
84
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
85
for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
86
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
87
uint64_t physical_base_address = 0, gich = 0, gicv = 0;
88
- uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
89
+ uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
90
uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
91
- PPI(VIRTUAL_PMU_IRQ) : 0;
92
+ VIRTUAL_PMU_IRQ : 0;
93
94
if (vms->gic_version == VIRT_GIC_VERSION_2) {
95
physical_base_address = memmap[VIRT_GIC_CPU].base;
96
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
97
index XXXXXXX..XXXXXXX 100644
98
--- a/hw/arm/virt.c
99
+++ b/hw/arm/virt.c
100
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
101
}
102
qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
103
qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
104
- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
105
- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
106
- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
107
- GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
108
+ GIC_FDT_IRQ_TYPE_PPI,
109
+ INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
110
+ GIC_FDT_IRQ_TYPE_PPI,
111
+ INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
112
+ GIC_FDT_IRQ_TYPE_PPI,
113
+ INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
114
+ GIC_FDT_IRQ_TYPE_PPI,
115
+ INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
116
}
117
118
static void fdt_add_cpu_nodes(const VirtMachineState *vms)
119
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
120
*/
121
for (i = 0; i < smp_cpus; i++) {
122
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
123
- int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
124
+ int intidbase = NUM_IRQS + i * GIC_INTERNAL;
125
/* Mapping from the output timer irq lines from the CPU to the
126
* GIC PPI inputs we use for the virt board.
127
*/
128
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
129
for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
130
qdev_connect_gpio_out(cpudev, irq,
131
qdev_get_gpio_in(vms->gic,
132
- ppibase + timer_irq[irq]));
133
+ intidbase + timer_irq[irq]));
134
}
135
136
if (vms->gic_version != VIRT_GIC_VERSION_2) {
137
qemu_irq irq = qdev_get_gpio_in(vms->gic,
138
- ppibase + ARCH_GIC_MAINT_IRQ);
139
+ intidbase + ARCH_GIC_MAINT_IRQ);
140
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
141
0, irq);
142
} else if (vms->virt) {
143
qemu_irq irq = qdev_get_gpio_in(vms->gic,
144
- ppibase + ARCH_GIC_MAINT_IRQ);
145
+ intidbase + ARCH_GIC_MAINT_IRQ);
146
sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
147
}
148
149
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
150
- qdev_get_gpio_in(vms->gic, ppibase
151
+ qdev_get_gpio_in(vms->gic, intidbase
152
+ VIRTUAL_PMU_IRQ));
153
154
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
155
@@ -XXX,XX +XXX,XX @@ static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
156
if (pmu) {
157
assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
158
if (kvm_irqchip_in_kernel()) {
159
- kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
160
+ kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ);
161
}
162
kvm_arm_pmu_init(cpu);
163
}
164
--
165
2.34.1
diff view generated by jsdifflib
New patch
[PULL 11/24] include/hw/arm: move BSA definitions to bsa.h
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
2
3
virt.h defines a number of IRQs that are ultimately described by Arm's
4
Base System Architecture specification. Move these to a dedicated header
5
so that they can be reused by other platforms that do the same.
6
Include that header from virt.h to minimise churn.
7
8
While we're moving the definitions, sort them into numerical order,
9
and add the ARCH_TIMER_NS_EL2_VIRT_IRQ definition used by sbsa-ref
10
and which will eventually be needed by virt also.
11
12
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
13
Message-id: 20230919090229.188092-3-quic_llindhol@quicinc.com
14
[PMM: Remove unused PPI_TO_INTID macro; sort numerically;
15
add ARCH_TIMER_NS_EL2_VIRT_IRQ]
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/arm/bsa.h | 35 +++++++++++++++++++++++++++++++++++
20
include/hw/arm/virt.h | 12 +-----------
21
2 files changed, 36 insertions(+), 11 deletions(-)
22
create mode 100644 include/hw/arm/bsa.h
23
24
diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
25
new file mode 100644
26
index XXXXXXX..XXXXXXX
27
--- /dev/null
28
+++ b/include/hw/arm/bsa.h
29
@@ -XXX,XX +XXX,XX @@
30
+/*
31
+ * Common definitions for Arm Base System Architecture (BSA) platforms.
32
+ *
33
+ * Copyright (c) 2015 Linaro Limited
34
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
35
+ *
36
+ * This program is free software; you can redistribute it and/or modify it
37
+ * under the terms and conditions of the GNU General Public License,
38
+ * version 2 or later, as published by the Free Software Foundation.
39
+ *
40
+ * This program is distributed in the hope it will be useful, but WITHOUT
41
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
42
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
43
+ * more details.
44
+ *
45
+ * You should have received a copy of the GNU General Public License along with
46
+ * this program. If not, see <http://www.gnu.org/licenses/>.
47
+ *
48
+ */
49
+
50
+#ifndef QEMU_ARM_BSA_H
51
+#define QEMU_ARM_BSA_H
52
+
53
+/* These are architectural INTID values */
54
+#define VIRTUAL_PMU_IRQ 23
55
+#define ARCH_GIC_MAINT_IRQ 25
56
+#define ARCH_TIMER_NS_EL2_IRQ 26
57
+#define ARCH_TIMER_VIRT_IRQ 27
58
+#define ARCH_TIMER_NS_EL2_VIRT_IRQ 28
59
+#define ARCH_TIMER_S_EL1_IRQ 29
60
+#define ARCH_TIMER_NS_EL1_IRQ 30
61
+
62
+#define INTID_TO_PPI(irq) ((irq) - 16)
63
+
64
+#endif /* QEMU_ARM_BSA_H */
65
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
66
index XXXXXXX..XXXXXXX 100644
67
--- a/include/hw/arm/virt.h
68
+++ b/include/hw/arm/virt.h
69
@@ -XXX,XX +XXX,XX @@
70
#include "qemu/notify.h"
71
#include "hw/boards.h"
72
#include "hw/arm/boot.h"
73
+#include "hw/arm/bsa.h"
74
#include "hw/block/flash.h"
75
#include "sysemu/kvm.h"
76
#include "hw/intc/arm_gicv3_common.h"
77
@@ -XXX,XX +XXX,XX @@
78
#define NUM_VIRTIO_TRANSPORTS 32
79
#define NUM_SMMU_IRQS 4
80
81
-#define ARCH_GIC_MAINT_IRQ 25
82
-
83
-#define ARCH_TIMER_VIRT_IRQ 27
84
-#define ARCH_TIMER_S_EL1_IRQ 29
85
-#define ARCH_TIMER_NS_EL1_IRQ 30
86
-#define ARCH_TIMER_NS_EL2_IRQ 26
87
-
88
-#define VIRTUAL_PMU_IRQ 23
89
-
90
-#define INTID_TO_PPI(irq) ((irq) - 16)
91
-
92
/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
93
#define PVTIME_SIZE_PER_CPU 64
94
95
--
96
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/24] hw/arm/sbsa-ref: use bsa.h for PPI definitions
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
1
2
3
Use the private peripheral interrupt definitions from bsa.h instead of
4
defining them locally. Refactor to use the INTIDs defined there instead
5
of the PPI# used previously.
6
7
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
8
Message-id: 20230919090229.188092-4-quic_llindhol@quicinc.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/sbsa-ref.c | 21 +++++++++------------
13
1 file changed, 9 insertions(+), 12 deletions(-)
14
15
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/sbsa-ref.c
18
+++ b/hw/arm/sbsa-ref.c
19
@@ -XXX,XX +XXX,XX @@
20
* ARM SBSA Reference Platform emulation
21
*
22
* Copyright (c) 2018 Linaro Limited
23
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
24
* Written by Hongbo Zhang <hongbo.zhang@linaro.org>
25
*
26
* This program is free software; you can redistribute it and/or modify it
27
@@ -XXX,XX +XXX,XX @@
28
#include "exec/hwaddr.h"
29
#include "kvm_arm.h"
30
#include "hw/arm/boot.h"
31
+#include "hw/arm/bsa.h"
32
#include "hw/arm/fdt.h"
33
#include "hw/arm/smmuv3.h"
34
#include "hw/block/flash.h"
35
@@ -XXX,XX +XXX,XX @@
36
#define NUM_SMMU_IRQS 4
37
#define NUM_SATA_PORTS 6
38
39
-#define VIRTUAL_PMU_IRQ 7
40
-#define ARCH_GIC_MAINT_IRQ 9
41
-#define ARCH_TIMER_VIRT_IRQ 11
42
-#define ARCH_TIMER_S_EL1_IRQ 13
43
-#define ARCH_TIMER_NS_EL1_IRQ 14
44
-#define ARCH_TIMER_NS_EL2_IRQ 10
45
-#define ARCH_TIMER_NS_EL2_VIRT_IRQ 12
46
-
47
enum {
48
SBSA_FLASH,
49
SBSA_MEM,
50
@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
51
*/
52
for (i = 0; i < smp_cpus; i++) {
53
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
54
- int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
55
+ int intidbase = NUM_IRQS + i * GIC_INTERNAL;
56
int irq;
57
/*
58
* Mapping from the output timer irq lines from the CPU to the
59
@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
60
for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
61
qdev_connect_gpio_out(cpudev, irq,
62
qdev_get_gpio_in(sms->gic,
63
- ppibase + timer_irq[irq]));
64
+ intidbase + timer_irq[irq]));
65
}
66
67
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
68
- qdev_get_gpio_in(sms->gic, ppibase
69
+ qdev_get_gpio_in(sms->gic,
70
+ intidbase
71
+ ARCH_GIC_MAINT_IRQ));
72
+
73
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
74
- qdev_get_gpio_in(sms->gic, ppibase
75
+ qdev_get_gpio_in(sms->gic,
76
+ intidbase
77
+ VIRTUAL_PMU_IRQ));
78
79
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/24] arm/kvm: convert to kvm_set_one_reg
1
1
From: Cornelia Huck <cohuck@redhat.com>
2
3
We can neaten the code by switching to the kvm_set_one_reg function.
4
5
Reviewed-by: Gavin Shan <gshan@redhat.com>
6
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20231010142453.224369-2-cohuck@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/kvm.c | 13 +++------
13
target/arm/kvm64.c | 66 +++++++++++++---------------------------------
14
2 files changed, 21 insertions(+), 58 deletions(-)
15
16
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm.c
19
+++ b/target/arm/kvm.c
20
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
21
bool ok = true;
22
23
for (i = 0; i < cpu->cpreg_array_len; i++) {
24
- struct kvm_one_reg r;
25
uint64_t regidx = cpu->cpreg_indexes[i];
26
uint32_t v32;
27
int ret;
28
@@ -XXX,XX +XXX,XX @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
29
continue;
30
}
31
32
- r.id = regidx;
33
switch (regidx & KVM_REG_SIZE_MASK) {
34
case KVM_REG_SIZE_U32:
35
v32 = cpu->cpreg_values[i];
36
- r.addr = (uintptr_t)&v32;
37
+ ret = kvm_set_one_reg(cs, regidx, &v32);
38
break;
39
case KVM_REG_SIZE_U64:
40
- r.addr = (uintptr_t)(cpu->cpreg_values + i);
41
+ ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i);
42
break;
43
default:
44
g_assert_not_reached();
45
}
46
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
47
if (ret) {
48
/* We might fail for "unknown register" and also for
49
* "you tried to set a register which is constant with
50
@@ -XXX,XX +XXX,XX @@ void kvm_arm_get_virtual_time(CPUState *cs)
51
void kvm_arm_put_virtual_time(CPUState *cs)
52
{
53
ARMCPU *cpu = ARM_CPU(cs);
54
- struct kvm_one_reg reg = {
55
- .id = KVM_REG_ARM_TIMER_CNT,
56
- .addr = (uintptr_t)&cpu->kvm_vtime,
57
- };
58
int ret;
59
60
if (!cpu->kvm_vtime_dirty) {
61
return;
62
}
63
64
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
65
+ ret = kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime);
66
if (ret) {
67
error_report("Failed to set KVM_REG_ARM_TIMER_CNT");
68
abort();
69
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/arm/kvm64.c
72
+++ b/target/arm/kvm64.c
73
@@ -XXX,XX +XXX,XX @@ static int kvm_arm_sve_set_vls(CPUState *cs)
74
{
75
ARMCPU *cpu = ARM_CPU(cs);
76
uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = { cpu->sve_vq.map };
77
- struct kvm_one_reg reg = {
78
- .id = KVM_REG_ARM64_SVE_VLS,
79
- .addr = (uint64_t)&vls[0],
80
- };
81
82
assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);
83
84
- return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
85
+ return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]);
86
}
87
88
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
89
@@ -XXX,XX +XXX,XX @@ static void kvm_inject_arm_sea(CPUState *c)
90
static int kvm_arch_put_fpsimd(CPUState *cs)
91
{
92
CPUARMState *env = &ARM_CPU(cs)->env;
93
- struct kvm_one_reg reg;
94
int i, ret;
95
96
for (i = 0; i < 32; i++) {
97
uint64_t *q = aa64_vfp_qreg(env, i);
98
#if HOST_BIG_ENDIAN
99
uint64_t fp_val[2] = { q[1], q[0] };
100
- reg.addr = (uintptr_t)fp_val;
101
+ ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]),
102
+ fp_val);
103
#else
104
- reg.addr = (uintptr_t)q;
105
+ ret = kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q);
106
#endif
107
- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
108
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
109
if (ret) {
110
return ret;
111
}
112
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
113
CPUARMState *env = &cpu->env;
114
uint64_t tmp[ARM_MAX_VQ * 2];
115
uint64_t *r;
116
- struct kvm_one_reg reg;
117
int n, ret;
118
119
for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
120
r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
121
- reg.addr = (uintptr_t)r;
122
- reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
123
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
124
+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r);
125
if (ret) {
126
return ret;
127
}
128
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
129
for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
130
r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
131
DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
132
- reg.addr = (uintptr_t)r;
133
- reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
134
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
135
+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r);
136
if (ret) {
137
return ret;
138
}
139
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
140
141
r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],
142
DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
143
- reg.addr = (uintptr_t)r;
144
- reg.id = KVM_REG_ARM64_SVE_FFR(0);
145
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
146
+ ret = kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r);
147
if (ret) {
148
return ret;
149
}
150
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_sve(CPUState *cs)
151
152
int kvm_arch_put_registers(CPUState *cs, int level)
153
{
154
- struct kvm_one_reg reg;
155
uint64_t val;
156
uint32_t fpr;
157
int i, ret;
158
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
159
}
160
161
for (i = 0; i < 31; i++) {
162
- reg.id = AARCH64_CORE_REG(regs.regs[i]);
163
- reg.addr = (uintptr_t) &env->xregs[i];
164
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
165
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]),
166
+ &env->xregs[i]);
167
if (ret) {
168
return ret;
169
}
170
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
171
*/
172
aarch64_save_sp(env, 1);
173
174
- reg.id = AARCH64_CORE_REG(regs.sp);
175
- reg.addr = (uintptr_t) &env->sp_el[0];
176
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
177
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]);
178
if (ret) {
179
return ret;
180
}
181
182
- reg.id = AARCH64_CORE_REG(sp_el1);
183
- reg.addr = (uintptr_t) &env->sp_el[1];
184
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
185
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]);
186
if (ret) {
187
return ret;
188
}
189
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
190
} else {
191
val = cpsr_read(env);
192
}
193
- reg.id = AARCH64_CORE_REG(regs.pstate);
194
- reg.addr = (uintptr_t) &val;
195
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
196
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val);
197
if (ret) {
198
return ret;
199
}
200
201
- reg.id = AARCH64_CORE_REG(regs.pc);
202
- reg.addr = (uintptr_t) &env->pc;
203
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
204
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc);
205
if (ret) {
206
return ret;
207
}
208
209
- reg.id = AARCH64_CORE_REG(elr_el1);
210
- reg.addr = (uintptr_t) &env->elr_el[1];
211
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
212
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]);
213
if (ret) {
214
return ret;
215
}
216
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
217
218
/* KVM 0-4 map to QEMU banks 1-5 */
219
for (i = 0; i < KVM_NR_SPSR; i++) {
220
- reg.id = AARCH64_CORE_REG(spsr[i]);
221
- reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
222
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
223
+ ret = kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]),
224
+ &env->banked_spsr[i + 1]);
225
if (ret) {
226
return ret;
227
}
228
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
229
return ret;
230
}
231
232
- reg.addr = (uintptr_t)(&fpr);
233
fpr = vfp_get_fpsr(env);
234
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
235
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
236
+ ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);
237
if (ret) {
238
return ret;
239
}
240
241
- reg.addr = (uintptr_t)(&fpr);
242
fpr = vfp_get_fpcr(env);
243
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
244
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
245
+ ret = kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr);
246
if (ret) {
247
return ret;
248
}
249
--
250
2.34.1
251
252
diff view generated by jsdifflib
New patch
[PULL 14/24] arm/kvm: convert to kvm_get_one_reg
1
1
From: Cornelia Huck <cohuck@redhat.com>
2
3
We can neaten the code by switching the callers that work on a
4
CPUstate to the kvm_get_one_reg function.
5
6
Reviewed-by: Gavin Shan <gshan@redhat.com>
7
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20231010142453.224369-3-cohuck@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/kvm.c | 15 +++---------
14
target/arm/kvm64.c | 57 ++++++++++++----------------------------------
15
2 files changed, 18 insertions(+), 54 deletions(-)
16
17
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/kvm.c
20
+++ b/target/arm/kvm.c
21
@@ -XXX,XX +XXX,XX @@ bool write_kvmstate_to_list(ARMCPU *cpu)
22
bool ok = true;
23
24
for (i = 0; i < cpu->cpreg_array_len; i++) {
25
- struct kvm_one_reg r;
26
uint64_t regidx = cpu->cpreg_indexes[i];
27
uint32_t v32;
28
int ret;
29
30
- r.id = regidx;
31
-
32
switch (regidx & KVM_REG_SIZE_MASK) {
33
case KVM_REG_SIZE_U32:
34
- r.addr = (uintptr_t)&v32;
35
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
36
+ ret = kvm_get_one_reg(cs, regidx, &v32);
37
if (!ret) {
38
cpu->cpreg_values[i] = v32;
39
}
40
break;
41
case KVM_REG_SIZE_U64:
42
- r.addr = (uintptr_t)(cpu->cpreg_values + i);
43
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
44
+ ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i);
45
break;
46
default:
47
g_assert_not_reached();
48
@@ -XXX,XX +XXX,XX @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu)
49
void kvm_arm_get_virtual_time(CPUState *cs)
50
{
51
ARMCPU *cpu = ARM_CPU(cs);
52
- struct kvm_one_reg reg = {
53
- .id = KVM_REG_ARM_TIMER_CNT,
54
- .addr = (uintptr_t)&cpu->kvm_vtime,
55
- };
56
int ret;
57
58
if (cpu->kvm_vtime_dirty) {
59
return;
60
}
61
62
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
63
+ ret = kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime);
64
if (ret) {
65
error_report("Failed to get KVM_REG_ARM_TIMER_CNT");
66
abort();
67
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/kvm64.c
70
+++ b/target/arm/kvm64.c
71
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
72
static int kvm_arch_get_fpsimd(CPUState *cs)
73
{
74
CPUARMState *env = &ARM_CPU(cs)->env;
75
- struct kvm_one_reg reg;
76
int i, ret;
77
78
for (i = 0; i < 32; i++) {
79
uint64_t *q = aa64_vfp_qreg(env, i);
80
- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
81
- reg.addr = (uintptr_t)q;
82
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
83
+ ret = kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]), q);
84
if (ret) {
85
return ret;
86
} else {
87
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
88
{
89
ARMCPU *cpu = ARM_CPU(cs);
90
CPUARMState *env = &cpu->env;
91
- struct kvm_one_reg reg;
92
uint64_t *r;
93
int n, ret;
94
95
for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
96
r = &env->vfp.zregs[n].d[0];
97
- reg.addr = (uintptr_t)r;
98
- reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
99
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
100
+ ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r);
101
if (ret) {
102
return ret;
103
}
104
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
105
106
for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
107
r = &env->vfp.pregs[n].p[0];
108
- reg.addr = (uintptr_t)r;
109
- reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
110
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
111
+ ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r);
112
if (ret) {
113
return ret;
114
}
115
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
116
}
117
118
r = &env->vfp.pregs[FFR_PRED_NUM].p[0];
119
- reg.addr = (uintptr_t)r;
120
- reg.id = KVM_REG_ARM64_SVE_FFR(0);
121
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
122
+ ret = kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r);
123
if (ret) {
124
return ret;
125
}
126
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_sve(CPUState *cs)
127
128
int kvm_arch_get_registers(CPUState *cs)
129
{
130
- struct kvm_one_reg reg;
131
uint64_t val;
132
unsigned int el;
133
uint32_t fpr;
134
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
135
CPUARMState *env = &cpu->env;
136
137
for (i = 0; i < 31; i++) {
138
- reg.id = AARCH64_CORE_REG(regs.regs[i]);
139
- reg.addr = (uintptr_t) &env->xregs[i];
140
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
141
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]),
142
+ &env->xregs[i]);
143
if (ret) {
144
return ret;
145
}
146
}
147
148
- reg.id = AARCH64_CORE_REG(regs.sp);
149
- reg.addr = (uintptr_t) &env->sp_el[0];
150
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
151
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]);
152
if (ret) {
153
return ret;
154
}
155
156
- reg.id = AARCH64_CORE_REG(sp_el1);
157
- reg.addr = (uintptr_t) &env->sp_el[1];
158
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
159
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]);
160
if (ret) {
161
return ret;
162
}
163
164
- reg.id = AARCH64_CORE_REG(regs.pstate);
165
- reg.addr = (uintptr_t) &val;
166
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
167
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val);
168
if (ret) {
169
return ret;
170
}
171
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
172
*/
173
aarch64_restore_sp(env, 1);
174
175
- reg.id = AARCH64_CORE_REG(regs.pc);
176
- reg.addr = (uintptr_t) &env->pc;
177
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
178
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc);
179
if (ret) {
180
return ret;
181
}
182
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
183
aarch64_sync_64_to_32(env);
184
}
185
186
- reg.id = AARCH64_CORE_REG(elr_el1);
187
- reg.addr = (uintptr_t) &env->elr_el[1];
188
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
189
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]);
190
if (ret) {
191
return ret;
192
}
193
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
194
* KVM SPSRs 0-4 map to QEMU banks 1-5
195
*/
196
for (i = 0; i < KVM_NR_SPSR; i++) {
197
- reg.id = AARCH64_CORE_REG(spsr[i]);
198
- reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
199
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
200
+ ret = kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]),
201
+ &env->banked_spsr[i + 1]);
202
if (ret) {
203
return ret;
204
}
205
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
206
return ret;
207
}
208
209
- reg.addr = (uintptr_t)(&fpr);
210
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
211
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
212
+ ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr);
213
if (ret) {
214
return ret;
215
}
216
vfp_set_fpsr(env, fpr);
217
218
- reg.addr = (uintptr_t)(&fpr);
219
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
220
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
221
+ ret = kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr);
222
if (ret) {
223
return ret;
224
}
225
--
226
2.34.1
227
228
diff view generated by jsdifflib
New patch
[PULL 15/24] target/arm: Permit T32 LDM with single register
1
For the Thumb T32 encoding of LDM, if only a single register is
2
specified in the register list this instruction is UNPREDICTABLE,
3
with the following choices:
4
* instruction UNDEFs
5
* instruction is a NOP
6
* instruction loads a single register
7
* instruction loads an unspecified set of registers
1
8
9
Currently we choose to UNDEF (a behaviour chosen in commit
10
4b222545dbf30 in 2019; previously we treated it as "load the
11
specified single register").
12
13
Unfortunately there is real world code out there (which shipped in at
14
least Android 11, 12 and 13) which incorrectly uses this
15
UNPREDICTABLE insn on the assumption that it does a single register
16
load, which is (presumably) what it happens to do on real hardware,
17
and is also what it does on the equivalent A32 encoding.
18
19
Revert to the pre-4b222545dbf30 behaviour of not UNDEFing
20
for this T32 encoding.
21
22
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1799
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20230927101853.39288-1-peter.maydell@linaro.org
27
---
28
target/arm/tcg/translate.c | 37 +++++++++++++++++++++++--------------
29
1 file changed, 23 insertions(+), 14 deletions(-)
30
31
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/tcg/translate.c
34
+++ b/target/arm/tcg/translate.c
35
@@ -XXX,XX +XXX,XX @@ static void op_addr_block_post(DisasContext *s, arg_ldst_block *a,
36
}
37
}
38
39
-static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
40
+static bool op_stm(DisasContext *s, arg_ldst_block *a)
41
{
42
int i, j, n, list, mem_idx;
43
bool user = a->u;
44
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
45
46
list = a->list;
47
n = ctpop16(list);
48
- if (n < min_n || a->rn == 15) {
49
+ /*
50
+ * This is UNPREDICTABLE for n < 1 in all encodings, and we choose
51
+ * to UNDEF. In the T32 STM encoding n == 1 is also UNPREDICTABLE,
52
+ * but hardware treats it like the A32 version and implements the
53
+ * single-register-store, and some in-the-wild (buggy) software
54
+ * assumes that, so we don't UNDEF on that case.
55
+ */
56
+ if (n < 1 || a->rn == 15) {
57
unallocated_encoding(s);
58
return true;
59
}
60
@@ -XXX,XX +XXX,XX @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
61
62
static bool trans_STM(DisasContext *s, arg_ldst_block *a)
63
{
64
- /* BitCount(list) < 1 is UNPREDICTABLE */
65
- return op_stm(s, a, 1);
66
+ return op_stm(s, a);
67
}
68
69
static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a)
70
@@ -XXX,XX +XXX,XX @@ static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a)
71
unallocated_encoding(s);
72
return true;
73
}
74
- /* BitCount(list) < 2 is UNPREDICTABLE */
75
- return op_stm(s, a, 2);
76
+ return op_stm(s, a);
77
}
78
79
-static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
80
+static bool do_ldm(DisasContext *s, arg_ldst_block *a)
81
{
82
int i, j, n, list, mem_idx;
83
bool loaded_base;
84
@@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
85
86
list = a->list;
87
n = ctpop16(list);
88
- if (n < min_n || a->rn == 15) {
89
+ /*
90
+ * This is UNPREDICTABLE for n < 1 in all encodings, and we choose
91
+ * to UNDEF. In the T32 LDM encoding n == 1 is also UNPREDICTABLE,
92
+ * but hardware treats it like the A32 version and implements the
93
+ * single-register-load, and some in-the-wild (buggy) software
94
+ * assumes that, so we don't UNDEF on that case.
95
+ */
96
+ if (n < 1 || a->rn == 15) {
97
unallocated_encoding(s);
98
return true;
99
}
100
@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a)
101
unallocated_encoding(s);
102
return true;
103
}
104
- /* BitCount(list) < 1 is UNPREDICTABLE */
105
- return do_ldm(s, a, 1);
106
+ return do_ldm(s, a);
107
}
108
109
static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
110
@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
111
unallocated_encoding(s);
112
return true;
113
}
114
- /* BitCount(list) < 2 is UNPREDICTABLE */
115
- return do_ldm(s, a, 2);
116
+ return do_ldm(s, a);
117
}
118
119
static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
120
{
121
/* Writeback is conditional on the base register not being loaded. */
122
a->w = !(a->list & (1 << a->rn));
123
- /* BitCount(list) < 1 is UNPREDICTABLE */
124
- return do_ldm(s, a, 1);
125
+ return do_ldm(s, a);
126
}
127
128
static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
129
--
130
2.34.1
131
132
diff view generated by jsdifflib
New patch
[PULL 16/24] hw/arm/smmuv3: Update ID register bit field definitions
1
Update the SMMUv3 ID register bit field definitions to the
2
set in the most recent specification (IHI0700 F.a).
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Mostafa Saleh <smostafa@google.com>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20230914145705.1648377-2-peter.maydell@linaro.org
9
---
10
hw/arm/smmuv3-internal.h | 38 ++++++++++++++++++++++++++++++++++++++
11
1 file changed, 38 insertions(+)
12
13
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/smmuv3-internal.h
16
+++ b/hw/arm/smmuv3-internal.h
17
@@ -XXX,XX +XXX,XX @@ REG32(IDR0, 0x0)
18
FIELD(IDR0, S1P, 1 , 1)
19
FIELD(IDR0, TTF, 2 , 2)
20
FIELD(IDR0, COHACC, 4 , 1)
21
+ FIELD(IDR0, BTM, 5 , 1)
22
+ FIELD(IDR0, HTTU, 6 , 2)
23
+ FIELD(IDR0, DORMHINT, 8 , 1)
24
+ FIELD(IDR0, HYP, 9 , 1)
25
+ FIELD(IDR0, ATS, 10, 1)
26
+ FIELD(IDR0, NS1ATS, 11, 1)
27
FIELD(IDR0, ASID16, 12, 1)
28
+ FIELD(IDR0, MSI, 13, 1)
29
+ FIELD(IDR0, SEV, 14, 1)
30
+ FIELD(IDR0, ATOS, 15, 1)
31
+ FIELD(IDR0, PRI, 16, 1)
32
+ FIELD(IDR0, VMW, 17, 1)
33
FIELD(IDR0, VMID16, 18, 1)
34
+ FIELD(IDR0, CD2L, 19, 1)
35
+ FIELD(IDR0, VATOS, 20, 1)
36
FIELD(IDR0, TTENDIAN, 21, 2)
37
+ FIELD(IDR0, ATSRECERR, 23, 1)
38
FIELD(IDR0, STALL_MODEL, 24, 2)
39
FIELD(IDR0, TERM_MODEL, 26, 1)
40
FIELD(IDR0, STLEVEL, 27, 2)
41
+ FIELD(IDR0, RME_IMPL, 30, 1)
42
43
REG32(IDR1, 0x4)
44
FIELD(IDR1, SIDSIZE, 0 , 6)
45
+ FIELD(IDR1, SSIDSIZE, 6 , 5)
46
+ FIELD(IDR1, PRIQS, 11, 5)
47
FIELD(IDR1, EVENTQS, 16, 5)
48
FIELD(IDR1, CMDQS, 21, 5)
49
+ FIELD(IDR1, ATTR_PERMS_OVR, 26, 1)
50
+ FIELD(IDR1, ATTR_TYPES_OVR, 27, 1)
51
+ FIELD(IDR1, REL, 28, 1)
52
+ FIELD(IDR1, QUEUES_PRESET, 29, 1)
53
+ FIELD(IDR1, TABLES_PRESET, 30, 1)
54
+ FIELD(IDR1, ECMDQ, 31, 1)
55
56
#define SMMU_IDR1_SIDSIZE 16
57
#define SMMU_CMDQS 19
58
#define SMMU_EVENTQS 19
59
60
REG32(IDR2, 0x8)
61
+ FIELD(IDR2, BA_VATOS, 0, 10)
62
+
63
REG32(IDR3, 0xc)
64
FIELD(IDR3, HAD, 2, 1);
65
+ FIELD(IDR3, PBHA, 3, 1);
66
+ FIELD(IDR3, XNX, 4, 1);
67
+ FIELD(IDR3, PPS, 5, 1);
68
+ FIELD(IDR3, MPAM, 7, 1);
69
+ FIELD(IDR3, FWB, 8, 1);
70
+ FIELD(IDR3, STT, 9, 1);
71
FIELD(IDR3, RIL, 10, 1);
72
FIELD(IDR3, BBML, 11, 2);
73
+ FIELD(IDR3, E0PD, 13, 1);
74
+ FIELD(IDR3, PTWNNC, 14, 1);
75
+ FIELD(IDR3, DPT, 15, 1);
76
+
77
REG32(IDR4, 0x10)
78
+
79
REG32(IDR5, 0x14)
80
FIELD(IDR5, OAS, 0, 3);
81
FIELD(IDR5, GRAN4K, 4, 1);
82
FIELD(IDR5, GRAN16K, 5, 1);
83
FIELD(IDR5, GRAN64K, 6, 1);
84
+ FIELD(IDR5, VAX, 10, 2);
85
+ FIELD(IDR5, STALL_MAX, 16, 16);
86
87
#define SMMU_IDR5_OAS 4
88
89
--
90
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/24] hw/arm/smmuv3: Sort ID register setting into field order
1
In smmuv3_init_regs() when we set the various bits in the ID
2
registers, we do this almost in order of the fields in the
3
registers, but not quite. Move the initialization of
4
SMMU_IDR3.RIL and SMMU_IDR5.OAS into their correct places.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Mostafa Saleh <smostafa@google.com>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Message-id: 20230914145705.1648377-3-peter.maydell@linaro.org
11
---
12
hw/arm/smmuv3.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/smmuv3.c
18
+++ b/hw/arm/smmuv3.c
19
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
20
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
21
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS);
22
23
- s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
24
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
25
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
26
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
27
28
+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
29
/* 4K, 16K and 64K granule support */
30
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);
31
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1);
32
s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
33
- s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */
34
35
s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);
36
s->cmdq.prod = 0;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/24] hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature
1
The SMMUv3.1-XNX feature is mandatory for an SMMUv3.1 if S2P is
2
supported, so we should theoretically have implemented it as part of
3
the recent S2P work. Fortunately, for us the implementation is a
4
no-op.
1
5
6
This feature is about interpretation of the stage 2 page table
7
descriptor XN bits, which control execute permissions.
8
9
For QEMU, the permission bits passed to an IOMMU (via MemTxAttrs and
10
IOMMUAccessFlags) only indicate read and write; we do not distinguish
11
data reads from instruction reads outside the CPU proper. In the
12
SMMU architecture's terms, our interconnect between the client device
13
and the SMMU doesn't have the ability to convey the INST attribute,
14
and we therefore use the default value of "data" for this attribute.
15
16
We also do not support the bits in the Stream Table Entry that can
17
override the on-the-bus transaction attribute permissions (we do not
18
set SMMU_IDR1.ATTR_PERMS_OVR=1).
19
20
These two things together mean that for our implementation, it never
21
has to deal with transactions with the INST attribute, and so it can
22
correctly ignore the XN bits entirely. So we already implement
23
FEAT_XNX's "XN field is now 2 bits, not 1" behaviour to the extent
24
that we need to.
25
26
Advertise the presence of the feature in SMMU_IDR3.XNX.
27
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
30
Reviewed-by: Mostafa Saleh <smostafa@google.com>
31
Reviewed-by: Eric Auger <eric.auger@redhat.com>
32
Message-id: 20230914145705.1648377-4-peter.maydell@linaro.org
33
---
34
hw/arm/smmuv3.c | 4 ++++
35
1 file changed, 4 insertions(+)
36
37
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/smmuv3.c
40
+++ b/hw/arm/smmuv3.c
41
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
42
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS);
43
44
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
45
+ if (FIELD_EX32(s->idr[0], IDR0, S2P)) {
46
+ /* XNX is a stage-2-specific feature */
47
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, XNX, 1);
48
+ }
49
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
50
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
51
52
--
53
2.34.1
diff view generated by jsdifflib
New patch
[PULL 19/24] target/arm: Implement FEAT_HPMN0
1
FEAT_HPMN0 is a small feature which defines that it is valid for
2
MDCR_EL2.HPMN to be set to 0, meaning "no PMU event counters provided
3
to an EL1 guest" (previously this setting was reserved). QEMU's
4
implementation almost gets HPMN == 0 right, but we need to fix
5
one check in pmevcntr_is_64_bit(). That is enough for us to
6
advertise the feature in the 'max' CPU.
1
7
8
(We don't need to make the behaviour conditional on feature
9
presence, because the FEAT_HPMN0 behaviour is within the range
10
of permitted UNPREDICTABLE behaviour for a non-FEAT_HPMN0
11
implementation.)
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20230921185445.3339214-1-peter.maydell@linaro.org
16
---
17
docs/system/arm/emulation.rst | 1 +
18
target/arm/helper.c | 2 +-
19
target/arm/tcg/cpu32.c | 4 ++++
20
target/arm/tcg/cpu64.c | 1 +
21
4 files changed, 7 insertions(+), 1 deletion(-)
22
23
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
24
index XXXXXXX..XXXXXXX 100644
25
--- a/docs/system/arm/emulation.rst
26
+++ b/docs/system/arm/emulation.rst
27
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
28
- FEAT_HCX (Support for the HCRX_EL2 register)
29
- FEAT_HPDS (Hierarchical permission disables)
30
- FEAT_HPDS2 (Translation table page-based hardware attributes)
31
+- FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero)
32
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
33
- FEAT_IDST (ID space trap handling)
34
- FEAT_IESB (Implicit error synchronization event)
35
diff --git a/target/arm/helper.c b/target/arm/helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper.c
38
+++ b/target/arm/helper.c
39
@@ -XXX,XX +XXX,XX @@ static bool pmevcntr_is_64_bit(CPUARMState *env, int counter)
40
bool hlp = env->cp15.mdcr_el2 & MDCR_HLP;
41
int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN;
42
43
- if (hpmn != 0 && counter >= hpmn) {
44
+ if (counter >= hpmn) {
45
return hlp;
46
}
47
}
48
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/tcg/cpu32.c
51
+++ b/target/arm/tcg/cpu32.c
52
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
53
t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
54
t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
55
cpu->isar.id_dfr0 = t;
56
+
57
+ t = cpu->isar.id_dfr1;
58
+ t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
59
+ cpu->isar.id_dfr1 = t;
60
}
61
62
/* CPU models. These are not needed for the AArch64 linux-user build. */
63
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/tcg/cpu64.c
66
+++ b/target/arm/tcg/cpu64.c
67
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
68
t = cpu->isar.id_aa64dfr0;
69
t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
70
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
71
+ t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
72
cpu->isar.id_aa64dfr0 = t;
73
74
t = cpu->isar.id_aa64smfr0;
75
--
76
2.34.1
diff view generated by jsdifflib
New patch
[PULL 20/24] target/arm/kvm64.c: Remove unused include
1
The include of hw/arm/virt.h in kvm64.c is unnecessary and also a
2
layering violation since the generic KVM code shouldn't need to know
3
anything about board-specifics. The include line is an accidental
4
leftover from commit 15613357ba53a4763, where we cleaned up the code
5
to not depend on virt board internals but forgot to also remove the
6
now-redundant include line.
1
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Gavin Shan <gshan@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20230925110429.3917202-1-peter.maydell@linaro.org
12
---
13
target/arm/kvm64.c | 1 -
14
1 file changed, 1 deletion(-)
15
16
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/kvm64.c
19
+++ b/target/arm/kvm64.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "internals.h"
22
#include "hw/acpi/acpi.h"
23
#include "hw/acpi/ghes.h"
24
-#include "hw/arm/virt.h"
25
26
static bool have_guest_debug;
27
28
--
29
2.34.1
30
31
diff view generated by jsdifflib
New patch
[PULL 21/24] target/arm/common-semi-target.h: Remove unnecessary boot.h include
1
The hw/arm/boot.h include in common-semi-target.h is not actually
2
needed, and it's a bit odd because it pulls a hw/arm header into a
3
target/arm file.
1
4
5
This include was originally needed because the semihosting code used
6
the arm_boot_info struct to get the base address of the RAM in system
7
emulation, to use in a (bad) heuristic for the return values for the
8
SYS_HEAPINFO semihosting call. We've since overhauled how we
9
calculate the HEAPINFO values in system emulation, and the code no
10
longer uses the arm_boot_info struct.
11
12
Remove the now-redundant include line, and instead directly include
13
the cpu-qom.h header that we were previously getting via boot.h.
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20230925112219.3919261-1-peter.maydell@linaro.org
18
---
19
target/arm/common-semi-target.h | 4 +---
20
1 file changed, 1 insertion(+), 3 deletions(-)
21
22
diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-target.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/common-semi-target.h
25
+++ b/target/arm/common-semi-target.h
26
@@ -XXX,XX +XXX,XX @@
27
#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H
28
#define TARGET_ARM_COMMON_SEMI_TARGET_H
29
30
-#ifndef CONFIG_USER_ONLY
31
-#include "hw/arm/boot.h"
32
-#endif
33
+#include "target/arm/cpu-qom.h"
34
35
static inline target_ulong common_semi_arg(CPUState *cs, int argno)
36
{
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 22/24] target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL
1
1
The code for powering on a CPU in arm-powerctl.c has two separate
2
use cases:
3
* emulation of a real hardware power controller
4
* emulation of firmware interfaces (primarily PSCI) with
5
CPU on/off APIs
6
7
For the first case, we only need to reset the CPU and set its
8
starting PC and X0. For the second case, because we're emulating the
9
firmware we need to ensure that it's in the state that the firmware
10
provides. In particular, when we reset to a lower EL than the
11
highest one we are emulating, we need to put the CPU into a state
12
that permits correct running at that lower EL. We already do a
13
little of this in arm-powerctl.c (for instance we set SCR_HCE to
14
enable the HVC insn) but we don't do enough of it. This means that
15
in the case where we are emulating EL3 but also providing emulated
16
PSCI the guest will crash when a secondary core tries to use a
17
feature that needs an SCR_EL3 bit to be set, such as MTE or PAuth.
18
19
The hw/arm/boot.c code also has to support this "start guest code in
20
an EL that's lower than the highest emulated EL" case in order to do
21
direct guest kernel booting; it has all the necessary initialization
22
code to set the SCR_EL3 bits. Pull the relevant boot.c code out into
23
a separate function so we can share it between there and
24
arm-powerctl.c.
25
26
This refactoring has a few code changes that look like they
27
might be behaviour changes but aren't:
28
* if info->secure_boot is false and info->secure_board_setup is
29
true, then the old code would start the first CPU in Hyp
30
mode but without changing SCR.NS and NSACR.{CP11,CP10}.
31
This was wrong behaviour because there's no such thing
32
as Secure Hyp mode. The new code will leave the CPU in SVC.
33
(There is no board which sets secure_boot to false and
34
secure_board_setup to true, so this isn't a behaviour
35
change for any of our boards.)
36
* we don't explicitly clear SCR.NS when arm-powerctl.c
37
does a CPU-on to EL3. This was a no-op because CPU reset
38
will reset to NS == 0.
39
40
And some real behaviour changes:
41
* we no longer set HCR_EL2.RW when booting into EL2: the guest
42
can and should do that themselves before dropping into their
43
EL1 code. (arm-powerctl and boot did this differently; I
44
opted to use the logic from arm-powerctl, which only sets
45
HCR_EL2.RW when it's directly starting the guest in EL1,
46
because it's more correct, and I don't expect guests to be
47
accidentally depending on our having set the RW bit for them.)
48
* if we are booting a CPU into AArch32 Secure SVC then we won't
49
set SCR.HCE any more. This affects only the vexpress-a15 and
50
raspi2b machine types. Guests booting in this case will either:
51
- be able to set SCR.HCE themselves as part of moving from
52
Secure SVC into NS Hyp mode
53
- will move from Secure SVC to NS SVC, and won't care about
54
behaviour of the HVC insn
55
- will stay in Secure SVC, and won't care about HVC
56
* on an arm-powerctl CPU-on we will now set the SCR bits for
57
pauth/mte/sve/sme/hcx/fgt features
58
59
The first two of these are very minor and I don't expect guest
60
code to trip over them, so I didn't judge it worth convoluting
61
the code in an attempt to keep exactly the same boot.c behaviour.
62
The third change fixes issue 1899.
63
64
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1899
65
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
66
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
67
Message-id: 20230926155619.4028618-1-peter.maydell@linaro.org
68
---
69
target/arm/cpu.h | 22 +++++++++
70
hw/arm/boot.c | 95 ++++++++++-----------------------------
71
target/arm/arm-powerctl.c | 53 +---------------------
72
target/arm/cpu.c | 95 +++++++++++++++++++++++++++++++++++++++
73
4 files changed, 141 insertions(+), 124 deletions(-)
74
75
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/cpu.h
78
+++ b/target/arm/cpu.h
79
@@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
80
int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
81
int cpuid, DumpState *s);
82
83
+/**
84
+ * arm_emulate_firmware_reset: Emulate firmware CPU reset handling
85
+ * @cpu: CPU (which must have been freshly reset)
86
+ * @target_el: exception level to put the CPU into
87
+ * @secure: whether to put the CPU in secure state
88
+ *
89
+ * When QEMU is directly running a guest kernel at a lower level than
90
+ * EL3 it implicitly emulates some aspects of the guest firmware.
91
+ * This includes that on reset we need to configure the parts of the
92
+ * CPU corresponding to EL3 so that the real guest code can run at its
93
+ * lower exception level. This function does that post-reset CPU setup,
94
+ * for when we do direct boot of a guest kernel, and for when we
95
+ * emulate PSCI and similar firmware interfaces starting a CPU at a
96
+ * lower exception level.
97
+ *
98
+ * @target_el must be an EL implemented by the CPU between 1 and 3.
99
+ * We do not support dropping into a Secure EL other than 3.
100
+ *
101
+ * It is the responsibility of the caller to call arm_rebuild_hflags().
102
+ */
103
+void arm_emulate_firmware_reset(CPUState *cpustate, int target_el);
104
+
105
#ifdef TARGET_AARCH64
106
int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
107
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
108
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/arm/boot.c
111
+++ b/hw/arm/boot.c
112
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
113
114
cpu_set_pc(cs, entry);
115
} else {
116
- /* If we are booting Linux then we need to check whether we are
117
- * booting into secure or non-secure state and adjust the state
118
- * accordingly. Out of reset, ARM is defined to be in secure state
119
- * (SCR.NS = 0), we change that here if non-secure boot has been
120
- * requested.
121
+ /*
122
+ * If we are booting Linux then we might need to do so at:
123
+ * - AArch64 NS EL2 or NS EL1
124
+ * - AArch32 Secure SVC (EL3)
125
+ * - AArch32 NS Hyp (EL2)
126
+ * - AArch32 NS SVC (EL1)
127
+ * Configure the CPU in the way boot firmware would do to
128
+ * drop us down to the appropriate level.
129
*/
130
- if (arm_feature(env, ARM_FEATURE_EL3)) {
131
- /* AArch64 is defined to come out of reset into EL3 if enabled.
132
- * If we are booting Linux then we need to adjust our EL as
133
- * Linux expects us to be in EL2 or EL1. AArch32 resets into
134
- * SVC, which Linux expects, so no privilege/exception level to
135
- * adjust.
136
- */
137
- if (env->aarch64) {
138
- env->cp15.scr_el3 |= SCR_RW;
139
- if (arm_feature(env, ARM_FEATURE_EL2)) {
140
- env->cp15.hcr_el2 |= HCR_RW;
141
- env->pstate = PSTATE_MODE_EL2h;
142
- } else {
143
- env->pstate = PSTATE_MODE_EL1h;
144
- }
145
- if (cpu_isar_feature(aa64_pauth, cpu)) {
146
- env->cp15.scr_el3 |= SCR_API | SCR_APK;
147
- }
148
- if (cpu_isar_feature(aa64_mte, cpu)) {
149
- env->cp15.scr_el3 |= SCR_ATA;
150
- }
151
- if (cpu_isar_feature(aa64_sve, cpu)) {
152
- env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
153
- env->vfp.zcr_el[3] = 0xf;
154
- }
155
- if (cpu_isar_feature(aa64_sme, cpu)) {
156
- env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
157
- env->cp15.scr_el3 |= SCR_ENTP2;
158
- env->vfp.smcr_el[3] = 0xf;
159
- }
160
- if (cpu_isar_feature(aa64_hcx, cpu)) {
161
- env->cp15.scr_el3 |= SCR_HXEN;
162
- }
163
- if (cpu_isar_feature(aa64_fgt, cpu)) {
164
- env->cp15.scr_el3 |= SCR_FGTEN;
165
- }
166
+ int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
167
168
- /* AArch64 kernels never boot in secure mode */
169
- assert(!info->secure_boot);
170
- /* This hook is only supported for AArch32 currently:
171
- * bootloader_aarch64[] will not call the hook, and
172
- * the code above has already dropped us into EL2 or EL1.
173
- */
174
- assert(!info->secure_board_setup);
175
- }
176
-
177
- if (arm_feature(env, ARM_FEATURE_EL2)) {
178
- /* If we have EL2 then Linux expects the HVC insn to work */
179
- env->cp15.scr_el3 |= SCR_HCE;
180
- }
181
-
182
- /* Set to non-secure if not a secure boot */
183
- if (!info->secure_boot &&
184
- (cs != first_cpu || !info->secure_board_setup)) {
185
- /* Linux expects non-secure state */
186
- env->cp15.scr_el3 |= SCR_NS;
187
- /* Set NSACR.{CP11,CP10} so NS can access the FPU */
188
- env->cp15.nsacr |= 3 << 10;
189
- }
190
- }
191
-
192
- if (!env->aarch64 && !info->secure_boot &&
193
- arm_feature(env, ARM_FEATURE_EL2)) {
194
+ if (env->aarch64) {
195
/*
196
- * This is an AArch32 boot not to Secure state, and
197
- * we have Hyp mode available, so boot the kernel into
198
- * Hyp mode. This is not how the CPU comes out of reset,
199
- * so we need to manually put it there.
200
+ * AArch64 kernels never boot in secure mode, and we don't
201
+ * support the secure_board_setup hook for AArch64.
202
*/
203
- cpsr_write(env, ARM_CPU_MODE_HYP, CPSR_M, CPSRWriteRaw);
204
+ assert(!info->secure_boot);
205
+ assert(!info->secure_board_setup);
206
+ } else {
207
+ if (arm_feature(env, ARM_FEATURE_EL3) &&
208
+ (info->secure_boot ||
209
+ (info->secure_board_setup && cs == first_cpu))) {
210
+ /* Start this CPU in Secure SVC */
211
+ target_el = 3;
212
+ }
213
}
214
215
+ arm_emulate_firmware_reset(cs, target_el);
216
+
217
if (cs == first_cpu) {
218
AddressSpace *as = arm_boot_address_space(cpu, info);
219
220
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
221
index XXXXXXX..XXXXXXX 100644
222
--- a/target/arm/arm-powerctl.c
223
+++ b/target/arm/arm-powerctl.c
224
@@ -XXX,XX +XXX,XX @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state,
225
226
/* Initialize the cpu we are turning on */
227
cpu_reset(target_cpu_state);
228
+ arm_emulate_firmware_reset(target_cpu_state, info->target_el);
229
target_cpu_state->halted = 0;
230
231
- if (info->target_aa64) {
232
- if ((info->target_el < 3) && arm_feature(&target_cpu->env,
233
- ARM_FEATURE_EL3)) {
234
- /*
235
- * As target mode is AArch64, we need to set lower
236
- * exception level (the requested level 2) to AArch64
237
- */
238
- target_cpu->env.cp15.scr_el3 |= SCR_RW;
239
- }
240
-
241
- if ((info->target_el < 2) && arm_feature(&target_cpu->env,
242
- ARM_FEATURE_EL2)) {
243
- /*
244
- * As target mode is AArch64, we need to set lower
245
- * exception level (the requested level 1) to AArch64
246
- */
247
- target_cpu->env.cp15.hcr_el2 |= HCR_RW;
248
- }
249
-
250
- target_cpu->env.pstate = aarch64_pstate_mode(info->target_el, true);
251
- } else {
252
- /* We are requested to boot in AArch32 mode */
253
- static const uint32_t mode_for_el[] = { 0,
254
- ARM_CPU_MODE_SVC,
255
- ARM_CPU_MODE_HYP,
256
- ARM_CPU_MODE_SVC };
257
-
258
- cpsr_write(&target_cpu->env, mode_for_el[info->target_el], CPSR_M,
259
- CPSRWriteRaw);
260
- }
261
-
262
- if (info->target_el == 3) {
263
- /* Processor is in secure mode */
264
- target_cpu->env.cp15.scr_el3 &= ~SCR_NS;
265
- } else {
266
- /* Processor is not in secure mode */
267
- target_cpu->env.cp15.scr_el3 |= SCR_NS;
268
-
269
- /* Set NSACR.{CP11,CP10} so NS can access the FPU */
270
- target_cpu->env.cp15.nsacr |= 3 << 10;
271
-
272
- /*
273
- * If QEMU is providing the equivalent of EL3 firmware, then we need
274
- * to make sure a CPU targeting EL2 comes out of reset with a
275
- * functional HVC insn.
276
- */
277
- if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3)
278
- && info->target_el == 2) {
279
- target_cpu->env.cp15.scr_el3 |= SCR_HCE;
280
- }
281
- }
282
-
283
/* We check if the started CPU is now at the correct level */
284
assert(info->target_el == arm_current_el(&target_cpu->env));
285
286
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
287
index XXXXXXX..XXXXXXX 100644
288
--- a/target/arm/cpu.c
289
+++ b/target/arm/cpu.c
290
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
291
}
292
}
293
294
+void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
295
+{
296
+ ARMCPU *cpu = ARM_CPU(cpustate);
297
+ CPUARMState *env = &cpu->env;
298
+ bool have_el3 = arm_feature(env, ARM_FEATURE_EL3);
299
+ bool have_el2 = arm_feature(env, ARM_FEATURE_EL2);
300
+
301
+ /*
302
+ * Check we have the EL we're aiming for. If that is the
303
+ * highest implemented EL, then cpu_reset has already done
304
+ * all the work.
305
+ */
306
+ switch (target_el) {
307
+ case 3:
308
+ assert(have_el3);
309
+ return;
310
+ case 2:
311
+ assert(have_el2);
312
+ if (!have_el3) {
313
+ return;
314
+ }
315
+ break;
316
+ case 1:
317
+ if (!have_el3 && !have_el2) {
318
+ return;
319
+ }
320
+ break;
321
+ default:
322
+ g_assert_not_reached();
323
+ }
324
+
325
+ if (have_el3) {
326
+ /*
327
+ * Set the EL3 state so code can run at EL2. This should match
328
+ * the requirements set by Linux in its booting spec.
329
+ */
330
+ if (env->aarch64) {
331
+ env->cp15.scr_el3 |= SCR_RW;
332
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
333
+ env->cp15.scr_el3 |= SCR_API | SCR_APK;
334
+ }
335
+ if (cpu_isar_feature(aa64_mte, cpu)) {
336
+ env->cp15.scr_el3 |= SCR_ATA;
337
+ }
338
+ if (cpu_isar_feature(aa64_sve, cpu)) {
339
+ env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
340
+ env->vfp.zcr_el[3] = 0xf;
341
+ }
342
+ if (cpu_isar_feature(aa64_sme, cpu)) {
343
+ env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
344
+ env->cp15.scr_el3 |= SCR_ENTP2;
345
+ env->vfp.smcr_el[3] = 0xf;
346
+ }
347
+ if (cpu_isar_feature(aa64_hcx, cpu)) {
348
+ env->cp15.scr_el3 |= SCR_HXEN;
349
+ }
350
+ if (cpu_isar_feature(aa64_fgt, cpu)) {
351
+ env->cp15.scr_el3 |= SCR_FGTEN;
352
+ }
353
+ }
354
+
355
+ if (target_el == 2) {
356
+ /* If the guest is at EL2 then Linux expects the HVC insn to work */
357
+ env->cp15.scr_el3 |= SCR_HCE;
358
+ }
359
+
360
+ /* Put CPU into non-secure state */
361
+ env->cp15.scr_el3 |= SCR_NS;
362
+ /* Set NSACR.{CP11,CP10} so NS can access the FPU */
363
+ env->cp15.nsacr |= 3 << 10;
364
+ }
365
+
366
+ if (have_el2 && target_el < 2) {
367
+ /* Set EL2 state so code can run at EL1. */
368
+ if (env->aarch64) {
369
+ env->cp15.hcr_el2 |= HCR_RW;
370
+ }
371
+ }
372
+
373
+ /* Set the CPU to the desired state */
374
+ if (env->aarch64) {
375
+ env->pstate = aarch64_pstate_mode(target_el, true);
376
+ } else {
377
+ static const uint32_t mode_for_el[] = {
378
+ 0,
379
+ ARM_CPU_MODE_SVC,
380
+ ARM_CPU_MODE_HYP,
381
+ ARM_CPU_MODE_SVC,
382
+ };
383
+
384
+ cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw);
385
+ }
386
+}
387
+
388
+
389
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
390
391
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
392
--
393
2.34.1
diff view generated by jsdifflib
New patch
[PULL 23/24] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero
1
From: Chris Rauer <crauer@google.com>
1
2
3
The counter register is only 24-bits and counts down. If the timer is
4
running but the qtimer to reset it hasn't fired off yet, there is a chance
5
the regster read can return an invalid result.
6
7
Signed-off-by: Chris Rauer <crauer@google.com>
8
Message-id: 20230922181411.2697135-1-crauer@google.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/timer/npcm7xx_timer.c | 3 +++
13
1 file changed, 3 insertions(+)
14
15
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/timer/npcm7xx_timer.c
18
+++ b/hw/timer/npcm7xx_timer.c
19
@@ -XXX,XX +XXX,XX @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
20
/* Convert a time interval in nanoseconds to a timer cycle count. */
21
static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
22
{
23
+ if (ns < 0) {
24
+ return 0;
25
+ }
26
return clock_ns_to_ticks(t->ctrl->clock, ns) /
27
npcm7xx_tcsr_prescaler(t->tcsr);
28
}
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/24] contrib/elf2dmp: Use g_malloc(), g_new() and g_free()
1
From: Suraj Shirvankar <surajshirvankar@gmail.com>
1
2
3
QEMU coding style uses the glib memory allocation APIs, not
4
the raw libc malloc/free. Switch the allocation and free
5
calls in elf2dmp to use these functions (dropping the now-unneeded
6
checks for failure).
7
8
Signed-off-by: Suraj Shirvankar <surajshirvankar@gmail.com>
9
Message-id: 169753938460.23804.11418813007617535750-1@git.sr.ht
10
[PMM: also remove NULL checks from g_malloc() calls;
11
beef up commit message]
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
contrib/elf2dmp/addrspace.c | 7 ++-----
16
contrib/elf2dmp/main.c | 9 +++------
17
contrib/elf2dmp/pdb.c | 19 ++++++++-----------
18
contrib/elf2dmp/qemu_elf.c | 7 ++-----
19
4 files changed, 15 insertions(+), 27 deletions(-)
20
21
diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/contrib/elf2dmp/addrspace.c
24
+++ b/contrib/elf2dmp/addrspace.c
25
@@ -XXX,XX +XXX,XX @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf)
26
}
27
}
28
29
- ps->block = malloc(sizeof(*ps->block) * ps->block_nr);
30
- if (!ps->block) {
31
- return 1;
32
- }
33
+ ps->block = g_new(struct pa_block, ps->block_nr);
34
35
for (i = 0; i < phdr_nr; i++) {
36
if (phdr[i].p_type == PT_LOAD) {
37
@@ -XXX,XX +XXX,XX @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf)
38
void pa_space_destroy(struct pa_space *ps)
39
{
40
ps->block_nr = 0;
41
- free(ps->block);
42
+ g_free(ps->block);
43
}
44
45
void va_space_set_dtb(struct va_space *vs, uint64_t dtb)
46
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/contrib/elf2dmp/main.c
49
+++ b/contrib/elf2dmp/main.c
50
@@ -XXX,XX +XXX,XX @@ static KDDEBUGGER_DATA64 *get_kdbg(uint64_t KernBase, struct pdb_reader *pdb,
51
}
52
}
53
54
- kdbg = malloc(kdbg_hdr.Size);
55
- if (!kdbg) {
56
- return NULL;
57
- }
58
+ kdbg = g_malloc(kdbg_hdr.Size);
59
60
if (va_space_rw(vs, KdDebuggerDataBlock, kdbg, kdbg_hdr.Size, 0)) {
61
eprintf("Failed to extract entire KDBG\n");
62
- free(kdbg);
63
+ g_free(kdbg);
64
return NULL;
65
}
66
67
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
68
}
69
70
out_kdbg:
71
- free(kdbg);
72
+ g_free(kdbg);
73
out_pdb:
74
pdb_exit(&pdb);
75
out_pdb_file:
76
diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/contrib/elf2dmp/pdb.c
79
+++ b/contrib/elf2dmp/pdb.c
80
@@ -XXX,XX +XXX,XX @@ uint64_t pdb_resolve(uint64_t img_base, struct pdb_reader *r, const char *name)
81
82
static void pdb_reader_ds_exit(struct pdb_reader *r)
83
{
84
- free(r->ds.toc);
85
+ g_free(r->ds.toc);
86
}
87
88
static void pdb_exit_symbols(struct pdb_reader *r)
89
{
90
- free(r->modimage);
91
- free(r->symbols);
92
+ g_free(r->modimage);
93
+ g_free(r->symbols);
94
}
95
96
static void pdb_exit_segments(struct pdb_reader *r)
97
{
98
- free(r->segs);
99
+ g_free(r->segs);
100
}
101
102
static void *pdb_ds_read(const PDB_DS_HEADER *header,
103
@@ -XXX,XX +XXX,XX @@ static void *pdb_ds_read(const PDB_DS_HEADER *header,
104
105
nBlocks = (size + header->block_size - 1) / header->block_size;
106
107
- buffer = malloc(nBlocks * header->block_size);
108
- if (!buffer) {
109
- return NULL;
110
- }
111
+ buffer = g_malloc(nBlocks * header->block_size);
112
113
for (i = 0; i < nBlocks; i++) {
114
memcpy(buffer + i * header->block_size, (const char *)header +
115
@@ -XXX,XX +XXX,XX @@ static int pdb_init_symbols(struct pdb_reader *r)
116
return 0;
117
118
out_symbols:
119
- free(symbols);
120
+ g_free(symbols);
121
122
return err;
123
}
124
@@ -XXX,XX +XXX,XX @@ static int pdb_reader_init(struct pdb_reader *r, void *data)
125
out_sym:
126
pdb_exit_symbols(r);
127
out_root:
128
- free(r->ds.root);
129
+ g_free(r->ds.root);
130
out_ds:
131
pdb_reader_ds_exit(r);
132
133
@@ -XXX,XX +XXX,XX @@ static void pdb_reader_exit(struct pdb_reader *r)
134
{
135
pdb_exit_segments(r);
136
pdb_exit_symbols(r);
137
- free(r->ds.root);
138
+ g_free(r->ds.root);
139
pdb_reader_ds_exit(r);
140
}
141
142
diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/elf2dmp/qemu_elf.c
143
index XXXXXXX..XXXXXXX 100644
144
--- a/contrib/elf2dmp/qemu_elf.c
145
+++ b/contrib/elf2dmp/qemu_elf.c
146
@@ -XXX,XX +XXX,XX @@ static int init_states(QEMU_Elf *qe)
147
148
printf("%zu CPU states has been found\n", cpu_nr);
149
150
- qe->state = malloc(sizeof(*qe->state) * cpu_nr);
151
- if (!qe->state) {
152
- return 1;
153
- }
154
+ qe->state = g_new(QEMUCPUState*, cpu_nr);
155
156
cpu_nr = 0;
157
158
@@ -XXX,XX +XXX,XX @@ static int init_states(QEMU_Elf *qe)
159
160
static void exit_states(QEMU_Elf *qe)
161
{
162
- free(qe->state);
163
+ g_free(qe->state);
164
}
165
166
static bool check_ehdr(QEMU_Elf *qe)
167
--
168
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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