1
v2: dropped a couple of cadence_gem changes to ID regs that
1
target-arm queue: just bugfixes, mostly mine.
2
caused new clang sanitizer warnings.
3
2
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
6
The following changes since commit 885fc169f09f5915ce037263d20a59eb226d473d:
7
7
8
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
8
Merge tag 'pull-riscv-to-apply-20230723-3' of https://github.com/alistair23/qemu into staging (2023-07-24 11:34:35 +0100)
9
9
10
are available in the Git repository at:
10
are available in the Git repository at:
11
11
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230725
13
13
14
for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
14
for you to fetch changes up to 78cc90346ec680a7f1bb9f138bf7c9654cf526d5:
15
15
16
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
16
tests/decode: Suppress "error: " string for expected-failure tests (2023-07-25 10:56:52 +0100)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
20
* tests/decode: Suppress "error: " string for expected-failure tests
21
* target/arm: Fix aarch64_sve_change_el wrt EL0
21
* ui/curses: For curses display, recognize a few more control keys
22
* target/arm: Define fields of ISAR registers
22
* target/arm: Special case M-profile in debug_helper.c code
23
* target/arm: Align cortex-r5 id_isar0
23
* scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
24
* target/arm: Fix cortex-a7 id_isar0
24
* hw/arm/smmu: Handle big-endian hosts correctly
25
* net/cadence_gem: Fix various bugs, add support for new
26
features that will be used by the Xilinx Versal board
27
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
28
* target/arm: Add the Cortex-A72
29
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
30
* target/arm: Mask PMOVSR writes based on supported counters
31
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
32
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
33
25
34
----------------------------------------------------------------
26
----------------------------------------------------------------
35
Aaron Lindsay (2):
27
Peter Maydell (4):
36
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
28
hw/arm/smmu: Handle big-endian hosts correctly
37
target/arm: Mask PMOVSR writes based on supported counters
29
scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
30
target/arm: Special case M-profile in debug_helper.c code
31
tests/decode: Suppress "error: " string for expected-failure tests
38
32
39
Edgar E. Iglesias (8):
33
Sean Estabrooks (1):
40
net: cadence_gem: Disable TSU feature bit
34
For curses display, recognize a few more control keys
41
net: cadence_gem: Use uint32_t for 32bit descriptor words
42
net: cadence_gem: Add macro with max number of descriptor words
43
net: cadence_gem: Add support for extended descriptors
44
net: cadence_gem: Add support for selecting the DMA MemoryRegion
45
net: cadence_gem: Implement support for 64bit descriptor addresses
46
target-arm: powerctl: Enable HVC when starting CPUs to EL2
47
target/arm: Add the Cortex-A72
48
35
49
Jerome Forissier (1):
36
ui/curses_keys.h | 6 ++++++
50
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
37
hw/arm/smmu-common.c | 3 +--
51
38
hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++--------
52
Peter Maydell (2):
39
target/arm/debug_helper.c | 18 ++++++++++++------
53
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
40
scripts/decodetree.py | 6 +++++-
54
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
41
scripts/git-submodule.sh | 2 +-
55
42
6 files changed, 56 insertions(+), 18 deletions(-)
56
Richard Henderson (4):
57
target/arm: Fix aarch64_sve_change_el wrt EL0
58
target/arm: Define fields of ISAR registers
59
target/arm: Align cortex-r5 id_isar0
60
target/arm: Fix cortex-a7 id_isar0
61
62
include/hw/net/cadence_gem.h | 7 +-
63
target/arm/cpu.h | 95 ++++++++++++++-
64
hw/arm/virt.c | 4 +
65
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
66
target/arm/arm-powerctl.c | 10 ++
67
target/arm/cpu.c | 7 +-
68
target/arm/cpu64.c | 66 +++++++++-
69
target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
71
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
72
10 files changed, 402 insertions(+), 70 deletions(-)
73
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
74
diff view generated by jsdifflib
New patch
1
The implementation of the SMMUv3 has multiple places where it reads a
2
data structure from the guest and directly operates on it without
3
doing a guest-to-host endianness conversion. Since all SMMU data
4
structures are little-endian, this means that the SMMU doesn't work
5
on a big-endian host. In particular, this causes the Avocado test
6
machine_aarch64_virt.py:Aarch64VirtMachine.test_alpine_virt_tcg_gic_max
7
to fail on an s390x host.
1
8
9
Add appropriate byte-swapping on reads and writes of guest in-memory
10
data structures so that the device works correctly on big-endian
11
hosts.
12
13
As part of this we constrain queue_read() to operate only on Cmd
14
structs and queue_write() on Evt structs, because in practice these
15
are the only data structures the two functions are used with, and we
16
need to know what the data structure is to be able to byte-swap its
17
parts correctly.
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Tested-by: Thomas Huth <thuth@redhat.com>
21
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
22
Reviewed-by: Eric Auger <eric.auger@redhat.com>
23
Message-id: 20230717132641.764660-1-peter.maydell@linaro.org
24
Cc: qemu-stable@nongnu.org
25
---
26
hw/arm/smmu-common.c | 3 +--
27
hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++--------
28
2 files changed, 32 insertions(+), 10 deletions(-)
29
30
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/smmu-common.c
33
+++ b/hw/arm/smmu-common.c
34
@@ -XXX,XX +XXX,XX @@ static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte,
35
dma_addr_t addr = baseaddr + index * sizeof(*pte);
36
37
/* TODO: guarantee 64-bit single-copy atomicity */
38
- ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte),
39
- MEMTXATTRS_UNSPECIFIED);
40
+ ret = ldq_le_dma(&address_space_memory, addr, pte, MEMTXATTRS_UNSPECIFIED);
41
42
if (ret != MEMTX_OK) {
43
info->type = SMMU_PTW_ERR_WALK_EABT;
44
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/smmuv3.c
47
+++ b/hw/arm/smmuv3.c
48
@@ -XXX,XX +XXX,XX @@ static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
49
trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn);
50
}
51
52
-static inline MemTxResult queue_read(SMMUQueue *q, void *data)
53
+static inline MemTxResult queue_read(SMMUQueue *q, Cmd *cmd)
54
{
55
dma_addr_t addr = Q_CONS_ENTRY(q);
56
+ MemTxResult ret;
57
+ int i;
58
59
- return dma_memory_read(&address_space_memory, addr, data, q->entry_size,
60
- MEMTXATTRS_UNSPECIFIED);
61
+ ret = dma_memory_read(&address_space_memory, addr, cmd, sizeof(Cmd),
62
+ MEMTXATTRS_UNSPECIFIED);
63
+ if (ret != MEMTX_OK) {
64
+ return ret;
65
+ }
66
+ for (i = 0; i < ARRAY_SIZE(cmd->word); i++) {
67
+ le32_to_cpus(&cmd->word[i]);
68
+ }
69
+ return ret;
70
}
71
72
-static MemTxResult queue_write(SMMUQueue *q, void *data)
73
+static MemTxResult queue_write(SMMUQueue *q, Evt *evt_in)
74
{
75
dma_addr_t addr = Q_PROD_ENTRY(q);
76
MemTxResult ret;
77
+ Evt evt = *evt_in;
78
+ int i;
79
80
- ret = dma_memory_write(&address_space_memory, addr, data, q->entry_size,
81
+ for (i = 0; i < ARRAY_SIZE(evt.word); i++) {
82
+ cpu_to_le32s(&evt.word[i]);
83
+ }
84
+ ret = dma_memory_write(&address_space_memory, addr, &evt, sizeof(Evt),
85
MEMTXATTRS_UNSPECIFIED);
86
if (ret != MEMTX_OK) {
87
return ret;
88
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
89
static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
90
SMMUEventInfo *event)
91
{
92
- int ret;
93
+ int ret, i;
94
95
trace_smmuv3_get_ste(addr);
96
/* TODO: guarantee 64-bit single-copy atomicity */
97
@@ -XXX,XX +XXX,XX @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
98
event->u.f_ste_fetch.addr = addr;
99
return -EINVAL;
100
}
101
+ for (i = 0; i < ARRAY_SIZE(buf->word); i++) {
102
+ le32_to_cpus(&buf->word[i]);
103
+ }
104
return 0;
105
106
}
107
@@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
108
CD *buf, SMMUEventInfo *event)
109
{
110
dma_addr_t addr = STE_CTXPTR(ste);
111
- int ret;
112
+ int ret, i;
113
114
trace_smmuv3_get_cd(addr);
115
/* TODO: guarantee 64-bit single-copy atomicity */
116
@@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
117
event->u.f_ste_fetch.addr = addr;
118
return -EINVAL;
119
}
120
+ for (i = 0; i < ARRAY_SIZE(buf->word); i++) {
121
+ le32_to_cpus(&buf->word[i]);
122
+ }
123
return 0;
124
}
125
126
@@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
127
return -EINVAL;
128
}
129
if (s->features & SMMU_FEATURE_2LVL_STE) {
130
- int l1_ste_offset, l2_ste_offset, max_l2_ste, span;
131
+ int l1_ste_offset, l2_ste_offset, max_l2_ste, span, i;
132
dma_addr_t l1ptr, l2ptr;
133
STEDesc l1std;
134
135
@@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
136
event->u.f_ste_fetch.addr = l1ptr;
137
return -EINVAL;
138
}
139
+ for (i = 0; i < ARRAY_SIZE(l1std.word); i++) {
140
+ le32_to_cpus(&l1std.word[i]);
141
+ }
142
143
span = L1STD_SPAN(&l1std);
144
145
--
146
2.34.1
147
148
diff view generated by jsdifflib
New patch
1
The POSIX definition of the 'read' utility requires that you
2
specify the variable name to set; omitting the name and
3
having it default to 'REPLY' is a bashism. If your system
4
sh is dash, then it will print an error message during build:
1
5
6
qemu/pc-bios/s390-ccw/../../scripts/git-submodule.sh: 106: read: arg count
7
8
Specify the variable name explicitly.
9
10
Fixes: fdb8fd8cb915647b ("git-submodule: allow partial update of .git-submodule-status")
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Message-id: 20230720153038.1587196-1-peter.maydell@linaro.org
15
---
16
scripts/git-submodule.sh | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
18
19
diff --git a/scripts/git-submodule.sh b/scripts/git-submodule.sh
20
index XXXXXXX..XXXXXXX 100755
21
--- a/scripts/git-submodule.sh
22
+++ b/scripts/git-submodule.sh
23
@@ -XXX,XX +XXX,XX @@ update)
24
check_updated $module || echo Updated "$module"
25
done
26
27
- (while read -r; do
28
+ (while read -r REPLY; do
29
for module in $modules; do
30
case $REPLY in
31
*" $module "*) continue 2 ;;
32
--
33
2.34.1
34
35
diff view generated by jsdifflib
New patch
1
A lot of the code called from helper_exception_bkpt_insn() is written
2
assuming A-profile, but we will also call this helper on M-profile
3
CPUs when they execute a BKPT insn. This used to work by accident,
4
but recent changes mean that we will hit an assert when some of this
5
code calls down into lower level functions that end up calling
6
arm_security_space_below_el3(), arm_el_is_aa64(), and other functions
7
that now explicitly assert that the guest CPU is not M-profile.
1
8
9
Handle M-profile directly to avoid the assertions:
10
* in arm_debug_target_el(), M-profile debug exceptions always
11
go to EL1
12
* in arm_debug_exception_fsr(), M-profile always uses the short
13
format FSR (compare commit d7fe699be54b2, though in this case
14
the code in arm_v7m_cpu_do_interrupt() does not need to
15
look at the FSR value at all)
16
17
Cc: qemu-stable@nongnu.org
18
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1775
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20230721143239.1753066-1-peter.maydell@linaro.org
22
---
23
target/arm/debug_helper.c | 18 ++++++++++++------
24
1 file changed, 12 insertions(+), 6 deletions(-)
25
26
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/debug_helper.c
29
+++ b/target/arm/debug_helper.c
30
@@ -XXX,XX +XXX,XX @@ static int arm_debug_target_el(CPUARMState *env)
31
bool secure = arm_is_secure(env);
32
bool route_to_el2 = false;
33
34
+ if (arm_feature(env, ARM_FEATURE_M)) {
35
+ return 1;
36
+ }
37
+
38
if (arm_is_el2_enabled(env)) {
39
route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
40
env->cp15.mdcr_el2 & MDCR_TDE;
41
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
42
{
43
ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
44
int target_el = arm_debug_target_el(env);
45
- bool using_lpae = false;
46
+ bool using_lpae;
47
48
- if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
49
+ if (arm_feature(env, ARM_FEATURE_M)) {
50
+ using_lpae = false;
51
+ } else if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
52
using_lpae = true;
53
} else if (arm_feature(env, ARM_FEATURE_PMSA) &&
54
arm_feature(env, ARM_FEATURE_V8)) {
55
using_lpae = true;
56
+ } else if (arm_feature(env, ARM_FEATURE_LPAE) &&
57
+ (env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
58
+ using_lpae = true;
59
} else {
60
- if (arm_feature(env, ARM_FEATURE_LPAE) &&
61
- (env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
62
- using_lpae = true;
63
- }
64
+ using_lpae = false;
65
}
66
67
if (using_lpae) {
68
--
69
2.34.1
diff view generated by jsdifflib
New patch
1
From: Sean Estabrooks <sean.estabrooks@gmail.com>
1
2
3
The curses display handles most control-X keys, and translates
4
them into their corresponding keycode. Here we recognize
5
a few that are missing, Ctrl-@ (null), Ctrl-\ (backslash),
6
Ctrl-] (right bracket), Ctrl-^ (caret), Ctrl-_ (underscore).
7
8
Signed-off-by: Sean Estabrooks <sean.estabrooks@gmail.com>
9
Message-id: CAHyVn3Bh9CRgDuOmf7G7Ngwamu8d4cVozAcB2i4ymnnggBXNmg@mail.gmail.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
ui/curses_keys.h | 6 ++++++
14
1 file changed, 6 insertions(+)
15
16
diff --git a/ui/curses_keys.h b/ui/curses_keys.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/ui/curses_keys.h
19
+++ b/ui/curses_keys.h
20
@@ -XXX,XX +XXX,XX @@ static const int _curses2keycode[CURSES_CHARS] = {
21
['N' - '@'] = 49 | CNTRL, /* Control + n */
22
/* Control + m collides with the keycode for Enter */
23
24
+ ['@' - '@'] = 3 | CNTRL, /* Control + @ */
25
+ /* Control + [ collides with the keycode for Escape */
26
+ ['\\' - '@'] = 43 | CNTRL, /* Control + Backslash */
27
+ [']' - '@'] = 27 | CNTRL, /* Control + ] */
28
+ ['^' - '@'] = 7 | CNTRL, /* Control + ^ */
29
+ ['_' - '@'] = 12 | CNTRL, /* Control + Underscore */
30
};
31
32
static const int _curseskey2keycode[CURSES_KEYS] = {
33
--
34
2.34.1
diff view generated by jsdifflib
New patch
1
The "expected failure" tests for decodetree result in the
2
error messages from decodetree ending up in logs and in
3
V=1 output:
1
4
5
>>> MALLOC_PERTURB_=226 /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/pyvenv/bin/python3 /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/scripts/decodetree.py --output-null --test-for-error /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/../../tests/decode/err_argset1.decode
6
――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――― ✀ ――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――
7
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/../../tests/decode/err_argset1.decode:5: error: duplicate argument "a"
8
―――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――
9
1/44 qemu:decodetree / err_argset1 OK 0.05s
10
11
This then produces false positives when scanning the
12
logfiles for strings like "error: ".
13
14
For the expected-failure tests, make decodetree print
15
"detected:" instead of "error:".
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20230720131521.1325905-1-peter.maydell@linaro.org
21
---
22
scripts/decodetree.py | 6 +++++-
23
1 file changed, 5 insertions(+), 1 deletion(-)
24
25
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
26
index XXXXXXX..XXXXXXX 100644
27
--- a/scripts/decodetree.py
28
+++ b/scripts/decodetree.py
29
@@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args):
30
global output_file
31
global output_fd
32
33
+ # For the test suite expected-errors case, don't print the
34
+ # string "error: ", so they don't turn up as false positives
35
+ # if you grep the meson logs for strings like that.
36
+ end = 'error: ' if not testforerror else 'detected: '
37
prefix = ''
38
if file:
39
prefix += f'{file}:'
40
@@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args):
41
prefix += f'{lineno}:'
42
if prefix:
43
prefix += ' '
44
- print(prefix, end='error: ', file=sys.stderr)
45
+ print(prefix, end=end, file=sys.stderr)
46
print(*args, file=sys.stderr)
47
48
if output_file and output_fd:
49
--
50
2.34.1
51
52
diff view generated by jsdifflib