1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a: |
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2 | caused new clang sanitizer warnings. | ||
3 | 2 | ||
4 | -- PMM | 3 | Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000) |
5 | |||
6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | ||
7 | |||
8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | ||
9 | 4 | ||
10 | are available in the Git repository at: | 5 | are available in the Git repository at: |
11 | 6 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328 |
13 | 8 | ||
14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 9 | for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a: |
15 | 10 | ||
16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 11 | target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100) |
17 | 12 | ||
18 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
19 | target-arm queue: | 14 | target-arm queue: |
20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 15 | * fix part of the "TCG-disabled builds are broken" issue |
21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | ||
22 | * target/arm: Define fields of ISAR registers | ||
23 | * target/arm: Align cortex-r5 id_isar0 | ||
24 | * target/arm: Fix cortex-a7 id_isar0 | ||
25 | * net/cadence_gem: Fix various bugs, add support for new | ||
26 | features that will be used by the Xilinx Versal board | ||
27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
28 | * target/arm: Add the Cortex-A72 | ||
29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | ||
30 | * target/arm: Mask PMOVSR writes based on supported counters | ||
31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
33 | 16 | ||
34 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
35 | Aaron Lindsay (2): | 18 | Philippe Mathieu-Daudé (1): |
36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 19 | target/arm/gdbstub: Only advertise M-profile features if TCG available |
37 | target/arm: Mask PMOVSR writes based on supported counters | ||
38 | 20 | ||
39 | Edgar E. Iglesias (8): | 21 | target/arm/gdbstub.c | 5 +++-- |
40 | net: cadence_gem: Disable TSU feature bit | 22 | 1 file changed, 3 insertions(+), 2 deletions(-) |
41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | ||
42 | net: cadence_gem: Add macro with max number of descriptor words | ||
43 | net: cadence_gem: Add support for extended descriptors | ||
44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
45 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
47 | target/arm: Add the Cortex-A72 | ||
48 | 23 | ||
49 | Jerome Forissier (1): | ||
50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | ||
51 | |||
52 | Peter Maydell (2): | ||
53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
55 | |||
56 | Richard Henderson (4): | ||
57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | ||
58 | target/arm: Define fields of ISAR registers | ||
59 | target/arm: Align cortex-r5 id_isar0 | ||
60 | target/arm: Fix cortex-a7 id_isar0 | ||
61 | |||
62 | include/hw/net/cadence_gem.h | 7 +- | ||
63 | target/arm/cpu.h | 95 ++++++++++++++- | ||
64 | hw/arm/virt.c | 4 + | ||
65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | ||
66 | target/arm/arm-powerctl.c | 10 ++ | ||
67 | target/arm/cpu.c | 7 +- | ||
68 | target/arm/cpu64.c | 66 +++++++++- | ||
69 | target/arm/helper.c | 27 +++-- | ||
70 | target/arm/op_helper.c | 6 +- | ||
71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | ||
72 | 10 files changed, 402 insertions(+), 70 deletions(-) | ||
73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | ||
74 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
1 | 2 | ||
3 | Cortex-M profile is only emulable from TCG accelerator. Restrict | ||
4 | the GDBstub features to its availability in order to avoid a link | ||
5 | error when TCG is not enabled: | ||
6 | |||
7 | Undefined symbols for architecture arm64: | ||
8 | "_arm_v7m_get_sp_ptr", referenced from: | ||
9 | _m_sysreg_get in target_arm_gdbstub.c.o | ||
10 | "_arm_v7m_mrs_control", referenced from: | ||
11 | _arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o | ||
12 | ld: symbol(s) not found for architecture arm64 | ||
13 | clang: error: linker command failed with exit code 1 (use -v to see invocation) | ||
14 | |||
15 | Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext") | ||
16 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
19 | Message-id: 20230322142902.69511-3-philmd@linaro.org | ||
20 | [PMM: add #include since I cherry-picked this patch from the series] | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | --- | ||
23 | target/arm/gdbstub.c | 5 +++-- | ||
24 | 1 file changed, 3 insertions(+), 2 deletions(-) | ||
25 | |||
26 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/gdbstub.c | ||
29 | +++ b/target/arm/gdbstub.c | ||
30 | @@ -XXX,XX +XXX,XX @@ | ||
31 | #include "cpu.h" | ||
32 | #include "exec/gdbstub.h" | ||
33 | #include "gdbstub/helpers.h" | ||
34 | +#include "sysemu/tcg.h" | ||
35 | #include "internals.h" | ||
36 | #include "cpregs.h" | ||
37 | |||
38 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
39 | 2, "arm-vfp-sysregs.xml", 0); | ||
40 | } | ||
41 | } | ||
42 | - if (cpu_isar_feature(aa32_mve, cpu)) { | ||
43 | + if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) { | ||
44 | gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, | ||
45 | 1, "arm-m-profile-mve.xml", 0); | ||
46 | } | ||
47 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
48 | arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), | ||
49 | "system-registers.xml", 0); | ||
50 | |||
51 | - if (arm_feature(env, ARM_FEATURE_M)) { | ||
52 | + if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { | ||
53 | gdb_register_coprocessor(cs, | ||
54 | arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, | ||
55 | arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), | ||
56 | -- | ||
57 | 2.34.1 | ||
58 | |||
59 | diff view generated by jsdifflib |