[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 0/1] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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Just one bugfix patch for this rc:
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caused new clang sanitizer warnings.
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-- PMM
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The following changes since commit ca5f3d4df1b47d7f66a109cdb504e83dfd7ec433:
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge tag 'pull-la-20220808' of https://gitlab.com/rth7680/qemu into staging (2022-08-08 19:51:12 -0700)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220809
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to c7f26ded6d5065e4116f630f6a490b55f6c5f58e:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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icount: Take iothread lock when running QEMU timers (2022-08-09 10:55:14 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* icount: Take iothread lock when running QEMU timers
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* target/arm: Define fields of ISAR registers
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* target/arm: Align cortex-r5 id_isar0
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* target/arm: Fix cortex-a7 id_isar0
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* net/cadence_gem: Fix various bugs, add support for new
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features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Peter Maydell (1):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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icount: Take iothread lock when running QEMU timers
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target/arm: Mask PMOVSR writes based on supported counters
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Edgar E. Iglesias (8):
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accel/tcg/tcg-accel-ops-icount.c | 6 ++++++
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net: cadence_gem: Disable TSU feature bit
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1 file changed, 6 insertions(+)
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Jerome Forissier (1):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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Peter Maydell (2):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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Richard Henderson (4):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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diff view generated by jsdifflib
New patch
[PULL 1/1] icount: Take iothread lock when running QEMU timers
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The function icount_prepare_for_run() is called with the iothread
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unlocked, but it can call icount_notify_aio_contexts() which will
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run qemu timer handlers. Those are supposed to be run only with
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the iothread lock held, so take the lock while we do that.
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Since icount mode runs everything on a single thread anyway,
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not holding the lock is likely mostly not going to introduce
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races, but it can cause us to trip over assertions that we
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do hold the lock, such as the one reported in issue 1130.
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1130
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Tested-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
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Message-id: 20220801164527.3134765-1-peter.maydell@linaro.org
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---
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accel/tcg/tcg-accel-ops-icount.c | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c
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index XXXXXXX..XXXXXXX 100644
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--- a/accel/tcg/tcg-accel-ops-icount.c
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+++ b/accel/tcg/tcg-accel-ops-icount.c
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@@ -XXX,XX +XXX,XX @@ void icount_prepare_for_run(CPUState *cpu)
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replay_mutex_lock();
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if (cpu->icount_budget == 0) {
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+ /*
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+ * We're called without the iothread lock, so must take it while
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+ * we're calling timer handlers.
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+ */
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+ qemu_mutex_lock_iothread();
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icount_notify_aio_contexts();
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+ qemu_mutex_unlock_iothread();
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}
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}
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--
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2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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