[Qemu-devel] [PULL 00/17] target-arm queue
[PULL v2 00/61] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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This pullreq is (1) my GICv4 patches (2) most of the first third of RTH's
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caused new clang sanitizer warnings.
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cleanup patchset (3) one patch fixing an smmuv3 bug...
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v2 changes: fix build failure on aarch64 hosts by moving the
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gicv3_add_its() and gicv3_foreach_its() functions to
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arm_gicv3_its_common.h.
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thanks
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-- PMM
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-- PMM
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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The following changes since commit a74782936dc6e979ce371dabda4b1c05624ea87f:
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Merge tag 'pull-migration-20220421a' of https://gitlab.com/dagrh/qemu into staging (2022-04-21 18:48:18 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220422-1
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to c3ca7d56c4790c2223122f7e84b71161cd36dbce:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() (2022-04-22 14:44:55 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* Implement GICv4 emulation
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* Some cleanup patches in target/arm
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* target/arm: Define fields of ISAR registers
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* hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate()
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* target/arm: Align cortex-r5 id_isar0
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* target/arm: Fix cortex-a7 id_isar0
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* net/cadence_gem: Fix various bugs, add support for new
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features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Peter Maydell (41):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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hw/intc/arm_gicv3_its: Add missing blank line
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target/arm: Mask PMOVSR writes based on supported counters
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hw/intc/arm_gicv3: Sanity-check num-cpu property
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hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count
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hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers
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target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2
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hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?"
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hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4
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hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI
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hw/intc/arm_gicv3_its: Implement VMAPP
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hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE
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hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid"
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hw/intc/arm_gicv3_its: Factor out CTE lookup sequence
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hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code
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hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()
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hw/intc/arm_gicv3: Keep pointers to every connected ITS
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hw/intc/arm_gicv3_its: Implement VMOVP
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hw/intc/arm_gicv3_its: Implement VSYNC
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hw/intc/arm_gicv3_its: Implement INV command properly
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hw/intc/arm_gicv3_its: Implement INV for virtual interrupts
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hw/intc/arm_gicv3_its: Implement VMOVI
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hw/intc/arm_gicv3_its: Implement VINVALL
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hw/intc/arm_gicv3: Implement GICv4's new redistributor frame
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hw/intc/arm_gicv3: Implement new GICv4 redistributor registers
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hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()
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hw/intc/arm_gicv3_cpuif: Support vLPIs
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hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily
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hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic
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hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic
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hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes
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hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code
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hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()
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hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()
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hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling
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hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()
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hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()
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hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()
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hw/intc/arm_gicv3: Update ID and feature registers for GICv4
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hw/intc/arm_gicv3: Allow 'revision' property to be set to 4
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hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic()
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hw/arm/virt: Abstract out calculation of redistributor region capacity
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hw/arm/virt: Support TCG GICv4
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Edgar E. Iglesias (8):
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Richard Henderson (19):
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net: cadence_gem: Disable TSU feature bit
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target/arm: Update ISAR fields for ARMv8.8
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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target/arm: Update SCR_EL3 bits to ARMv8.8
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net: cadence_gem: Add macro with max number of descriptor words
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target/arm: Update SCTLR bits to ARMv9.2
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net: cadence_gem: Add support for extended descriptors
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target/arm: Change DisasContext.aarch64 to bool
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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target/arm: Change CPUArchState.aarch64 to bool
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target/arm: Extend store_cpu_offset to take field size
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Change DisasContext.thumb to bool
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target/arm: Add the Cortex-A72
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target/arm: Change CPUArchState.thumb to bool
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target/arm: Remove fpexc32_access
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target/arm: Split out set_btype_raw
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target/arm: Split out gen_rebuild_hflags
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target/arm: Simplify GEN_SHIFT in translate.c
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target/arm: Simplify gen_sar
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target/arm: Simplify aa32 DISAS_WFI
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target/arm: Use tcg_constant in translate-m-nocp.c
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target/arm: Use tcg_constant in translate-neon.c
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target/arm: Use smin/smax for do_sat_addsub_32
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target/arm: Use tcg_constant in translate-vfp.c
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target/arm: Use tcg_constant_i32 in translate.h
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Jerome Forissier (1):
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Xiang Chen (1):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate()
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Peter Maydell (2):
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docs/system/arm/virt.rst | 5 +-
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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hw/intc/gicv3_internal.h | 213 +++++++-
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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include/hw/arm/virt.h | 19 +-
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include/hw/intc/arm_gicv3_common.h | 13 +
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Richard Henderson (4):
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include/hw/intc/arm_gicv3_its_common.h | 19 +
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm/cpu.h | 59 ++-
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target/arm: Define fields of ISAR registers
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target/arm/translate-a32.h | 13 +-
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target/arm: Align cortex-r5 id_isar0
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target/arm/translate.h | 17 +-
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target/arm: Fix cortex-a7 id_isar0
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hw/arm/smmuv3.c | 2 +-
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hw/arm/virt.c | 102 +++-
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include/hw/net/cadence_gem.h | 7 +-
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hw/intc/arm_gicv3_common.c | 54 +-
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/intc/arm_gicv3_cpuif.c | 195 ++++++--
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hw/arm/virt.c | 4 +
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hw/intc/arm_gicv3_dist.c | 7 +-
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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hw/intc/arm_gicv3_its.c | 876 +++++++++++++++++++++++++++------
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target/arm/arm-powerctl.c | 10 ++
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hw/intc/arm_gicv3_its_kvm.c | 2 +
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target/arm/cpu.c | 7 +-
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hw/intc/arm_gicv3_kvm.c | 5 +
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target/arm/cpu64.c | 66 +++++++++-
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hw/intc/arm_gicv3_redist.c | 480 +++++++++++++++---
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target/arm/helper.c | 27 +++--
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linux-user/arm/cpu_loop.c | 2 +-
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target/arm/op_helper.c | 6 +-
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target/arm/cpu.c | 16 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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target/arm/helper-a64.c | 4 +-
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10 files changed, 402 insertions(+), 70 deletions(-)
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target/arm/helper.c | 19 +-
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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target/arm/hvf/hvf.c | 2 +-
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target/arm/m_helper.c | 6 +-
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target/arm/op_helper.c | 13 -
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target/arm/translate-a64.c | 50 +-
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target/arm/translate-m-nocp.c | 12 +-
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target/arm/translate-neon.c | 21 +-
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target/arm/translate-sve.c | 9 +-
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target/arm/translate-vfp.c | 76 +--
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target/arm/translate.c | 101 ++--
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hw/intc/trace-events | 18 +-
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31 files changed, 1890 insertions(+), 540 deletions(-)
diff view generated by jsdifflib

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