[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 0/2] target-arm queue
1
v2: dropped a couple of cadence_gem changes to ID regs that
1
Couple of trivial fixes for rc3...
2
caused new clang sanitizer warnings.
3
2
4
-- PMM
3
The following changes since commit 20661b75ea6093f5e59079d00a778a972d6732c5:
5
4
6
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
5
Merge tag 'pull-ppc-20220404' of https://github.com/legoater/qemu into staging (2022-04-04 15:48:55 +0100)
7
8
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
9
6
10
are available in the Git repository at:
7
are available in the Git repository at:
11
8
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220405
13
10
14
for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
11
for you to fetch changes up to 80b952bb694a90f7e530d407b01066894e64a443:
15
12
16
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
13
docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation. (2022-04-05 09:29:28 +0100)
17
14
18
----------------------------------------------------------------
15
----------------------------------------------------------------
19
target-arm queue:
16
target-arm queue:
20
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
17
* docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.
21
* target/arm: Fix aarch64_sve_change_el wrt EL0
18
* xlnx-bbram: hw/nvram: Fix uninitialized Error *
22
* target/arm: Define fields of ISAR registers
23
* target/arm: Align cortex-r5 id_isar0
24
* target/arm: Fix cortex-a7 id_isar0
25
* net/cadence_gem: Fix various bugs, add support for new
26
features that will be used by the Xilinx Versal board
27
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
28
* target/arm: Add the Cortex-A72
29
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
30
* target/arm: Mask PMOVSR writes based on supported counters
31
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
32
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
33
19
34
----------------------------------------------------------------
20
----------------------------------------------------------------
35
Aaron Lindsay (2):
21
Pavel Pisa (1):
36
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
22
docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.
37
target/arm: Mask PMOVSR writes based on supported counters
38
23
39
Edgar E. Iglesias (8):
24
Tong Ho (1):
40
net: cadence_gem: Disable TSU feature bit
25
xlnx-bbram: hw/nvram: Fix uninitialized Error *
41
net: cadence_gem: Use uint32_t for 32bit descriptor words
42
net: cadence_gem: Add macro with max number of descriptor words
43
net: cadence_gem: Add support for extended descriptors
44
net: cadence_gem: Add support for selecting the DMA MemoryRegion
45
net: cadence_gem: Implement support for 64bit descriptor addresses
46
target-arm: powerctl: Enable HVC when starting CPUs to EL2
47
target/arm: Add the Cortex-A72
48
26
49
Jerome Forissier (1):
27
docs/system/devices/can.rst | 6 +++---
50
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
28
hw/nvram/xlnx-bbram.c | 2 +-
51
29
2 files changed, 4 insertions(+), 4 deletions(-)
52
Peter Maydell (2):
53
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
54
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
55
56
Richard Henderson (4):
57
target/arm: Fix aarch64_sve_change_el wrt EL0
58
target/arm: Define fields of ISAR registers
59
target/arm: Align cortex-r5 id_isar0
60
target/arm: Fix cortex-a7 id_isar0
61
62
include/hw/net/cadence_gem.h | 7 +-
63
target/arm/cpu.h | 95 ++++++++++++++-
64
hw/arm/virt.c | 4 +
65
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
66
target/arm/arm-powerctl.c | 10 ++
67
target/arm/cpu.c | 7 +-
68
target/arm/cpu64.c | 66 +++++++++-
69
target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
71
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
72
10 files changed, 402 insertions(+), 70 deletions(-)
73
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
74
diff view generated by jsdifflib
New patch
[PULL 1/2] xlnx-bbram: hw/nvram: Fix uninitialized Error *
1
From: Tong Ho <tong.ho@xilinx.com>
1
2
3
This adds required initialization of Error * variable.
4
5
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
6
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
hw/nvram/xlnx-bbram.c | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
11
12
diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/nvram/xlnx-bbram.c
15
+++ b/hw/nvram/xlnx-bbram.c
16
@@ -XXX,XX +XXX,XX @@ static bool bbram_pgm_enabled(XlnxBBRam *s)
17
18
static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail)
19
{
20
- Error *errp;
21
+ Error *errp = NULL;
22
23
error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.",
24
blk_name(s->blk), detail);
25
--
26
2.25.1
diff view generated by jsdifflib
New patch
[PULL 2/2] docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.
1
From: Pavel Pisa <pisa@cmp.felk.cvut.cz>
1
2
3
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
4
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
5
Message-id: 20220402204523.32643-1-pisa@cmp.felk.cvut.cz
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
docs/system/devices/can.rst | 6 +++---
9
1 file changed, 3 insertions(+), 3 deletions(-)
10
11
diff --git a/docs/system/devices/can.rst b/docs/system/devices/can.rst
12
index XXXXXXX..XXXXXXX 100644
13
--- a/docs/system/devices/can.rst
14
+++ b/docs/system/devices/can.rst
15
@@ -XXX,XX +XXX,XX @@ Links to other resources
16
(5) `GNU/Linux, CAN and CANopen in Real-time Control Applications Slides from LinuxDays 2017 (include updated RTLWS 2015 content) <https://www.linuxdays.cz/2017/video/Pavel_Pisa-CAN_canopen.pdf>`_
17
(6) `Linux SocketCAN utilities <https://github.com/linux-can/can-utils>`_
18
(7) `CTU CAN FD project including core VHDL design, Linux driver, test utilities etc. <https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core>`_
19
- (8) `CTU CAN FD Core Datasheet Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/Progdokum.pdf>`_
20
- (9) `CTU CAN FD Core System Architecture Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/ctu_can_fd_architecture.pdf>`_
21
- (10) `CTU CAN FD Driver Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/driver_doc/ctucanfd-driver.html>`_
22
+ (8) `CTU CAN FD Core Datasheet Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf>`_
23
+ (9) `CTU CAN FD Core System Architecture Documentation <http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/System_Architecture.pdf>`_
24
+ (10) `CTU CAN FD Driver Documentation <https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/linux_driver/build/ctucanfd-driver.html>`_
25
(11) `Integration with PCIe interfacing for Intel/Altera Cyclone IV based board <https://gitlab.fel.cvut.cz/canbus/pcie-ctu_can_fd>`_
26
--
27
2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.