[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 0/6] target-arm queue
1
v2: dropped a couple of cadence_gem changes to ID regs that
1
Some small arm bug fixes for rc3.
2
caused new clang sanitizer warnings.
3
2
4
-- PMM
3
-- PMM
5
4
6
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
5
The following changes since commit 9b617b1bb4056e60b39be4c33be20c10928a6a5c:
7
6
8
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
7
Merge tag 'trivial-branch-for-7.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-04-01 10:23:27 +0100)
9
8
10
are available in the Git repository at:
9
are available in the Git repository at:
11
10
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220401
13
12
14
for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
13
for you to fetch changes up to a5b1e1ab662aa6dc42d5a913080fccbb8bf82e9b:
15
14
16
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
15
target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen (2022-04-01 15:35:49 +0100)
17
16
18
----------------------------------------------------------------
17
----------------------------------------------------------------
19
target-arm queue:
18
target-arm queue:
20
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
19
* target/arm: Fix some bugs in secure EL2 handling
21
* target/arm: Fix aarch64_sve_change_el wrt EL0
20
* target/arm: Fix assert when !HAVE_CMPXCHG128
22
* target/arm: Define fields of ISAR registers
21
* MAINTAINERS: change Fred Konrad's email address
23
* target/arm: Align cortex-r5 id_isar0
24
* target/arm: Fix cortex-a7 id_isar0
25
* net/cadence_gem: Fix various bugs, add support for new
26
features that will be used by the Xilinx Versal board
27
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
28
* target/arm: Add the Cortex-A72
29
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
30
* target/arm: Mask PMOVSR writes based on supported counters
31
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
32
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
33
22
34
----------------------------------------------------------------
23
----------------------------------------------------------------
35
Aaron Lindsay (2):
24
Frederic Konrad (1):
36
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
25
MAINTAINERS: change Fred Konrad's email address
37
target/arm: Mask PMOVSR writes based on supported counters
38
26
39
Edgar E. Iglesias (8):
27
Idan Horowitz (4):
40
net: cadence_gem: Disable TSU feature bit
28
target/arm: Fix MTE access checks for disabled SEL2
41
net: cadence_gem: Use uint32_t for 32bit descriptor words
29
target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
42
net: cadence_gem: Add macro with max number of descriptor words
30
target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk
43
net: cadence_gem: Add support for extended descriptors
31
target/arm: Determine final stage 2 output PA space based on original IPA
44
net: cadence_gem: Add support for selecting the DMA MemoryRegion
45
net: cadence_gem: Implement support for 64bit descriptor addresses
46
target-arm: powerctl: Enable HVC when starting CPUs to EL2
47
target/arm: Add the Cortex-A72
48
32
49
Jerome Forissier (1):
33
Peter Maydell (1):
50
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
34
target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen
51
35
52
Peter Maydell (2):
36
target/arm/internals.h | 2 +-
53
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
37
target/arm/helper.c | 18 +++++++++++++++---
54
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
38
target/arm/translate-a64.c | 7 ++++++-
55
39
.mailmap | 3 ++-
56
Richard Henderson (4):
40
MAINTAINERS | 2 +-
57
target/arm: Fix aarch64_sve_change_el wrt EL0
41
5 files changed, 25 insertions(+), 7 deletions(-)
58
target/arm: Define fields of ISAR registers
59
target/arm: Align cortex-r5 id_isar0
60
target/arm: Fix cortex-a7 id_isar0
61
62
include/hw/net/cadence_gem.h | 7 +-
63
target/arm/cpu.h | 95 ++++++++++++++-
64
hw/arm/virt.c | 4 +
65
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
66
target/arm/arm-powerctl.c | 10 ++
67
target/arm/cpu.c | 7 +-
68
target/arm/cpu64.c | 66 +++++++++-
69
target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
71
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
72
10 files changed, 402 insertions(+), 70 deletions(-)
73
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
74
diff view generated by jsdifflib
New patch
[PULL 1/6] target/arm: Fix MTE access checks for disabled SEL2
1
From: Idan Horowitz <idan.horowitz@gmail.com>
1
2
3
While not mentioned anywhere in the actual specification text, the
4
HCR_EL2.ATA bit is treated as '1' when EL2 is disabled at the current
5
security state. This can be observed in the psuedo-code implementation
6
of AArch64.AllocationTagAccessIsEnabled().
7
8
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220328173107.311267-1-idan.horowitz@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/internals.h | 2 +-
14
target/arm/helper.c | 2 +-
15
2 files changed, 2 insertions(+), 2 deletions(-)
16
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
20
+++ b/target/arm/internals.h
21
@@ -XXX,XX +XXX,XX @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
22
&& !(env->cp15.scr_el3 & SCR_ATA)) {
23
return false;
24
}
25
- if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
26
+ if (el < 2 && arm_is_el2_enabled(env)) {
27
uint64_t hcr = arm_hcr_el2_eff(env);
28
if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
29
return false;
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri,
35
{
36
int el = arm_current_el(env);
37
38
- if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
39
+ if (el < 2 && arm_is_el2_enabled(env)) {
40
uint64_t hcr = arm_hcr_el2_eff(env);
41
if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
42
return CP_ACCESS_TRAP_EL2;
43
--
44
2.25.1
diff view generated by jsdifflib
New patch
[PULL 2/6] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
1
From: Idan Horowitz <idan.horowitz@gmail.com>
1
2
3
As per the AArch64.SS2OutputPASpace() psuedo-code in the ARMv8 ARM when the
4
PA space of the IPA is non secure, the output PA space is secure if and only
5
if all of the bits VTCR.<NSW, NSA>, VSTCR.<SW, SA> are not set.
6
7
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220327093427.1548629-2-idan.horowitz@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
20
} else {
21
attrs->secure =
22
!((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW))
23
- || (env->cp15.vstcr_el2.raw_tcr & VSTCR_SA));
24
+ || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)));
25
}
26
}
27
return 0;
28
--
29
2.25.1
diff view generated by jsdifflib
New patch
[PULL 3/6] target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk
1
From: Idan Horowitz <idan.horowitz@gmail.com>
1
2
3
As per the AArch64.SS2InitialTTWState() psuedo-code in the ARMv8 ARM the
4
initial PA space used for stage 2 table walks is assigned based on the SW
5
and NSW bits of the VSTCR and VTCR registers.
6
This was already implemented for the recursive stage 2 page table walks
7
in S1_ptw_translate(), but was missing for the final stage 2 walk.
8
9
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220327093427.1548629-3-idan.horowitz@gmail.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/helper.c | 10 ++++++++++
15
1 file changed, 10 insertions(+)
16
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.c
20
+++ b/target/arm/helper.c
21
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
22
return ret;
23
}
24
25
+ if (arm_is_secure_below_el3(env)) {
26
+ if (attrs->secure) {
27
+ attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
28
+ } else {
29
+ attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
30
+ }
31
+ } else {
32
+ assert(!attrs->secure);
33
+ }
34
+
35
s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
36
is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
37
38
--
39
2.25.1
diff view generated by jsdifflib
New patch
[PULL 4/6] target/arm: Determine final stage 2 output PA space based on original IPA
1
From: Idan Horowitz <idan.horowitz@gmail.com>
1
2
3
As per the AArch64.S2Walk() pseudo-code in the ARMv8 ARM, the final
4
decision as to the output address's PA space based on the SA/SW/NSA/NSW
5
bits needs to take the input IPA's PA space into account, and not the
6
PA space of the result of the stage 2 walk itself.
7
8
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220327093427.1548629-4-idan.horowitz@gmail.com
11
[PMM: fixed commit message typo]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/helper.c | 8 +++++---
15
1 file changed, 5 insertions(+), 3 deletions(-)
16
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.c
20
+++ b/target/arm/helper.c
21
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
22
hwaddr ipa;
23
int s2_prot;
24
int ret;
25
+ bool ipa_secure;
26
ARMCacheAttrs cacheattrs2 = {};
27
ARMMMUIdx s2_mmu_idx;
28
bool is_el0;
29
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
30
return ret;
31
}
32
33
+ ipa_secure = attrs->secure;
34
if (arm_is_secure_below_el3(env)) {
35
- if (attrs->secure) {
36
+ if (ipa_secure) {
37
attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW);
38
} else {
39
attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW);
40
}
41
} else {
42
- assert(!attrs->secure);
43
+ assert(!ipa_secure);
44
}
45
46
s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
47
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
48
49
/* Check if IPA translates to secure or non-secure PA space. */
50
if (arm_is_secure_below_el3(env)) {
51
- if (attrs->secure) {
52
+ if (ipa_secure) {
53
attrs->secure =
54
!(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW));
55
} else {
56
--
57
2.25.1
diff view generated by jsdifflib
New patch
[PULL 5/6] MAINTAINERS: change Fred Konrad's email address
1
From: Frederic Konrad <konrad@adacore.com>
1
2
3
frederic.konrad@adacore.com and konrad@adacore.com will stop working starting
4
2022-04-01.
5
6
Use my personal email instead.
7
8
Signed-off-by: Frederic Konrad <frederic.konrad@adacore.com>
9
Reviewed-by: Fabien Chouteau <chouteau@adacore.com <clg@kaod.org>>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 1648643217-15811-1-git-send-email-frederic.konrad@adacore.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
.mailmap | 3 ++-
15
MAINTAINERS | 2 +-
16
2 files changed, 3 insertions(+), 2 deletions(-)
17
18
diff --git a/.mailmap b/.mailmap
19
index XXXXXXX..XXXXXXX 100644
20
--- a/.mailmap
21
+++ b/.mailmap
22
@@ -XXX,XX +XXX,XX @@ Alexander Graf <agraf@csgraf.de> <agraf@suse.de>
23
Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
24
Christian Borntraeger <borntraeger@linux.ibm.com> <borntraeger@de.ibm.com>
25
Filip Bozuta <filip.bozuta@syrmia.com> <filip.bozuta@rt-rk.com.com>
26
-Frederic Konrad <konrad@adacore.com> <fred.konrad@greensocs.com>
27
+Frederic Konrad <konrad.frederic@yahoo.fr> <fred.konrad@greensocs.com>
28
+Frederic Konrad <konrad.frederic@yahoo.fr> <konrad@adacore.com>
29
Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
30
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
31
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
32
diff --git a/MAINTAINERS b/MAINTAINERS
33
index XXXXXXX..XXXXXXX 100644
34
--- a/MAINTAINERS
35
+++ b/MAINTAINERS
36
@@ -XXX,XX +XXX,XX @@ F: include/hw/rtc/sun4v-rtc.h
37
38
Leon3
39
M: Fabien Chouteau <chouteau@adacore.com>
40
-M: KONRAD Frederic <frederic.konrad@adacore.com>
41
+M: Frederic Konrad <konrad.frederic@yahoo.fr>
42
S: Maintained
43
F: hw/sparc/leon3.c
44
F: hw/*/grlib*
45
--
46
2.25.1
47
48
diff view generated by jsdifflib
New patch
[PULL 6/6] target/arm: Don't use DISAS_NORETURN in STXP !HAVE_CMPXCHG128 codegen
1
In gen_store_exclusive(), if the host does not have a cmpxchg128
2
primitive then we generate bad code for STXP for storing two 64-bit
3
values. We generate a call to the exit_atomic helper, which never
4
returns, and set is_jmp to DISAS_NORETURN. However, this is
5
forgetting that we have already emitted a brcond that jumps over this
6
call for the case where we don't hold the exclusive. The effect is
7
that we don't generate any code to end the TB for the
8
exclusive-not-held execution path, which falls into the "exit with
9
TB_EXIT_REQUESTED" code that gen_tb_end() emits. This then causes an
10
assert at runtime when cpu_loop_exec_tb() sees an EXIT_REQUESTED TB
11
return that wasn't for an interrupt or icount.
1
12
13
In particular, you can hit this case when using the clang sanitizers
14
and trying to run the xlnx-versal-virt acceptance test in 'make
15
check-acceptance'. This bug was masked until commit 848126d11e93ff
16
("meson: move int128 checks from configure") because we used to set
17
CONFIG_CMPXCHG128=1 and avoid the buggy codepath, but after that we
18
do not.
19
20
Fix the bug by not setting is_jmp. The code after the exit_atomic
21
call up to the fail_label is dead, but TCG is smart enough to
22
eliminate it. We do need to set 'tmp' to some valid value, though
23
(in the same way the exit_atomic-using code in tcg/tcg-op.c does).
24
25
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/953
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Message-id: 20220331150858.96348-1-peter.maydell@linaro.org
29
---
30
target/arm/translate-a64.c | 7 ++++++-
31
1 file changed, 6 insertions(+), 1 deletion(-)
32
33
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate-a64.c
36
+++ b/target/arm/translate-a64.c
37
@@ -XXX,XX +XXX,XX @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
38
} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
39
if (!HAVE_CMPXCHG128) {
40
gen_helper_exit_atomic(cpu_env);
41
- s->base.is_jmp = DISAS_NORETURN;
42
+ /*
43
+ * Produce a result so we have a well-formed opcode
44
+ * stream when the following (dead) code uses 'tmp'.
45
+ * TCG will remove the dead ops for us.
46
+ */
47
+ tcg_gen_movi_i64(tmp, 0);
48
} else if (s->be_data == MO_LE) {
49
gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env,
50
cpu_exclusive_addr,
51
--
52
2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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