[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 0/1] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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Apologies for sending two pullreqs today; Eric's patch came in a
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caused new clang sanitizer warnings.
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few hours after I sent the first one but it's definitely a
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release-critical fix.
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-- PMM
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-- PMM
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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The following changes since commit 89d2f9e4c63799f7f03e9180c63b7dc45fc2a04a:
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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Merge tag 'pull-target-arm-20211122' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2021-11-22 16:35:54 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122-1
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to 33a0c404fb90a3fa8eea6ebf5c535fc7bc0b9912:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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hw/intc/arm_gicv3_its: Revert version increments in vmstate_its (2021-11-22 18:17:19 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* drop spurious bump of ITS vmstate version fields
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* target/arm: Define fields of ISAR registers
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* target/arm: Align cortex-r5 id_isar0
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* target/arm: Fix cortex-a7 id_isar0
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* net/cadence_gem: Fix various bugs, add support for new
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features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Eric Auger (1):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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hw/intc/arm_gicv3_its: Revert version increments in vmstate_its
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target/arm: Mask PMOVSR writes based on supported counters
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Edgar E. Iglesias (8):
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hw/intc/arm_gicv3_its_common.c | 2 --
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net: cadence_gem: Disable TSU feature bit
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1 file changed, 2 deletions(-)
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Jerome Forissier (1):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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Peter Maydell (2):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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Richard Henderson (4):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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diff view generated by jsdifflib
New patch
[PULL 1/1] hw/intc/arm_gicv3_its: Revert version increments in vmstate_its
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From: Eric Auger <eric.auger@redhat.com>
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Commit 18f6290a6a ("hw/intc: GICv3 ITS initial framework")
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incremented version_id and minimum_version_id fields of
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VMStateDescription vmstate_its. This breaks the migration between
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6.2 and 6.1 with the following message:
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qemu-system-aarch64: savevm: unsupported version 1 for 'arm_gicv3_its' v0
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qemu-system-aarch64: load of migration failed: Invalid argument
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Revert that change.
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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Message-id: 20211122171020.1195483-1-eric.auger@redhat.com
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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hw/intc/arm_gicv3_its_common.c | 2 --
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1 file changed, 2 deletions(-)
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diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/intc/arm_gicv3_its_common.c
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+++ b/hw/intc/arm_gicv3_its_common.c
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@@ -XXX,XX +XXX,XX @@ static int gicv3_its_post_load(void *opaque, int version_id)
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static const VMStateDescription vmstate_its = {
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.name = "arm_gicv3_its",
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- .version_id = 1,
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- .minimum_version_id = 1,
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.pre_save = gicv3_its_pre_save,
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.post_load = gicv3_its_post_load,
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.priority = MIG_PRI_GICV3_ITS,
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--
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2.25.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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