[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 0/1] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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Just one patch for rc2, a revert.
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caused new clang sanitizer warnings.
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-- PMM
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-- PMM
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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The following changes since commit 49aaac3548bc5a4632a14de939d5312b28dc1ba2:
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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Merge tag 'linux-user-for-6.2-pull-request' of git://github.com/vivier/qemu into staging (2021-11-22 10:33:13 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211122
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to 4825eaae4fdd56fba0febdfbdd7bf9684ae3ee0d:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" (2021-11-22 13:41:48 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* revert SMCCC/PSCI change, as it regresses some usecases for some boards
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* target/arm: Define fields of ISAR registers
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* target/arm: Align cortex-r5 id_isar0
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* target/arm: Fix cortex-a7 id_isar0
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* net/cadence_gem: Fix various bugs, add support for new
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features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Peter Maydell (1):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"
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target/arm: Mask PMOVSR writes based on supported counters
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Edgar E. Iglesias (8):
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target/arm/psci.c | 35 +++++++++++++++++++++++++++++------
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net: cadence_gem: Disable TSU feature bit
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1 file changed, 29 insertions(+), 6 deletions(-)
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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27
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Jerome Forissier (1):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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Peter Maydell (2):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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Richard Henderson (4):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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diff view generated by jsdifflib
New patch
[PULL 1/1] Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"
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This reverts commit 9fcd15b9193e819b6cc2fd0a45e3506148812bb4.
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This change turns out to cause regressions, for instance on the
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imx6ul boards as described here:
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https://lore.kernel.org/qemu-devel/c8b89685-7490-328b-51a3-48711c140a84@tribudubois.net/
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The primary cause of that regression is that the guest code running
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at EL3 expects SMCs (not related to PSCI) to do what they would if
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our PSCI emulation was not present at all, but after this change
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they instead set a value in R0/X0 and continue.
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We could fix that by a refactoring that allowed us to only turn on
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the PSCI emulation if we weren't booting the guest at EL3, but there
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is a more tangled problem with the highbank board, which:
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(1) wants to enable PSCI emulation
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(2) has a bit of guest code that it wants to run at EL3 and
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to perform SMC calls that trap to the monitor vector table:
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this is the boot stub code that is written to memory by
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arm_write_secure_board_setup_dummy_smc() and which the
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highbank board enables by setting bootinfo->secure_board_setup
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We can't satisfy both of those and also have the PSCI emulation
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handle all SMC instruction executions regardless of function
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identifier value.
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This is too tricky to try to sort out before 6.2 is released;
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revert this commit so we can take the time to get it right in
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the 7.0 release.
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20211119163419.557623-1-peter.maydell@linaro.org
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---
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target/arm/psci.c | 35 +++++++++++++++++++++++++++++------
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1 file changed, 29 insertions(+), 6 deletions(-)
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diff --git a/target/arm/psci.c b/target/arm/psci.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/psci.c
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+++ b/target/arm/psci.c
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@@ -XXX,XX +XXX,XX @@
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bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
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{
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- /*
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- * Return true if the exception type matches the configured PSCI conduit.
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- * This is called before the SMC/HVC instruction is executed, to decide
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- * whether we should treat it as a PSCI call or with the architecturally
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+ /* Return true if the r0/x0 value indicates a PSCI call and
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+ * the exception type matches the configured PSCI conduit. This is
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+ * called before the SMC/HVC instruction is executed, to decide whether
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+ * we should treat it as a PSCI call or with the architecturally
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* defined behaviour for an SMC or HVC (which might be UNDEF or trap
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* to EL2 or to EL3).
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*/
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+ CPUARMState *env = &cpu->env;
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+ uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
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switch (excp_type) {
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case EXCP_HVC:
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@@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
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return false;
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}
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- return true;
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+ switch (param) {
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+ case QEMU_PSCI_0_2_FN_PSCI_VERSION:
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+ case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
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+ case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
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+ case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
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+ case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
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+ case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
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+ case QEMU_PSCI_0_1_FN_CPU_ON:
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+ case QEMU_PSCI_0_2_FN_CPU_ON:
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+ case QEMU_PSCI_0_2_FN64_CPU_ON:
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+ case QEMU_PSCI_0_1_FN_CPU_OFF:
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+ case QEMU_PSCI_0_2_FN_CPU_OFF:
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+ case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
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+ case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
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+ case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
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+ case QEMU_PSCI_0_1_FN_MIGRATE:
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+ case QEMU_PSCI_0_2_FN_MIGRATE:
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+ return true;
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+ default:
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+ return false;
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+ }
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}
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void arm_handle_psci_call(ARMCPU *cpu)
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@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
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break;
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case QEMU_PSCI_0_1_FN_MIGRATE:
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case QEMU_PSCI_0_2_FN_MIGRATE:
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- default:
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ret = QEMU_PSCI_RET_NOT_SUPPORTED;
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break;
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+ default:
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+ g_assert_not_reached();
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}
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err:
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--
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2.25.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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