[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 0/4] target-arm queue
1
v2: dropped a couple of cadence_gem changes to ID regs that
1
Hi; some minor changes for 6.2, which I think can be classified
2
caused new clang sanitizer warnings.
2
as bug fixes and are OK for this point in the release cycle.
3
(Wouldn't be the end of the world if they slipped to 7.0.)
3
4
4
-- PMM
5
-- PMM
5
6
6
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
7
The following changes since commit 42f6c9179be4401974dd3a75ee72defd16b5092d:
7
8
8
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
9
Merge tag 'pull-ppc-20211112' of https://github.com/legoater/qemu into staging (2021-11-12 12:28:25 +0100)
9
10
10
are available in the Git repository at:
11
are available in the Git repository at:
11
12
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211115-1
13
14
14
for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
15
for you to fetch changes up to 1adf528ec3bdf62ea3b580b7ad562534a3676ff5:
15
16
16
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
17
hw/rtc/pl031: Send RTC_CHANGE QMP event (2021-11-15 18:53:00 +0000)
17
18
18
----------------------------------------------------------------
19
----------------------------------------------------------------
19
target-arm queue:
20
target-arm queue:
20
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
21
* Support multiple redistributor regions for TCG GICv3
21
* target/arm: Fix aarch64_sve_change_el wrt EL0
22
* Send RTC_CHANGE QMP event from pl031
22
* target/arm: Define fields of ISAR registers
23
* target/arm: Align cortex-r5 id_isar0
24
* target/arm: Fix cortex-a7 id_isar0
25
* net/cadence_gem: Fix various bugs, add support for new
26
features that will be used by the Xilinx Versal board
27
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
28
* target/arm: Add the Cortex-A72
29
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
30
* target/arm: Mask PMOVSR writes based on supported counters
31
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
32
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
33
23
34
----------------------------------------------------------------
24
----------------------------------------------------------------
35
Aaron Lindsay (2):
25
Eric Auger (1):
36
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
26
hw/rtc/pl031: Send RTC_CHANGE QMP event
37
target/arm: Mask PMOVSR writes based on supported counters
38
27
39
Edgar E. Iglesias (8):
28
Peter Maydell (3):
40
net: cadence_gem: Disable TSU feature bit
29
hw/intc/arm_gicv3: Move checking of redist-region-count to arm_gicv3_common_realize
41
net: cadence_gem: Use uint32_t for 32bit descriptor words
30
hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1
42
net: cadence_gem: Add macro with max number of descriptor words
31
hw/intc/arm_gicv3: Support multiple redistributor regions
43
net: cadence_gem: Add support for extended descriptors
44
net: cadence_gem: Add support for selecting the DMA MemoryRegion
45
net: cadence_gem: Implement support for 64bit descriptor addresses
46
target-arm: powerctl: Enable HVC when starting CPUs to EL2
47
target/arm: Add the Cortex-A72
48
32
49
Jerome Forissier (1):
33
include/hw/intc/arm_gicv3_common.h | 14 ++++++++--
50
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
34
hw/intc/arm_gicv3.c | 12 +-------
35
hw/intc/arm_gicv3_common.c | 56 ++++++++++++++++++++++++--------------
36
hw/intc/arm_gicv3_kvm.c | 10 ++-----
37
hw/intc/arm_gicv3_redist.c | 40 +++++++++++++++------------
38
hw/rtc/pl031.c | 10 ++++++-
39
hw/rtc/meson.build | 2 +-
40
7 files changed, 83 insertions(+), 61 deletions(-)
51
41
52
Peter Maydell (2):
53
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
54
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
55
56
Richard Henderson (4):
57
target/arm: Fix aarch64_sve_change_el wrt EL0
58
target/arm: Define fields of ISAR registers
59
target/arm: Align cortex-r5 id_isar0
60
target/arm: Fix cortex-a7 id_isar0
61
62
include/hw/net/cadence_gem.h | 7 +-
63
target/arm/cpu.h | 95 ++++++++++++++-
64
hw/arm/virt.c | 4 +
65
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
66
target/arm/arm-powerctl.c | 10 ++
67
target/arm/cpu.c | 7 +-
68
target/arm/cpu64.c | 66 +++++++++-
69
target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
71
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
72
10 files changed, 402 insertions(+), 70 deletions(-)
73
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
74
diff view generated by jsdifflib
New patch
[PULL 1/4] hw/intc/arm_gicv3: Move checking of redist-region-count to arm_gicv3_common_realize
1
The GICv3 devices have an array property redist-region-count.
2
Currently we check this for errors (bad values) in
3
gicv3_init_irqs_and_mmio(), just before we use it. Move this error
4
checking to the arm_gicv3_common_realize() function, where we
5
sanity-check all of the other base-class properties. (This will
6
always be before gicv3_init_irqs_and_mmio() is called, because
7
that function is called in the subclass realize methods, after
8
they have called the parent-class realize.)
1
9
10
The motivation for this refactor is:
11
* we would like to use the redist_region_count[] values in
12
arm_gicv3_common_realize() in a subsequent patch, so we need
13
to have already done the sanity-checking first
14
* this removes the only use of the Error** argument to
15
gicv3_init_irqs_and_mmio(), so we can remove some error-handling
16
boilerplate
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
---
21
include/hw/intc/arm_gicv3_common.h | 2 +-
22
hw/intc/arm_gicv3.c | 6 +-----
23
hw/intc/arm_gicv3_common.c | 26 +++++++++++++-------------
24
hw/intc/arm_gicv3_kvm.c | 6 +-----
25
4 files changed, 16 insertions(+), 24 deletions(-)
26
27
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/intc/arm_gicv3_common.h
30
+++ b/include/hw/intc/arm_gicv3_common.h
31
@@ -XXX,XX +XXX,XX @@ struct ARMGICv3CommonClass {
32
};
33
34
void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
35
- const MemoryRegionOps *ops, Error **errp);
36
+ const MemoryRegionOps *ops);
37
38
#endif
39
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/intc/arm_gicv3.c
42
+++ b/hw/intc/arm_gicv3.c
43
@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
44
return;
45
}
46
47
- gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops, &local_err);
48
- if (local_err) {
49
- error_propagate(errp, local_err);
50
- return;
51
- }
52
+ gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
53
54
gicv3_init_cpuif(s);
55
}
56
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/intc/arm_gicv3_common.c
59
+++ b/hw/intc/arm_gicv3_common.c
60
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = {
61
};
62
63
void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
64
- const MemoryRegionOps *ops, Error **errp)
65
+ const MemoryRegionOps *ops)
66
{
67
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
68
- int rdist_capacity = 0;
69
int i;
70
71
- for (i = 0; i < s->nb_redist_regions; i++) {
72
- rdist_capacity += s->redist_region_count[i];
73
- }
74
- if (rdist_capacity < s->num_cpu) {
75
- error_setg(errp, "Capacity of the redist regions(%d) "
76
- "is less than number of vcpus(%d)",
77
- rdist_capacity, s->num_cpu);
78
- return;
79
- }
80
-
81
/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
82
* GPIO array layout is thus:
83
* [0..N-1] spi
84
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
85
static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
86
{
87
GICv3State *s = ARM_GICV3_COMMON(dev);
88
- int i;
89
+ int i, rdist_capacity;
90
91
/* revision property is actually reserved and currently used only in order
92
* to keep the interface compatible with GICv2 code, avoiding extra
93
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
94
return;
95
}
96
97
+ rdist_capacity = 0;
98
+ for (i = 0; i < s->nb_redist_regions; i++) {
99
+ rdist_capacity += s->redist_region_count[i];
100
+ }
101
+ if (rdist_capacity < s->num_cpu) {
102
+ error_setg(errp, "Capacity of the redist regions(%d) "
103
+ "is less than number of vcpus(%d)",
104
+ rdist_capacity, s->num_cpu);
105
+ return;
106
+ }
107
+
108
s->cpu = g_new0(GICv3CPUState, s->num_cpu);
109
110
for (i = 0; i < s->num_cpu; i++) {
111
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/hw/intc/arm_gicv3_kvm.c
114
+++ b/hw/intc/arm_gicv3_kvm.c
115
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
116
return;
117
}
118
119
- gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL, &local_err);
120
- if (local_err) {
121
- error_propagate(errp, local_err);
122
- return;
123
- }
124
+ gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
125
126
for (i = 0; i < s->num_cpu; i++) {
127
ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
128
--
129
2.25.1
130
131
diff view generated by jsdifflib
New patch
[PULL 2/4] hw/intc/arm_gicv3: Set GICR_TYPER.Last correctly when nb_redist_regions > 1
1
The 'Last' bit in the GICR_TYPER GICv3 redistributor register is
2
supposed to be set to 1 if this is the last redistributor in a series
3
of contiguous redistributor pages. Currently we set Last only for
4
the redistributor for CPU (num_cpu - 1). This only works if there is
5
a single redistributor region; if there are multiple redistributor
6
regions then we need to set the Last bit for the last redistributor
7
in each region.
1
8
9
This doesn't cause any problems currently because only the KVM GICv3
10
supports multiple redistributor regions, and it ignores the value in
11
GICv3State::gicr_typer. But we need to fix this before we can enable
12
support for multiple regions in the emulated GICv3.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
---
17
hw/intc/arm_gicv3_common.c | 17 ++++++++++++-----
18
1 file changed, 12 insertions(+), 5 deletions(-)
19
20
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/arm_gicv3_common.c
23
+++ b/hw/intc/arm_gicv3_common.c
24
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
25
static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
26
{
27
GICv3State *s = ARM_GICV3_COMMON(dev);
28
- int i, rdist_capacity;
29
+ int i, rdist_capacity, cpuidx;
30
31
/* revision property is actually reserved and currently used only in order
32
* to keep the interface compatible with GICv2 code, avoiding extra
33
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
34
for (i = 0; i < s->num_cpu; i++) {
35
CPUState *cpu = qemu_get_cpu(i);
36
uint64_t cpu_affid;
37
- int last;
38
39
s->cpu[i].cpu = cpu;
40
s->cpu[i].gic = s;
41
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
42
* PLPIS == 0 (physical LPIs not supported)
43
*/
44
cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL);
45
- last = (i == s->num_cpu - 1);
46
47
/* The CPU mp-affinity property is in MPIDR register format; squash
48
* the affinity bytes into 32 bits as the GICR_TYPER has them.
49
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
50
(cpu_affid & 0xFFFFFF);
51
s->cpu[i].gicr_typer = (cpu_affid << 32) |
52
(1 << 24) |
53
- (i << 8) |
54
- (last << 4);
55
+ (i << 8);
56
57
if (s->lpi_enable) {
58
s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
59
}
60
}
61
+
62
+ /*
63
+ * Now go through and set GICR_TYPER.Last for the final
64
+ * redistributor in each region.
65
+ */
66
+ cpuidx = 0;
67
+ for (i = 0; i < s->nb_redist_regions; i++) {
68
+ cpuidx += s->redist_region_count[i];
69
+ s->cpu[cpuidx - 1].gicr_typer |= GICR_TYPER_LAST;
70
+ }
71
}
72
73
static void arm_gicv3_finalize(Object *obj)
74
--
75
2.25.1
76
77
diff view generated by jsdifflib
New patch
[PULL 3/4] hw/intc/arm_gicv3: Support multiple redistributor regions
1
1
Our GICv3 QOM interface includes an array property
2
redist-region-count which allows board models to specify that the
3
registributor registers are not in a single contiguous range, but
4
split into multiple pieces. We implemented this for KVM, but
5
currently the TCG GICv3 model insists that there is only one region.
6
You can see the limit being hit with a setup like:
7
qemu-system-aarch64 -machine virt,gic-version=3 -smp 124
8
9
Add support for split regions to the TCG GICv3. To do this we switch
10
from allocating a simple array of MemoryRegions to an array of
11
GICv3RedistRegion structs so that we can use the GICv3RedistRegion as
12
the opaque pointer in the MemoryRegion read/write callbacks. Each
13
GICv3RedistRegion contains the MemoryRegion, a backpointer allowing
14
the read/write callback to get hold of the GICv3State, and an index
15
which allows us to calculate which CPU's redistributor is being
16
accessed.
17
18
Note that arm_gicv3_kvm always passes in NULL as the ops argument
19
to gicv3_init_irqs_and_mmio(), so the only MemoryRegion read/write
20
callbacks we need to update to handle this new scheme are the
21
gicv3_redist_read/write functions used by the emulated GICv3.
22
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
---
26
include/hw/intc/arm_gicv3_common.h | 12 ++++++++-
27
hw/intc/arm_gicv3.c | 6 -----
28
hw/intc/arm_gicv3_common.c | 15 ++++++++---
29
hw/intc/arm_gicv3_kvm.c | 4 +--
30
hw/intc/arm_gicv3_redist.c | 40 ++++++++++++++++--------------
31
5 files changed, 46 insertions(+), 31 deletions(-)
32
33
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/include/hw/intc/arm_gicv3_common.h
36
+++ b/include/hw/intc/arm_gicv3_common.h
37
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
38
bool seenbetter;
39
};
40
41
+/*
42
+ * The redistributor pages might be split into more than one region
43
+ * on some machine types if there are many CPUs.
44
+ */
45
+typedef struct GICv3RedistRegion {
46
+ GICv3State *gic;
47
+ MemoryRegion iomem;
48
+ uint32_t cpuidx; /* index of first CPU this region covers */
49
+} GICv3RedistRegion;
50
+
51
struct GICv3State {
52
/*< private >*/
53
SysBusDevice parent_obj;
54
/*< public >*/
55
56
MemoryRegion iomem_dist; /* Distributor */
57
- MemoryRegion *iomem_redist; /* Redistributor Regions */
58
+ GICv3RedistRegion *redist_regions; /* Redistributor Regions */
59
uint32_t *redist_region_count; /* redistributor count within each region */
60
uint32_t nb_redist_regions; /* number of redist regions */
61
62
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/hw/intc/arm_gicv3.c
65
+++ b/hw/intc/arm_gicv3.c
66
@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
67
return;
68
}
69
70
- if (s->nb_redist_regions != 1) {
71
- error_setg(errp, "VGICv3 redist region number(%d) not equal to 1",
72
- s->nb_redist_regions);
73
- return;
74
- }
75
-
76
gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
77
78
gicv3_init_cpuif(s);
79
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/intc/arm_gicv3_common.c
82
+++ b/hw/intc/arm_gicv3_common.c
83
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
84
{
85
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
86
int i;
87
+ int cpuidx;
88
89
/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
90
* GPIO array layout is thus:
91
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
92
"gicv3_dist", 0x10000);
93
sysbus_init_mmio(sbd, &s->iomem_dist);
94
95
- s->iomem_redist = g_new0(MemoryRegion, s->nb_redist_regions);
96
+ s->redist_regions = g_new0(GICv3RedistRegion, s->nb_redist_regions);
97
+ cpuidx = 0;
98
for (i = 0; i < s->nb_redist_regions; i++) {
99
char *name = g_strdup_printf("gicv3_redist_region[%d]", i);
100
+ GICv3RedistRegion *region = &s->redist_regions[i];
101
102
- memory_region_init_io(&s->iomem_redist[i], OBJECT(s),
103
- ops ? &ops[1] : NULL, s, name,
104
+ region->gic = s;
105
+ region->cpuidx = cpuidx;
106
+ cpuidx += s->redist_region_count[i];
107
+
108
+ memory_region_init_io(&region->iomem, OBJECT(s),
109
+ ops ? &ops[1] : NULL, region, name,
110
s->redist_region_count[i] * GICV3_REDIST_SIZE);
111
- sysbus_init_mmio(sbd, &s->iomem_redist[i]);
112
+ sysbus_init_mmio(sbd, &region->iomem);
113
g_free(name);
114
}
115
}
116
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/hw/intc/arm_gicv3_kvm.c
119
+++ b/hw/intc/arm_gicv3_kvm.c
120
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
121
KVM_VGIC_V3_ADDR_TYPE_DIST, s->dev_fd, 0);
122
123
if (!multiple_redist_region_allowed) {
124
- kvm_arm_register_device(&s->iomem_redist[0], -1,
125
+ kvm_arm_register_device(&s->redist_regions[0].iomem, -1,
126
KVM_DEV_ARM_VGIC_GRP_ADDR,
127
KVM_VGIC_V3_ADDR_TYPE_REDIST, s->dev_fd, 0);
128
} else {
129
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
130
uint64_t addr_ormask =
131
i | ((uint64_t)s->redist_region_count[i] << 52);
132
133
- kvm_arm_register_device(&s->iomem_redist[i], -1,
134
+ kvm_arm_register_device(&s->redist_regions[i].iomem, -1,
135
KVM_DEV_ARM_VGIC_GRP_ADDR,
136
KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION,
137
s->dev_fd, addr_ormask);
138
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
139
index XXXXXXX..XXXXXXX 100644
140
--- a/hw/intc/arm_gicv3_redist.c
141
+++ b/hw/intc/arm_gicv3_redist.c
142
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset,
143
MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
144
unsigned size, MemTxAttrs attrs)
145
{
146
- GICv3State *s = opaque;
147
+ GICv3RedistRegion *region = opaque;
148
+ GICv3State *s = region->gic;
149
GICv3CPUState *cs;
150
MemTxResult r;
151
int cpuidx;
152
153
assert((offset & (size - 1)) == 0);
154
155
- /* This region covers all the redistributor pages; there are
156
- * (for GICv3) two 64K pages per CPU. At the moment they are
157
- * all contiguous (ie in this one region), though we might later
158
- * want to allow splitting of redistributor pages into several
159
- * blocks so we can support more CPUs.
160
+ /*
161
+ * There are (for GICv3) two 64K redistributor pages per CPU.
162
+ * In some cases the redistributor pages for all CPUs are not
163
+ * contiguous (eg on the virt board they are split into two
164
+ * parts if there are too many CPUs to all fit in the same place
165
+ * in the memory map); if so then the GIC has multiple MemoryRegions
166
+ * for the redistributors.
167
*/
168
- cpuidx = offset / 0x20000;
169
- offset %= 0x20000;
170
- assert(cpuidx < s->num_cpu);
171
+ cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;
172
+ offset %= GICV3_REDIST_SIZE;
173
174
cs = &s->cpu[cpuidx];
175
176
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
177
MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
178
unsigned size, MemTxAttrs attrs)
179
{
180
- GICv3State *s = opaque;
181
+ GICv3RedistRegion *region = opaque;
182
+ GICv3State *s = region->gic;
183
GICv3CPUState *cs;
184
MemTxResult r;
185
int cpuidx;
186
187
assert((offset & (size - 1)) == 0);
188
189
- /* This region covers all the redistributor pages; there are
190
- * (for GICv3) two 64K pages per CPU. At the moment they are
191
- * all contiguous (ie in this one region), though we might later
192
- * want to allow splitting of redistributor pages into several
193
- * blocks so we can support more CPUs.
194
+ /*
195
+ * There are (for GICv3) two 64K redistributor pages per CPU.
196
+ * In some cases the redistributor pages for all CPUs are not
197
+ * contiguous (eg on the virt board they are split into two
198
+ * parts if there are too many CPUs to all fit in the same place
199
+ * in the memory map); if so then the GIC has multiple MemoryRegions
200
+ * for the redistributors.
201
*/
202
- cpuidx = offset / 0x20000;
203
- offset %= 0x20000;
204
- assert(cpuidx < s->num_cpu);
205
+ cpuidx = region->cpuidx + offset / GICV3_REDIST_SIZE;
206
+ offset %= GICV3_REDIST_SIZE;
207
208
cs = &s->cpu[cpuidx];
209
210
--
211
2.25.1
212
213
diff view generated by jsdifflib
New patch
[PULL 4/4] hw/rtc/pl031: Send RTC_CHANGE QMP event
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
The PL031 currently is not able to report guest RTC change to the QMP
4
monitor as opposed to mc146818 or spapr RTCs. This patch adds the call
5
to qapi_event_send_rtc_change() when the Load Register is written. The
6
value which is reported corresponds to the difference between the guest
7
reference time and the reference time kept in softmmu/rtc.c.
8
9
For instance adding 20s to the guest RTC value will report 20. Adding
10
an extra 20s to the guest RTC value will report 20 + 20 = 40.
11
12
The inclusion of qapi/qapi-types-misc-target.h in hw/rtl/pl031.c
13
require to compile the PL031 with specific_ss.add() to avoid
14
./qapi/qapi-types-misc-target.h:18:13: error: attempt to use poisoned
15
"TARGET_<ARCH>".
16
17
Signed-off-by: Eric Auger <eric.auger@redhat.com>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Message-id: 20210920122535.269988-1-eric.auger@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
hw/rtc/pl031.c | 10 +++++++++-
23
hw/rtc/meson.build | 2 +-
24
2 files changed, 10 insertions(+), 2 deletions(-)
25
26
diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/rtc/pl031.c
29
+++ b/hw/rtc/pl031.c
30
@@ -XXX,XX +XXX,XX @@
31
#include "qemu/log.h"
32
#include "qemu/module.h"
33
#include "trace.h"
34
+#include "qapi/qapi-events-misc-target.h"
35
36
#define RTC_DR 0x00 /* Data read register */
37
#define RTC_MR 0x04 /* Match register */
38
@@ -XXX,XX +XXX,XX @@ static void pl031_write(void * opaque, hwaddr offset,
39
trace_pl031_write(offset, value);
40
41
switch (offset) {
42
- case RTC_LR:
43
+ case RTC_LR: {
44
+ struct tm tm;
45
+
46
s->tick_offset += value - pl031_get_count(s);
47
+
48
+ qemu_get_timedate(&tm, s->tick_offset);
49
+ qapi_event_send_rtc_change(qemu_timedate_diff(&tm));
50
+
51
pl031_set_alarm(s);
52
break;
53
+ }
54
case RTC_MR:
55
s->mr = value;
56
pl031_set_alarm(s);
57
diff --git a/hw/rtc/meson.build b/hw/rtc/meson.build
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/rtc/meson.build
60
+++ b/hw/rtc/meson.build
61
@@ -XXX,XX +XXX,XX @@
62
softmmu_ss.add(when: 'CONFIG_DS1338', if_true: files('ds1338.c'))
63
softmmu_ss.add(when: 'CONFIG_M41T80', if_true: files('m41t80.c'))
64
softmmu_ss.add(when: 'CONFIG_M48T59', if_true: files('m48t59.c'))
65
-softmmu_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c'))
66
+specific_ss.add(when: 'CONFIG_PL031', if_true: files('pl031.c'))
67
softmmu_ss.add(when: 'CONFIG_TWL92230', if_true: files('twl92230.c'))
68
softmmu_ss.add(when: ['CONFIG_ISA_BUS', 'CONFIG_M48T59'], if_true: files('m48t59-isa.c'))
69
softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-rtc.c'))
70
--
71
2.25.1
72
73
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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