Series comparison

-[Qemu-devel] [PULL 00/17] target-arm queue
+[PULL v2 00/57] target-arm queue
-v2: dropped a couple of cadence_gem changes to ID regs that
+Squashed in a trivial fix for 32-bit hosts:
-caused new clang sanitizer warnings.
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
                      acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
                                               m[H##ESIZE(e)]));          \
                  }                                                       \
 -                acc = int128_add(acc, 1 << 7);                          \
 +                acc = int128_add(acc, int128_make64(1 << 7));           \
              }                                                           \
          }                                                               \
          mve_advance_vpt(env);                                           \
 -- PMM
-The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
+The following changes since commit 53f306f316549d20c76886903181413d20842423:
-  Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
+  Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
-for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
+for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
-  coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
+  docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
+ * Don't require 'virt' board to be compiled in for ACPI GHES code
- * target/arm: Fix aarch64_sve_change_el wrt EL0
+ * docs: Document which architecture extensions we emulate
- * target/arm: Define fields of ISAR registers
+ * Fix bugs in M-profile FPCXT_NS accesses
- * target/arm: Align cortex-r5 id_isar0
+ * First slice of MVE patches
- * target/arm: Fix cortex-a7 id_isar0
+ * Implement MTE3
- * net/cadence_gem: Fix various bugs, add support for new
+ * docs/system: arm: Add nRF boards description
    features that will be used by the Xilinx Versal board
  * target-arm: powerctl: Enable HVC when starting CPUs to EL2
  * target/arm: Add the Cortex-A72
  * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
  * target/arm: Mask PMOVSR writes based on supported counters
  * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
  * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
 ----------------------------------------------------------------
-Aaron Lindsay (2):
+Alexandre Iooss (1):
-      target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
+      docs/system: arm: Add nRF boards description
       target/arm: Mask PMOVSR writes based on supported counters
-Edgar E. Iglesias (8):
+Peter Collingbourne (1):
-      net: cadence_gem: Disable TSU feature bit
+      target/arm: Implement MTE3
       net: cadence_gem: Use uint32_t for 32bit descriptor words
       net: cadence_gem: Add macro with max number of descriptor words
       net: cadence_gem: Add support for extended descriptors
       net: cadence_gem: Add support for selecting the DMA MemoryRegion
       net: cadence_gem: Implement support for 64bit descriptor addresses
       target-arm: powerctl: Enable HVC when starting CPUs to EL2
       target/arm: Add the Cortex-A72
-Jerome Forissier (1):
+Peter Maydell (55):
-      hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
+      hw/acpi: Provide stub version of acpi_ghes_record_errors()
       hw/acpi: Provide function acpi_ghes_present()
       target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
       docs/system/arm: Document which architecture extensions we emulate
       target/arm/translate-vfp.c: Whitespace fixes
       target/arm: Handle FPU being disabled in FPCXT_NS accesses
       target/arm: Don't NOCP fault for FPCXT_NS accesses
       target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
       target/arm: Factor FP context update code out into helper function
       target/arm: Split vfp_access_check() into A and M versions
       target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
       target/arm: Implement MVE VLDR/VSTR (non-widening forms)
       target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
       target/arm: Implement MVE VCLZ
       target/arm: Implement MVE VCLS
       target/arm: Implement MVE VREV16, VREV32, VREV64
       target/arm: Implement MVE VMVN (register)
       target/arm: Implement MVE VABS
       target/arm: Implement MVE VNEG
       tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
       target/arm: Implement MVE VDUP
       target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
       target/arm: Implement MVE VADD, VSUB, VMUL
       target/arm: Implement MVE VMULH
       target/arm: Implement MVE VRMULH
       target/arm: Implement MVE VMAX, VMIN
       target/arm: Implement MVE VABD
       target/arm: Implement MVE VHADD, VHSUB
       target/arm: Implement MVE VMULL
       target/arm: Implement MVE VMLALDAV
       target/arm: Implement MVE VMLSLDAV
       target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
       target/arm: Implement MVE VADD (scalar)
       target/arm: Implement MVE VSUB, VMUL (scalar)
       target/arm: Implement MVE VHADD, VHSUB (scalar)
       target/arm: Implement MVE VBRSR
       target/arm: Implement MVE VPST
       target/arm: Implement MVE VQADD and VQSUB
       target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
       target/arm: Implement MVE VQDMULL scalar
       target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
       target/arm: Implement MVE VQADD, VQSUB (vector)
       target/arm: Implement MVE VQSHL (vector)
       target/arm: Implement MVE VQRSHL
       target/arm: Implement MVE VSHL insn
       target/arm: Implement MVE VRSHL
       target/arm: Implement MVE VQDMLADH and VQRDMLADH
       target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
       target/arm: Implement MVE VQDMULL (vector)
       target/arm: Implement MVE VRHADD
       target/arm: Implement MVE VADC, VSBC
       target/arm: Implement MVE VCADD
       target/arm: Implement MVE VHCADD
       target/arm: Implement MVE VADDV
       target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
-Peter Maydell (2):
+ docs/system/arm/emulation.rst |  103 ++++
-      target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
+ docs/system/arm/nrf.rst       |   51 ++
-      coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
+ docs/system/target-arm.rst    |    7 +
  include/hw/acpi/ghes.h        |    9 +
  include/tcg/tcg-op.h          |    8 +
  include/tcg/tcg.h             |    1 -
  target/arm/helper-mve.h       |  357 +++++++++++++
  target/arm/helper.h           |    2 +
  target/arm/internals.h        |   11 +
  target/arm/translate-a32.h    |    3 +
  target/arm/translate.h        |   10 +
  target/arm/m-nocp.decode      |   24 +
  target/arm/mve.decode         |  240 +++++++++
  target/arm/vfp.decode         |   14 -
  hw/acpi/ghes-stub.c           |   22 +
  hw/acpi/ghes.c                |   17 +
  target/arm/cpu64.c            |    2 +-
  target/arm/kvm64.c            |    6 +-
  target/arm/mte_helper.c       |   82 +--
  target/arm/mve_helper.c       | 1160 +++++++++++++++++++++++++++++++++++++++++
  target/arm/translate-m-nocp.c |  550 +++++++++++++++++++
  target/arm/translate-mve.c    |  759 +++++++++++++++++++++++++++
  target/arm/translate-vfp.c    |  741 +++++++-------------------
  tcg/tcg-op-gvec.c             |   20 +-
  MAINTAINERS                   |    1 +
  hw/acpi/meson.build           |    6 +-
  target/arm/meson.build        |    1 +
 files changed, 3578 insertions(+), 629 deletions(-)
  create mode 100644 docs/system/arm/emulation.rst
  create mode 100644 docs/system/arm/nrf.rst
  create mode 100644 target/arm/helper-mve.h
  create mode 100644 hw/acpi/ghes-stub.c
  create mode 100644 target/arm/mve_helper.c
-Richard Henderson (4):
-      target/arm: Fix aarch64_sve_change_el wrt EL0
-      target/arm: Define fields of ISAR registers
-      target/arm: Align cortex-r5 id_isar0
-      target/arm: Fix cortex-a7 id_isar0
- include/hw/net/cadence_gem.h               |   7 +-
- target/arm/cpu.h                           |  95 ++++++++++++++-
- hw/arm/virt.c                              |   4 +
- hw/net/cadence_gem.c                       | 185 ++++++++++++++++++++---------
- target/arm/arm-powerctl.c                  |  10 ++
- target/arm/cpu.c                           |   7 +-
- target/arm/cpu64.c                         |  66 +++++++++-
- target/arm/helper.c                        |  27 +++--
- target/arm/op_helper.c                     |   6 +-
- scripts/coccinelle/inplace-byteswaps.cocci |  65 ++++++++++
-files changed, 402 insertions(+), 70 deletions(-)
- create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci

v2: dropped a couple of cadence_gem changes to ID regs that
caused new clang sanitizer warnings.

-- PMM

The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:

Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1

for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:

coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
 * target/arm: Fix aarch64_sve_change_el wrt EL0
 * target/arm: Define fields of ISAR registers
 * target/arm: Align cortex-r5 id_isar0
 * target/arm: Fix cortex-a7 id_isar0
 * net/cadence_gem: Fix various bugs, add support for new
   features that will be used by the Xilinx Versal board
 * target-arm: powerctl: Enable HVC when starting CPUs to EL2
 * target/arm: Add the Cortex-A72
 * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
 * target/arm: Mask PMOVSR writes based on supported counters
 * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
 * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls

----------------------------------------------------------------
Aaron Lindsay (2):
      target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
      target/arm: Mask PMOVSR writes based on supported counters

Edgar E. Iglesias (8):
      net: cadence_gem: Disable TSU feature bit
      net: cadence_gem: Use uint32_t for 32bit descriptor words
      net: cadence_gem: Add macro with max number of descriptor words
      net: cadence_gem: Add support for extended descriptors
      net: cadence_gem: Add support for selecting the DMA MemoryRegion
      net: cadence_gem: Implement support for 64bit descriptor addresses
      target-arm: powerctl: Enable HVC when starting CPUs to EL2
      target/arm: Add the Cortex-A72

Jerome Forissier (1):
      hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART

Peter Maydell (2):
      target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
      coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls

Richard Henderson (4):
      target/arm: Fix aarch64_sve_change_el wrt EL0
      target/arm: Define fields of ISAR registers
      target/arm: Align cortex-r5 id_isar0
      target/arm: Fix cortex-a7 id_isar0

include/hw/net/cadence_gem.h               |   7 +-
 target/arm/cpu.h                           |  95 ++++++++++++++-
 hw/arm/virt.c                              |   4 +
 hw/net/cadence_gem.c                       | 185 ++++++++++++++++++++---------
 target/arm/arm-powerctl.c                  |  10 ++
 target/arm/cpu.c                           |   7 +-
 target/arm/cpu64.c                         |  66 +++++++++-
 target/arm/helper.c                        |  27 +++--
 target/arm/op_helper.c                     |   6 +-
 scripts/coccinelle/inplace-byteswaps.cocci |  65 ++++++++++
 10 files changed, 402 insertions(+), 70 deletions(-)
 create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci

Squashed in a trivial fix for 32-bit hosts:

--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
                     acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
                                              m[H##ESIZE(e)]));          \
                 }                                                       \
-                acc = int128_add(acc, 1 << 7);                          \
+                acc = int128_add(acc, int128_make64(1 << 7));           \
             }                                                           \
         }                                                               \
         mve_advance_vpt(env);                                           \

-- PMM

The following changes since commit 53f306f316549d20c76886903181413d20842423:

Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624

for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:

docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)

----------------------------------------------------------------
target-arm queue:
 * Don't require 'virt' board to be compiled in for ACPI GHES code
 * docs: Document which architecture extensions we emulate
 * Fix bugs in M-profile FPCXT_NS accesses
 * First slice of MVE patches
 * Implement MTE3
 * docs/system: arm: Add nRF boards description

----------------------------------------------------------------
Alexandre Iooss (1):
      docs/system: arm: Add nRF boards description

Peter Collingbourne (1):
      target/arm: Implement MTE3

Peter Maydell (55):
      hw/acpi: Provide stub version of acpi_ghes_record_errors()
      hw/acpi: Provide function acpi_ghes_present()
      target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
      docs/system/arm: Document which architecture extensions we emulate
      target/arm/translate-vfp.c: Whitespace fixes
      target/arm: Handle FPU being disabled in FPCXT_NS accesses
      target/arm: Don't NOCP fault for FPCXT_NS accesses
      target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
      target/arm: Factor FP context update code out into helper function
      target/arm: Split vfp_access_check() into A and M versions
      target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
      target/arm: Implement MVE VLDR/VSTR (non-widening forms)
      target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
      target/arm: Implement MVE VCLZ
      target/arm: Implement MVE VCLS
      target/arm: Implement MVE VREV16, VREV32, VREV64
      target/arm: Implement MVE VMVN (register)
      target/arm: Implement MVE VABS
      target/arm: Implement MVE VNEG
      tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
      target/arm: Implement MVE VDUP
      target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
      target/arm: Implement MVE VADD, VSUB, VMUL
      target/arm: Implement MVE VMULH
      target/arm: Implement MVE VRMULH
      target/arm: Implement MVE VMAX, VMIN
      target/arm: Implement MVE VABD
      target/arm: Implement MVE VHADD, VHSUB
      target/arm: Implement MVE VMULL
      target/arm: Implement MVE VMLALDAV
      target/arm: Implement MVE VMLSLDAV
      target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
      target/arm: Implement MVE VADD (scalar)
      target/arm: Implement MVE VSUB, VMUL (scalar)
      target/arm: Implement MVE VHADD, VHSUB (scalar)
      target/arm: Implement MVE VBRSR
      target/arm: Implement MVE VPST
      target/arm: Implement MVE VQADD and VQSUB
      target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
      target/arm: Implement MVE VQDMULL scalar
      target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
      target/arm: Implement MVE VQADD, VQSUB (vector)
      target/arm: Implement MVE VQSHL (vector)
      target/arm: Implement MVE VQRSHL
      target/arm: Implement MVE VSHL insn
      target/arm: Implement MVE VRSHL
      target/arm: Implement MVE VQDMLADH and VQRDMLADH
      target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
      target/arm: Implement MVE VQDMULL (vector)
      target/arm: Implement MVE VRHADD
      target/arm: Implement MVE VADC, VSBC
      target/arm: Implement MVE VCADD
      target/arm: Implement MVE VHCADD
      target/arm: Implement MVE VADDV
      target/arm: Make VMOV scalar <-> gpreg beatwise for MVE

docs/system/arm/emulation.rst |  103 ++++
 docs/system/arm/nrf.rst       |   51 ++
 docs/system/target-arm.rst    |    7 +
 include/hw/acpi/ghes.h        |    9 +
 include/tcg/tcg-op.h          |    8 +
 include/tcg/tcg.h             |    1 -
 target/arm/helper-mve.h       |  357 +++++++++++++
 target/arm/helper.h           |    2 +
 target/arm/internals.h        |   11 +
 target/arm/translate-a32.h    |    3 +
 target/arm/translate.h        |   10 +
 target/arm/m-nocp.decode      |   24 +
 target/arm/mve.decode         |  240 +++++++++
 target/arm/vfp.decode         |   14 -
 hw/acpi/ghes-stub.c           |   22 +
 hw/acpi/ghes.c                |   17 +
 target/arm/cpu64.c            |    2 +-
 target/arm/kvm64.c            |    6 +-
 target/arm/mte_helper.c       |   82 +--
 target/arm/mve_helper.c       | 1160 +++++++++++++++++++++++++++++++++++++++++
 target/arm/translate-m-nocp.c |  550 +++++++++++++++++++
 target/arm/translate-mve.c    |  759 +++++++++++++++++++++++++++
 target/arm/translate-vfp.c    |  741 +++++++-------------------
 tcg/tcg-op-gvec.c             |   20 +-
 MAINTAINERS                   |    1 +
 hw/acpi/meson.build           |    6 +-
 target/arm/meson.build        |    1 +
 27 files changed, 3578 insertions(+), 629 deletions(-)
 create mode 100644 docs/system/arm/emulation.rst
 create mode 100644 docs/system/arm/nrf.rst
 create mode 100644 target/arm/helper-mve.h
 create mode 100644 hw/acpi/ghes-stub.c
 create mode 100644 target/arm/mve_helper.c