[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 0/3] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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A few last patches to go in for rc3...
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caused new clang sanitizer warnings.
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-- PMM
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The following changes since commit c1e90def01bdb8fcbdbebd9d1eaa8e4827ece620:
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210412' into staging (2021-04-12 12:12:09 +0100)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210413
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to 2d18b4ca023ca1a3aee18064251d6e6e1084f3eb:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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sphinx: qapidoc: Wrap "If" section body in a paragraph node (2021-04-13 10:14:58 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* Fix MPC setting for AN524 SRAM block
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* sphinx: qapidoc: Wrap "If" section body in a paragraph node
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* target/arm: Define fields of ISAR registers
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* target/arm: Align cortex-r5 id_isar0
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* target/arm: Fix cortex-a7 id_isar0
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* net/cadence_gem: Fix various bugs, add support for new
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features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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John Snow (1):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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sphinx: qapidoc: Wrap "If" section body in a paragraph node
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target/arm: Mask PMOVSR writes based on supported counters
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Edgar E. Iglesias (8):
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net: cadence_gem: Disable TSU feature bit
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Jerome Forissier (1):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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Peter Maydell (2):
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Peter Maydell (2):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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hw/arm/mps2-tz: Fix MPC setting for AN524 SRAM block
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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hw/arm/mps2-tz: Assert if more than one RAM is attached to an MPC
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27
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Richard Henderson (4):
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docs/sphinx/qapidoc.py | 4 +++-
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target/arm: Fix aarch64_sve_change_el wrt EL0
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hw/arm/mps2-tz.c | 10 +++++++---
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target/arm: Define fields of ISAR registers
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2 files changed, 10 insertions(+), 4 deletions(-)
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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diff view generated by jsdifflib
New patch
[PULL 1/3] hw/arm/mps2-tz: Fix MPC setting for AN524 SRAM block
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The AN524 has three MPCs: one for the BRAM, one for the QSPI flash,
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and one for the DDR. We incorrectly set the .mpc field in the
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RAMInfo struct for the SRAM block to 1, giving it the same MPC we are
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using for the QSPI. The effect of this was that the QSPI didn't get
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mapped into the system address space at all, via an MPC or otherwise,
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and guest programs which tried to read from the QSPI would get a bus
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error. Correct the SRAM RAMInfo to indicate that it does not have an
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associated MPC.
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Fixes: 25ff112a8cc ("hw/arm/mps2-tz: Add new mps3-an524 board")
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Message-id: 20210409150527.15053-2-peter.maydell@linaro.org
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---
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hw/arm/mps2-tz.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/arm/mps2-tz.c
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+++ b/hw/arm/mps2-tz.c
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@@ -XXX,XX +XXX,XX @@ static const RAMInfo an524_raminfo[] = { {
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.name = "sram",
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.base = 0x20000000,
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.size = 32 * 4 * KiB,
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- .mpc = 1,
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+ .mpc = -1,
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.mrindex = 1,
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}, {
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/* We don't model QSPI flash yet; for now expose it as simple ROM */
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--
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2.20.1
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diff view generated by jsdifflib
New patch
[PULL 2/3] hw/arm/mps2-tz: Assert if more than one RAM is attached to an MPC
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Each board in mps2-tz.c specifies a RAMInfo[] array providing
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information about each RAM in the board. The .mpc field of the
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RAMInfo struct specifies which MPC, if any, the RAM is attached to.
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We already assert if the array doesn't have any entry for an MPC, but
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we don't diagnose the error of using the same MPC number twice (which
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is quite easy to do by accident if copy-and-pasting structure
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entries).
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Enhance find_raminfo_for_mpc() so that it detects multiple entries
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for the MPC as well as missing entries.
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Message-id: 20210409150527.15053-3-peter.maydell@linaro.org
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---
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hw/arm/mps2-tz.c | 8 ++++++--
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1 file changed, 6 insertions(+), 2 deletions(-)
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diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/arm/mps2-tz.c
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+++ b/hw/arm/mps2-tz.c
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@@ -XXX,XX +XXX,XX @@ static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc)
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{
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MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
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const RAMInfo *p;
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+ const RAMInfo *found = NULL;
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for (p = mmc->raminfo; p->name; p++) {
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if (p->mpc == mpc && !(p->flags & IS_ALIAS)) {
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- return p;
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+ /* There should only be one entry in the array for this MPC */
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+ g_assert(!found);
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+ found = p;
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}
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}
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/* if raminfo array doesn't have an entry for each MPC this is a bug */
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- g_assert_not_reached();
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+ assert(found);
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+ return found;
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}
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static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms,
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--
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2.20.1
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diff view generated by jsdifflib
New patch
[PULL 3/3] sphinx: qapidoc: Wrap "If" section body in a paragraph node
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From: John Snow <jsnow@redhat.com>
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These sections need to be wrapped in a block-level element, such as
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Paragraph in order for them to be rendered into Texinfo correctly.
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Before (e.g.):
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<section ids="qapidoc-713">
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<title>If</title>
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<literal>defined(CONFIG_REPLICATION)</literal>
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</section>
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became:
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.SS If
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\fBdefined(CONFIG_REPLICATION)\fP.SS \fBBlockdevOptionsReplication\fP (Object)
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...
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After:
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<section ids="qapidoc-713">
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<title>If</title>
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<paragraph>
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<literal>defined(CONFIG_REPLICATION)</literal>
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</paragraph>
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</section>
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becomes:
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.SS If
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.sp
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\fBdefined(CONFIG_REPLICATION)\fP
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.SS \fBBlockdevOptionsReplication\fP (Object)
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...
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Reported-by: Markus Armbruster <armbru@redhat.com>
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Tested-by: Markus Armbruster <armbru@redhat.com>
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Signed-off-by: John Snow <jsnow@redhat.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20210406141909.1992225-2-jsnow@redhat.com
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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docs/sphinx/qapidoc.py | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/docs/sphinx/qapidoc.py b/docs/sphinx/qapidoc.py
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index XXXXXXX..XXXXXXX 100644
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--- a/docs/sphinx/qapidoc.py
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+++ b/docs/sphinx/qapidoc.py
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@@ -XXX,XX +XXX,XX @@ def _nodes_for_if_section(self, ifcond):
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nodelist = []
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if ifcond:
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snode = self._make_section('If')
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- snode += self._nodes_for_ifcond(ifcond, with_if=False)
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+ snode += nodes.paragraph(
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+ '', '', *self._nodes_for_ifcond(ifcond, with_if=False)
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+ )
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nodelist.append(snode)
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return nodelist
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--
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2.20.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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