Series comparison

-[Qemu-devel] [PULL 00/17] target-arm queue
+[PULL v2 00/54] target-arm queue
-v2: dropped a couple of cadence_gem changes to ID regs that
+v1->v2: fix format-string errors on 32-bit hosts in xilinx csu dma model.
 caused new clang sanitizer warnings.
 -- PMM
-The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
+The following changes since commit 0436c55edf6b357ff56e2a5bf688df8636f83456:
-  Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
+  Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-03-08 13:51:41 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210310
-for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
+for you to fetch changes up to 81b3ddaf8772ec6f88d372e52f9b433cfa46bc46:
-  coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
+  hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() (2021-03-10 13:54:51 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
+ * Add new mps3-an547 board
- * target/arm: Fix aarch64_sve_change_el wrt EL0
+ * target/arm: Restrict v7A TCG cpus to TCG accel
- * target/arm: Define fields of ISAR registers
+ * Implement a Xilinx CSU DMA model
- * target/arm: Align cortex-r5 id_isar0
+ * hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
  * target/arm: Fix cortex-a7 id_isar0
  * net/cadence_gem: Fix various bugs, add support for new
    features that will be used by the Xilinx Versal board
  * target-arm: powerctl: Enable HVC when starting CPUs to EL2
  * target/arm: Add the Cortex-A72
  * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
  * target/arm: Mask PMOVSR writes based on supported counters
  * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
  * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
 ----------------------------------------------------------------
-Aaron Lindsay (2):
+Peter Maydell (48):
-      target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
+      clock: Add ClockEvent parameter to callbacks
-      target/arm: Mask PMOVSR writes based on supported counters
+      clock: Add ClockPreUpdate callback event type
       clock: Add clock_ns_to_ticks() function
       hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks()
       hw/arm/armsse: Introduce SSE subsystem version property
       hw/misc/iotkit-sysctl: Remove is_sse200 flag
       hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values
       hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values
       hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300
       hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
       hw/timer/sse-counter: Model the SSE Subsystem System Counter
       hw/timer/sse-timer: Model the SSE Subsystem System Timer
       hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour
       hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300
       hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300
       hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register
       hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers
       hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values
       hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc
       hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block
       hw/arm/armsse: Use an array for apb_ppc fields in the state structure
       hw/arm/armsse: Add a define for number of IRQs used by the SSE itself
       hw/arm/armsse: Add framework for data-driven device placement
       hw/arm/armsse: Move dual-timer device into data-driven framework
       hw/arm/armsse: Move watchdogs into data-driven framework
       hw/arm/armsse: Move s32ktimer into data-driven framework
       hw/arm/armsse: Move sysinfo register block into data-driven framework
       hw/arm/armsse: Move sysctl register block into data-driven framework
       hw/arm/armsse: Move PPUs into data-driven framework
       hw/arm/armsse: Add missing SSE-200 SYS_PPU
       hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo
       hw/arm/armsse: Add support for SSE variants with a system counter
       hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo
       hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block
       hw/arm/armsse: Add SSE-300 support
       hw/arm/mps2-tz: Make UART overflow IRQ board-specific
       hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate
       hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
       hw/misc/mps2-scc: Implement changes for AN547
       hw/arm/mps2-tz: Support running APB peripherals on different clock
       hw/arm/mps2-tz: Make initsvtor0 setting board-specific
       hw/arm/mps2-tz: Add new mps3-an547 board
       docs/system/arm/mps2.rst: Document the new mps3-an547 board
       tests/qtest/sse-timer-test: Add simple test of the SSE counter
       tests/qtest/sse-timer-test: Test the system timer
       tests/qtest/sse-timer-test: Test counter scaling changes
       hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_
       hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
-Edgar E. Iglesias (8):
+Philippe Mathieu-Daudé (1):
-      net: cadence_gem: Disable TSU feature bit
+      target/arm: Restrict v7A TCG cpus to TCG accel
       net: cadence_gem: Use uint32_t for 32bit descriptor words
       net: cadence_gem: Add macro with max number of descriptor words
       net: cadence_gem: Add support for extended descriptors
       net: cadence_gem: Add support for selecting the DMA MemoryRegion
       net: cadence_gem: Implement support for 64bit descriptor addresses
       target-arm: powerctl: Enable HVC when starting CPUs to EL2
       target/arm: Add the Cortex-A72
-Jerome Forissier (1):
+Xuzhou Cheng (5):
-      hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
+      hw/dma: Implement a Xilinx CSU DMA model
       hw/arm: xlnx-zynqmp: Clean up coding convention issues
       hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
       hw/ssi: xilinx_spips: Clean up coding convention issues
       hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
-Peter Maydell (2):
+ docs/devel/clocks.rst                |   71 ++-
-      target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
+ docs/system/arm/mps2.rst             |    6 +-
-      coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
+ include/hw/arm/armsse-version.h      |   42 ++
  include/hw/arm/armsse.h              |   40 +-
  include/hw/arm/xlnx-zynqmp.h         |    5 +-
  include/hw/clock.h                   |   63 ++-
  include/hw/dma/xlnx_csu_dma.h        |   52 ++
  include/hw/misc/armsse-cpu-pwrctrl.h |   40 ++
  include/hw/misc/iotkit-secctl.h      |    2 +
  include/hw/misc/iotkit-sysctl.h      |   13 +-
  include/hw/misc/iotkit-sysinfo.h     |    2 +
  include/hw/misc/mps2-fpgaio.h        |    2 +
  include/hw/qdev-clock.h              |   17 +-
  include/hw/ssi/xilinx_spips.h        |    2 +-
  include/hw/timer/sse-counter.h       |  105 ++++
  include/hw/timer/sse-timer.h         |   53 ++
  hw/adc/npcm7xx_adc.c                 |    2 +-
  hw/arm/armsse.c                      | 1008 +++++++++++++++++++++++++---------
  hw/arm/mps2-tz.c                     |  168 +++++-
  hw/arm/xlnx-zynqmp.c                 |   21 +-
  hw/char/cadence_uart.c               |    4 +-
  hw/char/ibex_uart.c                  |    4 +-
  hw/char/pl011.c                      |    5 +-
  hw/core/clock.c                      |   24 +-
  hw/core/qdev-clock.c                 |    8 +-
  hw/dma/xlnx_csu_dma.c                |  745 +++++++++++++++++++++++++
  hw/mips/cps.c                        |    2 +-
  hw/misc/armsse-cpu-pwrctrl.c         |  149 +++++
  hw/misc/bcm2835_cprman.c             |   23 +-
  hw/misc/iotkit-secctl.c              |   50 +-
  hw/misc/iotkit-sysctl.c              |  522 +++++++++++++++---
  hw/misc/iotkit-sysinfo.c             |   51 +-
  hw/misc/mps2-fpgaio.c                |   52 +-
  hw/misc/mps2-scc.c                   |   15 +-
  hw/misc/npcm7xx_clk.c                |   26 +-
  hw/misc/npcm7xx_pwm.c                |    2 +-
  hw/misc/zynq_slcr.c                  |    5 +-
  hw/ssi/xilinx_spips.c                |   33 +-
  hw/timer/cmsdk-apb-dualtimer.c       |    5 +-
  hw/timer/cmsdk-apb-timer.c           |    4 +-
  hw/timer/npcm7xx_timer.c             |    6 +-
  hw/timer/renesas_tmr.c               |   33 +-
  hw/timer/sse-counter.c               |  474 ++++++++++++++++
  hw/timer/sse-timer.c                 |  470 ++++++++++++++++
  hw/watchdog/cmsdk-apb-watchdog.c     |    5 +-
  target/arm/cpu.c                     |  335 -----------
  target/arm/cpu_tcg.c                 |  318 +++++++++++
  target/mips/cpu.c                    |    2 +-
  tests/qtest/sse-timer-test.c         |  240 ++++++++
  MAINTAINERS                          |    7 +
  hw/arm/Kconfig                       |   10 +-
  hw/dma/Kconfig                       |    4 +
  hw/dma/meson.build                   |    1 +
  hw/misc/Kconfig                      |    9 +
  hw/misc/meson.build                  |    1 +
  hw/misc/trace-events                 |    4 +
  hw/timer/Kconfig                     |    6 +
  hw/timer/meson.build                 |    2 +
  hw/timer/trace-events                |   12 +
  tests/qtest/meson.build              |    1 +
 files changed, 4537 insertions(+), 846 deletions(-)
  create mode 100644 include/hw/arm/armsse-version.h
  create mode 100644 include/hw/dma/xlnx_csu_dma.h
  create mode 100644 include/hw/misc/armsse-cpu-pwrctrl.h
  create mode 100644 include/hw/timer/sse-counter.h
  create mode 100644 include/hw/timer/sse-timer.h
  create mode 100644 hw/dma/xlnx_csu_dma.c
  create mode 100644 hw/misc/armsse-cpu-pwrctrl.c
  create mode 100644 hw/timer/sse-counter.c
  create mode 100644 hw/timer/sse-timer.c
  create mode 100644 tests/qtest/sse-timer-test.c
-Richard Henderson (4):
-      target/arm: Fix aarch64_sve_change_el wrt EL0
-      target/arm: Define fields of ISAR registers
-      target/arm: Align cortex-r5 id_isar0
-      target/arm: Fix cortex-a7 id_isar0
- include/hw/net/cadence_gem.h               |   7 +-
- target/arm/cpu.h                           |  95 ++++++++++++++-
- hw/arm/virt.c                              |   4 +
- hw/net/cadence_gem.c                       | 185 ++++++++++++++++++++---------
- target/arm/arm-powerctl.c                  |  10 ++
- target/arm/cpu.c                           |   7 +-
- target/arm/cpu64.c                         |  66 +++++++++-
- target/arm/helper.c                        |  27 +++--
- target/arm/op_helper.c                     |   6 +-
- scripts/coccinelle/inplace-byteswaps.cocci |  65 ++++++++++
-files changed, 402 insertions(+), 70 deletions(-)
- create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci

v2: dropped a couple of cadence_gem changes to ID regs that
caused new clang sanitizer warnings.

-- PMM

The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:

Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1

for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:

coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
 * target/arm: Fix aarch64_sve_change_el wrt EL0
 * target/arm: Define fields of ISAR registers
 * target/arm: Align cortex-r5 id_isar0
 * target/arm: Fix cortex-a7 id_isar0
 * net/cadence_gem: Fix various bugs, add support for new
   features that will be used by the Xilinx Versal board
 * target-arm: powerctl: Enable HVC when starting CPUs to EL2
 * target/arm: Add the Cortex-A72
 * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
 * target/arm: Mask PMOVSR writes based on supported counters
 * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
 * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls

----------------------------------------------------------------
Aaron Lindsay (2):
      target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
      target/arm: Mask PMOVSR writes based on supported counters

Edgar E. Iglesias (8):
      net: cadence_gem: Disable TSU feature bit
      net: cadence_gem: Use uint32_t for 32bit descriptor words
      net: cadence_gem: Add macro with max number of descriptor words
      net: cadence_gem: Add support for extended descriptors
      net: cadence_gem: Add support for selecting the DMA MemoryRegion
      net: cadence_gem: Implement support for 64bit descriptor addresses
      target-arm: powerctl: Enable HVC when starting CPUs to EL2
      target/arm: Add the Cortex-A72

Jerome Forissier (1):
      hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART

Peter Maydell (2):
      target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
      coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls

Richard Henderson (4):
      target/arm: Fix aarch64_sve_change_el wrt EL0
      target/arm: Define fields of ISAR registers
      target/arm: Align cortex-r5 id_isar0
      target/arm: Fix cortex-a7 id_isar0

include/hw/net/cadence_gem.h               |   7 +-
 target/arm/cpu.h                           |  95 ++++++++++++++-
 hw/arm/virt.c                              |   4 +
 hw/net/cadence_gem.c                       | 185 ++++++++++++++++++++---------
 target/arm/arm-powerctl.c                  |  10 ++
 target/arm/cpu.c                           |   7 +-
 target/arm/cpu64.c                         |  66 +++++++++-
 target/arm/helper.c                        |  27 +++--
 target/arm/op_helper.c                     |   6 +-
 scripts/coccinelle/inplace-byteswaps.cocci |  65 ++++++++++
 10 files changed, 402 insertions(+), 70 deletions(-)
 create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci

v1->v2: fix format-string errors on 32-bit hosts in xilinx csu dma model.

-- PMM

The following changes since commit 0436c55edf6b357ff56e2a5bf688df8636f83456:

Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2021-03-08 13:51:41 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210310

for you to fetch changes up to 81b3ddaf8772ec6f88d372e52f9b433cfa46bc46:

hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt() (2021-03-10 13:54:51 +0000)

----------------------------------------------------------------
target-arm queue:
 * Add new mps3-an547 board
 * target/arm: Restrict v7A TCG cpus to TCG accel
 * Implement a Xilinx CSU DMA model
 * hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()

----------------------------------------------------------------
Peter Maydell (48):
      clock: Add ClockEvent parameter to callbacks
      clock: Add ClockPreUpdate callback event type
      clock: Add clock_ns_to_ticks() function
      hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks()
      hw/arm/armsse: Introduce SSE subsystem version property
      hw/misc/iotkit-sysctl: Remove is_sse200 flag
      hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values
      hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values
      hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300
      hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
      hw/timer/sse-counter: Model the SSE Subsystem System Counter
      hw/timer/sse-timer: Model the SSE Subsystem System Timer
      hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour
      hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300
      hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300
      hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register
      hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers
      hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values
      hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc
      hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block
      hw/arm/armsse: Use an array for apb_ppc fields in the state structure
      hw/arm/armsse: Add a define for number of IRQs used by the SSE itself
      hw/arm/armsse: Add framework for data-driven device placement
      hw/arm/armsse: Move dual-timer device into data-driven framework
      hw/arm/armsse: Move watchdogs into data-driven framework
      hw/arm/armsse: Move s32ktimer into data-driven framework
      hw/arm/armsse: Move sysinfo register block into data-driven framework
      hw/arm/armsse: Move sysctl register block into data-driven framework
      hw/arm/armsse: Move PPUs into data-driven framework
      hw/arm/armsse: Add missing SSE-200 SYS_PPU
      hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo
      hw/arm/armsse: Add support for SSE variants with a system counter
      hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo
      hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block
      hw/arm/armsse: Add SSE-300 support
      hw/arm/mps2-tz: Make UART overflow IRQ board-specific
      hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate
      hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
      hw/misc/mps2-scc: Implement changes for AN547
      hw/arm/mps2-tz: Support running APB peripherals on different clock
      hw/arm/mps2-tz: Make initsvtor0 setting board-specific
      hw/arm/mps2-tz: Add new mps3-an547 board
      docs/system/arm/mps2.rst: Document the new mps3-an547 board
      tests/qtest/sse-timer-test: Add simple test of the SSE counter
      tests/qtest/sse-timer-test: Test the system timer
      tests/qtest/sse-timer-test: Test counter scaling changes
      hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_
      hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()

Philippe Mathieu-Daudé (1):
      target/arm: Restrict v7A TCG cpus to TCG accel

Xuzhou Cheng (5):
      hw/dma: Implement a Xilinx CSU DMA model
      hw/arm: xlnx-zynqmp: Clean up coding convention issues
      hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
      hw/ssi: xilinx_spips: Clean up coding convention issues
      hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips