1
v2: dropped a couple of cadence_gem changes to ID regs that
1
v2: don't delete is_surface_bgr() definition, the ppc patches
2
caused new clang sanitizer warnings.
2
that drop use of it from sm501 haven't hit master yet.
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3
4
-- PMM
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-- PMM
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5
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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The following changes since commit 9a7beaad3dbba982f7a461d676b55a5c3851d312:
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging (2021-03-05 10:47:46 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210306
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13
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to d2d837d68f7c493e4bc306a237d7f72db88a0201:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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hw/arm/mps2: Update old infocenter.arm.com URLs (2021-03-06 13:30:40 +0000)
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17
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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* sbsa-ref: remove cortex-a53 from list of supported cpus
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* sbsa-ref: add 'max' to list of allowed cpus
21
* target/arm: Fix aarch64_sve_change_el wrt EL0
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* target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
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* target/arm: Define fields of ISAR registers
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* npcm7xx: add EMC model
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* target/arm: Align cortex-r5 id_isar0
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* xlnx-zynqmp: Remove obsolete 'has_rpu' property
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* target/arm: Fix cortex-a7 id_isar0
24
* target/arm: Speed up aarch64 TBL/TBX
25
* net/cadence_gem: Fix various bugs, add support for new
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* virtio-mmio: improve virtio-mmio get_dev_path alog
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features that will be used by the Xilinx Versal board
26
* target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks
27
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Restrict v8M IDAU to TCG
28
* target/arm: Add the Cortex-A72
28
* target/arm/cpu: Update coding style to make checkpatch.pl happy
29
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
29
* musicpal, tc6393xb, omap_lcdc, tcx: drop dead code for non-32-bit-RGB surfaces
30
* target/arm: Mask PMOVSR writes based on supported counters
30
* Add new board: mps3-an524
31
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
32
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
33
31
34
----------------------------------------------------------------
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----------------------------------------------------------------
35
Aaron Lindsay (2):
33
Doug Evans (3):
36
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
34
hw/net: Add npcm7xx emc model
37
target/arm: Mask PMOVSR writes based on supported counters
35
hw/arm: Add npcm7xx emc model
36
tests/qtests: Add npcm7xx emc model test
38
37
39
Edgar E. Iglesias (8):
38
Marcin Juszkiewicz (2):
40
net: cadence_gem: Disable TSU feature bit
39
sbsa-ref: remove cortex-a53 from list of supported cpus
41
net: cadence_gem: Use uint32_t for 32bit descriptor words
40
sbsa-ref: add 'max' to list of allowed cpus
42
net: cadence_gem: Add macro with max number of descriptor words
43
net: cadence_gem: Add support for extended descriptors
44
net: cadence_gem: Add support for selecting the DMA MemoryRegion
45
net: cadence_gem: Implement support for 64bit descriptor addresses
46
target-arm: powerctl: Enable HVC when starting CPUs to EL2
47
target/arm: Add the Cortex-A72
48
41
49
Jerome Forissier (1):
42
Peter Collingbourne (1):
50
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
43
target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks
51
44
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Peter Maydell (2):
45
Peter Maydell (34):
53
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
46
hw/arm/musicpal: Remove dead code for non-32-bit-RGB surfaces
54
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
47
hw/display/tc6393xb: Remove dead code for handling non-32bpp surfaces
48
hw/display/tc6393xb: Expand out macros in template header
49
hw/display/tc6393xb: Inline tc6393xb_draw_graphic32() at its callsite
50
hw/display/omap_lcdc: Expand out macros in template header
51
hw/display/omap_lcdc: Drop broken bigendian ifdef
52
hw/display/omap_lcdc: Fix coding style issues in template header
53
hw/display/omap_lcdc: Inline template header into C file
54
hw/display/omap_lcdc: Delete unnecessary macro
55
hw/display/tcx: Drop unnecessary code for handling BGR format outputs
56
hw/arm/mps2-tz: Make SYSCLK frequency board-specific
57
hw/misc/mps2-scc: Support configurable number of OSCCLK values
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hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511
59
hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board
60
hw/misc/mps2-fpgaio: Make number of LEDs configurable by board
61
hw/misc/mps2-fpgaio: Support SWITCH register
62
hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board
63
hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type
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hw/arm/mps2-tz: Make number of IRQs board-specific
65
hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524
66
hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI
67
hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts
68
hw/arm/mps2-tz: Move device IRQ info to data structures
69
hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs
70
hw/arm/mps2-tz: Allow boards to have different PPCInfo data
71
hw/arm/mps2-tz: Make RAM arrangement board-specific
72
hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data
73
hw/arm/mps2-tz: Support ROMs as well as RAMs
74
hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo
75
hw/arm/mps2-tz: Add new mps3-an524 board
76
hw/arm/mps2-tz: Stub out USB controller for mps3-an524
77
hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524
78
docs/system/arm/mps2.rst: Document the new mps3-an524 board
79
hw/arm/mps2: Update old infocenter.arm.com URLs
55
80
56
Richard Henderson (4):
81
Philippe Mathieu-Daudé (4):
57
target/arm: Fix aarch64_sve_change_el wrt EL0
82
hw/arm/xlnx-zynqmp: Remove obsolete 'has_rpu' property
58
target/arm: Define fields of ISAR registers
83
hw/i2c/npcm7xx_smbus: Simplify npcm7xx_smbus_init()
59
target/arm: Align cortex-r5 id_isar0
84
target/arm: Restrict v8M IDAU to TCG
60
target/arm: Fix cortex-a7 id_isar0
85
target/arm/cpu: Update coding style to make checkpatch.pl happy
61
86
62
include/hw/net/cadence_gem.h | 7 +-
87
Rebecca Cran (3):
63
target/arm/cpu.h | 95 ++++++++++++++-
88
target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe
64
hw/arm/virt.c | 4 +
89
target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
65
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
90
target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU
66
target/arm/arm-powerctl.c | 10 ++
67
target/arm/cpu.c | 7 +-
68
target/arm/cpu64.c | 66 +++++++++-
69
target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
71
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
72
10 files changed, 402 insertions(+), 70 deletions(-)
73
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
74
91
92
Richard Henderson (1):
93
target/arm: Speed up aarch64 TBL/TBX
94
95
schspa (1):
96
virtio-mmio: improve virtio-mmio get_dev_path alog
97
98
docs/system/arm/mps2.rst | 24 +-
99
docs/system/arm/nuvoton.rst | 3 +-
100
hw/display/omap_lcd_template.h | 169 --------
101
hw/display/tc6393xb_template.h | 72 ----
102
include/hw/arm/armsse.h | 4 +-
103
include/hw/arm/npcm7xx.h | 2 +
104
include/hw/arm/xlnx-zynqmp.h | 2 -
105
include/hw/misc/armsse-cpuid.h | 2 +-
106
include/hw/misc/armsse-mhu.h | 2 +-
107
include/hw/misc/iotkit-secctl.h | 2 +-
108
include/hw/misc/iotkit-sysctl.h | 2 +-
109
include/hw/misc/iotkit-sysinfo.h | 2 +-
110
include/hw/misc/mps2-fpgaio.h | 8 +-
111
include/hw/misc/mps2-scc.h | 10 +-
112
include/hw/net/npcm7xx_emc.h | 286 +++++++++++++
113
target/arm/cpu.h | 15 +-
114
target/arm/helper-a64.h | 2 +-
115
target/arm/internals.h | 6 +
116
hw/arm/mps2-tz.c | 632 +++++++++++++++++++++++-----
117
hw/arm/mps2.c | 5 +
118
hw/arm/musicpal.c | 64 ++-
119
hw/arm/npcm7xx.c | 50 ++-
120
hw/arm/sbsa-ref.c | 2 +-
121
hw/arm/xlnx-zynqmp.c | 6 -
122
hw/display/omap_lcdc.c | 129 +++++-
123
hw/display/tc6393xb.c | 48 +--
124
hw/display/tcx.c | 31 +-
125
hw/i2c/npcm7xx_smbus.c | 1 -
126
hw/misc/armsse-cpuid.c | 2 +-
127
hw/misc/armsse-mhu.c | 2 +-
128
hw/misc/iotkit-sysctl.c | 2 +-
129
hw/misc/iotkit-sysinfo.c | 2 +-
130
hw/misc/mps2-fpgaio.c | 43 +-
131
hw/misc/mps2-scc.c | 93 ++++-
132
hw/net/npcm7xx_emc.c | 857 ++++++++++++++++++++++++++++++++++++++
133
hw/virtio/virtio-mmio.c | 13 +-
134
target/arm/cpu.c | 23 +-
135
target/arm/cpu64.c | 5 +
136
target/arm/cpu_tcg.c | 8 +
137
target/arm/helper-a64.c | 32 --
138
target/arm/helper.c | 39 +-
139
target/arm/mte_helper.c | 13 +-
140
target/arm/translate-a64.c | 70 +---
141
target/arm/vec_helper.c | 48 +++
142
tests/qtest/npcm7xx_emc-test.c | 862 +++++++++++++++++++++++++++++++++++++++
143
hw/net/meson.build | 1 +
144
hw/net/trace-events | 17 +
145
tests/qtest/meson.build | 3 +-
146
48 files changed, 3098 insertions(+), 618 deletions(-)
147
delete mode 100644 hw/display/omap_lcd_template.h
148
delete mode 100644 hw/display/tc6393xb_template.h
149
create mode 100644 include/hw/net/npcm7xx_emc.h
150
create mode 100644 hw/net/npcm7xx_emc.c
151
create mode 100644 tests/qtest/npcm7xx_emc-test.c
152
diff view generated by jsdifflib