| 1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx |
|---|---|---|---|
| 2 | caused new clang sanitizer warnings. | 2 | ethernet device failed 'make check' on big-endian hosts. |
| 3 | 3 | ||
| 4 | -- PMM | 4 | -- PMM |
| 5 | 5 | ||
| 6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 6 | The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf: |
| 7 | 7 | ||
| 8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | 8 | Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000) |
| 9 | 9 | ||
| 10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 11 | 11 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1 |
| 13 | 13 | ||
| 14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 14 | for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621: |
| 15 | 15 | ||
| 16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 16 | target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000) |
| 17 | 17 | ||
| 18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 19 | target-arm queue: |
| 20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 20 | * Correctly initialize MDCR_EL2.HPMN |
| 21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 21 | * versal: Use nr_apu_cpus in favor of hard coding 2 |
| 22 | * target/arm: Define fields of ISAR registers | 22 | * accel/tcg: Add URL of clang bug to comment about our workaround |
| 23 | * target/arm: Align cortex-r5 id_isar0 | 23 | * Add support for FEAT_DIT, Data Independent Timing |
| 24 | * target/arm: Fix cortex-a7 id_isar0 | 24 | * Remove GPIO from unimplemented NPCM7XX |
| 25 | * net/cadence_gem: Fix various bugs, add support for new | 25 | * Fix SCR RES1 handling |
| 26 | features that will be used by the Xilinx Versal board | 26 | * Don't migrate CPUARMState.features |
| 27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 28 | * target/arm: Add the Cortex-A72 | ||
| 29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | ||
| 30 | * target/arm: Mask PMOVSR writes based on supported counters | ||
| 31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 33 | 27 | ||
| 34 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
| 35 | Aaron Lindsay (2): | 29 | Aaron Lindsay (1): |
| 36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 30 | target/arm: Don't migrate CPUARMState.features |
| 37 | target/arm: Mask PMOVSR writes based on supported counters | ||
| 38 | 31 | ||
| 39 | Edgar E. Iglesias (8): | 32 | Daniel Müller (1): |
| 40 | net: cadence_gem: Disable TSU feature bit | 33 | target/arm: Correctly initialize MDCR_EL2.HPMN |
| 41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | ||
| 42 | net: cadence_gem: Add macro with max number of descriptor words | ||
| 43 | net: cadence_gem: Add support for extended descriptors | ||
| 44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
| 45 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
| 46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 47 | target/arm: Add the Cortex-A72 | ||
| 48 | 34 | ||
| 49 | Jerome Forissier (1): | 35 | Edgar E. Iglesias (1): |
| 50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 36 | hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 |
| 37 | |||
| 38 | Hao Wu (1): | ||
| 39 | hw/arm: Remove GPIO from unimplemented NPCM7XX | ||
| 40 | |||
| 41 | Mike Nawrocki (1): | ||
| 42 | target/arm: Fix SCR RES1 handling | ||
| 51 | 43 | ||
| 52 | Peter Maydell (2): | 44 | Peter Maydell (2): |
| 53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 45 | arm: Update infocenter.arm.com URLs |
| 54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | 46 | accel/tcg: Add URL of clang bug to comment about our workaround |
| 55 | 47 | ||
| 56 | Richard Henderson (4): | 48 | Rebecca Cran (4): |
| 57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | 49 | target/arm: Add support for FEAT_DIT, Data Independent Timing |
| 58 | target/arm: Define fields of ISAR registers | 50 | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate |
| 59 | target/arm: Align cortex-r5 id_isar0 | 51 | target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU |
| 60 | target/arm: Fix cortex-a7 id_isar0 | 52 | target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU |
| 61 | 53 | ||
| 62 | include/hw/net/cadence_gem.h | 7 +- | 54 | include/hw/dma/pl080.h | 7 ++-- |
| 63 | target/arm/cpu.h | 95 ++++++++++++++- | 55 | include/hw/misc/arm_integrator_debug.h | 2 +- |
| 64 | hw/arm/virt.c | 4 + | 56 | include/hw/ssi/pl022.h | 5 ++- |
| 65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | 57 | target/arm/cpu.h | 17 ++++++++ |
| 66 | target/arm/arm-powerctl.c | 10 ++ | 58 | target/arm/internals.h | 6 +++ |
| 67 | target/arm/cpu.c | 7 +- | 59 | accel/tcg/cpu-exec.c | 25 +++++++++--- |
| 68 | target/arm/cpu64.c | 66 +++++++++- | 60 | hw/arm/aspeed_ast2600.c | 2 +- |
| 69 | target/arm/helper.c | 27 +++-- | 61 | hw/arm/musca.c | 4 +- |
| 70 | target/arm/op_helper.c | 6 +- | 62 | hw/arm/npcm7xx.c | 8 ---- |
| 71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | 63 | hw/arm/xlnx-versal.c | 4 +- |
| 72 | 10 files changed, 402 insertions(+), 70 deletions(-) | 64 | hw/misc/arm_integrator_debug.c | 2 +- |
| 73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | 65 | hw/timer/arm_timer.c | 7 ++-- |
| 66 | target/arm/cpu.c | 4 ++ | ||
| 67 | target/arm/cpu64.c | 5 +++ | ||
| 68 | target/arm/helper-a64.c | 27 +++++++++++-- | ||
| 69 | target/arm/helper.c | 71 +++++++++++++++++++++++++++------- | ||
| 70 | target/arm/machine.c | 2 +- | ||
| 71 | target/arm/op_helper.c | 9 +---- | ||
| 72 | target/arm/translate-a64.c | 12 ++++++ | ||
| 73 | 19 files changed, 164 insertions(+), 55 deletions(-) | ||
| 74 | 74 | diff view generated by jsdifflib |