| 1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | v2: drop pvpanic-pci patches. |
|---|---|---|---|
| 2 | caused new clang sanitizer warnings. | ||
| 3 | 2 | ||
| 4 | -- PMM | 3 | The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c: |
| 5 | 4 | ||
| 6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 5 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000) |
| 7 | |||
| 8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | ||
| 9 | 6 | ||
| 10 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 11 | 8 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1 |
| 13 | 10 | ||
| 14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 11 | for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8: |
| 15 | 12 | ||
| 16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 13 | docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000) |
| 17 | 14 | ||
| 18 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 16 | target-arm queue: |
| 20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 17 | * Implement IMPDEF pauth algorithm |
| 21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 18 | * Support ARMv8.4-SEL2 |
| 22 | * target/arm: Define fields of ISAR registers | 19 | * Fix bug where we were truncating predicate vector lengths in SVE insns |
| 23 | * target/arm: Align cortex-r5 id_isar0 | 20 | * npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 24 | * target/arm: Fix cortex-a7 id_isar0 | 21 | * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 25 | * net/cadence_gem: Fix various bugs, add support for new | 22 | * docs: Build and install all the docs in a single manual |
| 26 | features that will be used by the Xilinx Versal board | ||
| 27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 28 | * target/arm: Add the Cortex-A72 | ||
| 29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | ||
| 30 | * target/arm: Mask PMOVSR writes based on supported counters | ||
| 31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 33 | 23 | ||
| 34 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 35 | Aaron Lindsay (2): | 25 | Gan Qixin (1): |
| 36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 26 | npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 37 | target/arm: Mask PMOVSR writes based on supported counters | ||
| 38 | 27 | ||
| 39 | Edgar E. Iglesias (8): | 28 | Peter Maydell (1): |
| 40 | net: cadence_gem: Disable TSU feature bit | 29 | docs: Build and install all the docs in a single manual |
| 41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | ||
| 42 | net: cadence_gem: Add macro with max number of descriptor words | ||
| 43 | net: cadence_gem: Add support for extended descriptors | ||
| 44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
| 45 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
| 46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 47 | target/arm: Add the Cortex-A72 | ||
| 48 | 30 | ||
| 49 | Jerome Forissier (1): | 31 | Philippe Mathieu-Daudé (1): |
| 50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 32 | target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 51 | 33 | ||
| 52 | Peter Maydell (2): | 34 | Richard Henderson (7): |
| 53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 35 | target/arm: Implement an IMPDEF pauth algorithm |
| 54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | 36 | target/arm: Add cpu properties to control pauth |
| 37 | target/arm: Use object_property_add_bool for "sve" property | ||
| 38 | target/arm: Introduce PREDDESC field definitions | ||
| 39 | target/arm: Update PFIRST, PNEXT for pred_desc | ||
| 40 | target/arm: Update ZIP, UZP, TRN for pred_desc | ||
| 41 | target/arm: Update REV, PUNPK for pred_desc | ||
| 55 | 42 | ||
| 56 | Richard Henderson (4): | 43 | Rémi Denis-Courmont (19): |
| 57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | 44 | target/arm: remove redundant tests |
| 58 | target/arm: Define fields of ISAR registers | 45 | target/arm: add arm_is_el2_enabled() helper |
| 59 | target/arm: Align cortex-r5 id_isar0 | 46 | target/arm: use arm_is_el2_enabled() where applicable |
| 60 | target/arm: Fix cortex-a7 id_isar0 | 47 | target/arm: use arm_hcr_el2_eff() where applicable |
| 48 | target/arm: factor MDCR_EL2 common handling | ||
| 49 | target/arm: Define isar_feature function to test for presence of SEL2 | ||
| 50 | target/arm: add 64-bit S-EL2 to EL exception table | ||
| 51 | target/arm: add MMU stage 1 for Secure EL2 | ||
| 52 | target/arm: add ARMv8.4-SEL2 system registers | ||
| 53 | target/arm: handle VMID change in secure state | ||
| 54 | target/arm: do S1_ptw_translate() before address space lookup | ||
| 55 | target/arm: translate NS bit in page-walks | ||
| 56 | target/arm: generalize 2-stage page-walk condition | ||
| 57 | target/arm: secure stage 2 translation regime | ||
| 58 | target/arm: set HPFAR_EL2.NS on secure stage 2 faults | ||
| 59 | target/arm: revector to run-time pick target EL | ||
| 60 | target/arm: Implement SCR_EL2.EEL2 | ||
| 61 | target/arm: enable Secure EL2 in max CPU | ||
| 62 | target/arm: refactor vae1_tlbmask() | ||
| 61 | 63 | ||
| 62 | include/hw/net/cadence_gem.h | 7 +- | 64 | docs/conf.py | 46 ++++- |
| 63 | target/arm/cpu.h | 95 ++++++++++++++- | 65 | docs/devel/conf.py | 15 -- |
| 64 | hw/arm/virt.c | 4 + | 66 | docs/index.html.in | 17 -- |
| 65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | 67 | docs/interop/conf.py | 28 --- |
| 66 | target/arm/arm-powerctl.c | 10 ++ | 68 | docs/meson.build | 64 +++--- |
| 67 | target/arm/cpu.c | 7 +- | 69 | docs/specs/conf.py | 16 -- |
| 68 | target/arm/cpu64.c | 66 +++++++++- | 70 | docs/system/arm/cpu-features.rst | 21 ++ |
| 69 | target/arm/helper.c | 27 +++-- | 71 | docs/system/conf.py | 28 --- |
| 70 | target/arm/op_helper.c | 6 +- | 72 | docs/tools/conf.py | 37 ---- |
| 71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | 73 | docs/user/conf.py | 15 -- |
| 72 | 10 files changed, 402 insertions(+), 70 deletions(-) | 74 | include/qemu/xxhash.h | 98 +++++++++ |
| 73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | 75 | target/arm/cpu-param.h | 2 +- |
| 76 | target/arm/cpu.h | 107 ++++++++-- | ||
| 77 | target/arm/internals.h | 45 +++++ | ||
| 78 | target/arm/cpu.c | 23 ++- | ||
| 79 | target/arm/cpu64.c | 65 ++++-- | ||
| 80 | target/arm/helper-a64.c | 8 +- | ||
| 81 | target/arm/helper.c | 414 ++++++++++++++++++++++++++------------- | ||
| 82 | target/arm/m_helper.c | 2 +- | ||
| 83 | target/arm/monitor.c | 1 + | ||
| 84 | target/arm/op_helper.c | 4 +- | ||
| 85 | target/arm/pauth_helper.c | 27 ++- | ||
| 86 | target/arm/sve_helper.c | 33 ++-- | ||
| 87 | target/arm/tlb_helper.c | 3 + | ||
| 88 | target/arm/translate-a64.c | 4 + | ||
| 89 | target/arm/translate-sve.c | 31 ++- | ||
| 90 | target/arm/translate.c | 36 +++- | ||
| 91 | tests/qtest/arm-cpu-features.c | 13 ++ | ||
| 92 | tests/qtest/npcm7xx_adc-test.c | 1 + | ||
| 93 | .gitlab-ci.yml | 4 +- | ||
| 94 | 30 files changed, 770 insertions(+), 438 deletions(-) | ||
| 95 | delete mode 100644 docs/devel/conf.py | ||
| 96 | delete mode 100644 docs/index.html.in | ||
| 97 | delete mode 100644 docs/interop/conf.py | ||
| 98 | delete mode 100644 docs/specs/conf.py | ||
| 99 | delete mode 100644 docs/system/conf.py | ||
| 100 | delete mode 100644 docs/tools/conf.py | ||
| 101 | delete mode 100644 docs/user/conf.py | ||
| 74 | 102 | diff view generated by jsdifflib |