[Qemu-devel] [PULL 00/17] target-arm queue
[PULL v2 00/29] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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v2: dropped linux-user bti series.
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caused new clang sanitizer warnings.
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-- PMM
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The following changes since commit 4c41341af76cfc85b5a6c0f87de4838672ab9f89:
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into staging (2020-10-20 11:20:36 +0100)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201020-1
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to 8128c8e8cc9489a8387c74075974f86dc0222e7f:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension (2020-10-20 16:12:01 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* Fix AArch32 SMLAD incorrect setting of Q bit
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* AArch32 VCVT fixed-point to float is always round-to-nearest
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* target/arm: Define fields of ISAR registers
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* strongarm: Fix 'time to transmit a char' unit comment
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* target/arm: Align cortex-r5 id_isar0
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* Restrict APEI tables generation to the 'virt' machine
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* target/arm: Fix cortex-a7 id_isar0
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* bcm2835: minor code cleanups
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* net/cadence_gem: Fix various bugs, add support for new
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* bcm2835: connect all IRQs from SYS_timer device
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features that will be used by the Xilinx Versal board
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* correctly flush TLBs when TBI is enabled
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* tests/qtest: Add npcm7xx timer test
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* target/arm: Add the Cortex-A72
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* loads-stores.rst: add footnote that clarifies GETPC usage
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* Fix reported EL for mte_check_fail
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* target/arm: Mask PMOVSR writes based on supported counters
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* Ignore HCR_EL2.ATA when {E2H,TGE} != 11
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* microbit_i2c: Fix coredump when dump-vmstate
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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* nseries: Fix loading kernel image on n8x0 machines
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* Implement v8.1M low-overhead-loops
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Emanuele Giuseppe Esposito (1):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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loads-stores.rst: add footnote that clarifies GETPC usage
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target/arm: Mask PMOVSR writes based on supported counters
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Edgar E. Iglesias (8):
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Havard Skinnemoen (1):
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net: cadence_gem: Disable TSU feature bit
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tests/qtest: Add npcm7xx timer test
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Jerome Forissier (1):
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Peng Liang (1):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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microbit_i2c: Fix coredump when dump-vmstate
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Peter Maydell (2):
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Peter Maydell (12):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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target/arm: Fix SMLAD incorrect setting of Q bit
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest
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decodetree: Fix codegen for non-overlapping group inside overlapping group
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target/arm: Implement v8.1M NOCP handling
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target/arm: Implement v8.1M conditional-select insns
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target/arm: Make the t32 insn[25:23]=111 group non-overlapping
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target/arm: Don't allow BLX imm for M-profile
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target/arm: Implement v8.1M branch-future insns (as NOPs)
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target/arm: Implement v8.1M low-overhead-loop instructions
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target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
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target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
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target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
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Richard Henderson (4):
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Philippe Mathieu-Daudé (9):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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hw/arm/strongarm: Fix 'time to transmit a char' unit comment
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target/arm: Define fields of ISAR registers
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hw/arm: Restrict APEI tables generation to the 'virt' machine
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target/arm: Align cortex-r5 id_isar0
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hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition
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target/arm: Fix cortex-a7 id_isar0
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hw/timer/bcm2835: Rename variable holding CTRL_STATUS register
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hw/timer/bcm2835: Support the timer COMPARE registers
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hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs
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hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
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hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
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hw/arm/nseries: Fix loading kernel image on n8x0 machines
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include/hw/net/cadence_gem.h | 7 +-
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Richard Henderson (5):
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target/arm/cpu.h | 95 ++++++++++++++-
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accel/tcg: Add tlb_flush_page_bits_by_mmuidx*
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hw/arm/virt.c | 4 +
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target/arm: Use tlb_flush_page_bits_by_mmuidx*
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm: Remove redundant mmu_idx lookup
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target/arm/arm-powerctl.c | 10 ++
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target/arm: Fix reported EL for mte_check_fail
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target/arm/cpu.c | 7 +-
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target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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docs/devel/loads-stores.rst | 8 +-
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default-configs/devices/arm-softmmu.mak | 1 -
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include/exec/exec-all.h | 36 ++
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include/hw/timer/bcm2835_systmr.h | 17 +-
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target/arm/cpu.h | 8 +
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target/arm/helper.h | 13 +
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target/arm/internals.h | 9 +-
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target/arm/m-nocp.decode | 10 +-
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target/arm/t32.decode | 50 ++-
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accel/tcg/cputlb.c | 275 +++++++++++++++-
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hw/arm/bcm2835_peripherals.c | 13 +-
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hw/arm/nseries.c | 1 +
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hw/arm/strongarm.c | 2 +-
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hw/i2c/microbit_i2c.c | 1 +
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hw/intc/bcm2835_ic.c | 4 +-
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hw/intc/bcm2836_control.c | 8 +-
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hw/timer/bcm2835_systmr.c | 57 ++--
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target/arm/cpu.c | 38 ++-
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target/arm/helper.c | 55 +++-
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target/arm/mte_helper.c | 13 +-
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target/arm/translate.c | 239 +++++++++++++-
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target/arm/vfp_helper.c | 76 +++--
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tests/qtest/npcm7xx_timer-test.c | 562 ++++++++++++++++++++++++++++++++
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hw/arm/Kconfig | 1 +
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hw/intc/trace-events | 4 +
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hw/timer/trace-events | 6 +-
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scripts/decodetree.py | 2 +-
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target/arm/translate-vfp.c.inc | 41 ++-
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tests/qtest/meson.build | 1 +
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29 files changed, 1404 insertions(+), 147 deletions(-)
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create mode 100644 tests/qtest/npcm7xx_timer-test.c
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