| 1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | v2: minor tweak to fix format string issue on Windows hosts... |
|---|---|---|---|
| 2 | caused new clang sanitizer warnings. | ||
| 3 | 2 | ||
| 4 | -- PMM | ||
| 5 | 3 | ||
| 6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 4 | The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3: |
| 7 | 5 | ||
| 8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | 6 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100) |
| 9 | 7 | ||
| 10 | are available in the Git repository at: | 8 | are available in the Git repository at: |
| 11 | 9 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 10 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201008-1 |
| 13 | 11 | ||
| 14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 12 | for you to fetch changes up to d1b6b7017572e8d82f26eb827a1dba0e8cf3cae6: |
| 15 | 13 | ||
| 16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 14 | target/arm: Make '-cpu max' have a 48-bit PA (2020-10-08 21:40:01 +0100) |
| 17 | 15 | ||
| 18 | ---------------------------------------------------------------- | 16 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 17 | target-arm queue: |
| 20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 18 | * hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer |
| 21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 19 | * hw/arm/fsl-imx25: Fix a typo |
| 22 | * target/arm: Define fields of ISAR registers | 20 | * hw/arm/sbsa-ref : Fix SMMUv3 Initialisation |
| 23 | * target/arm: Align cortex-r5 id_isar0 | 21 | * hw/arm/sbsa-ref : allocate IRQs for SMMUv3 |
| 24 | * target/arm: Fix cortex-a7 id_isar0 | 22 | * hw/char/bcm2835_aux: Allow less than 32-bit accesses |
| 25 | * net/cadence_gem: Fix various bugs, add support for new | 23 | * hw/arm/virt: Implement kvm-steal-time |
| 26 | features that will be used by the Xilinx Versal board | 24 | * target/arm: Make '-cpu max' have a 48-bit PA |
| 27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 28 | * target/arm: Add the Cortex-A72 | ||
| 29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | ||
| 30 | * target/arm: Mask PMOVSR writes based on supported counters | ||
| 31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 33 | 25 | ||
| 34 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
| 35 | Aaron Lindsay (2): | 27 | Andrew Jones (6): |
| 36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 28 | linux headers: sync to 5.9-rc7 |
| 37 | target/arm: Mask PMOVSR writes based on supported counters | 29 | target/arm/kvm: Make uncalled stubs explicitly unreachable |
| 30 | hw/arm/virt: Move post cpu realize check into its own function | ||
| 31 | hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init | ||
| 32 | tests/qtest: Restore aarch64 arm-cpu-features test | ||
| 33 | hw/arm/virt: Implement kvm-steal-time | ||
| 38 | 34 | ||
| 39 | Edgar E. Iglesias (8): | 35 | Graeme Gregory (2): |
| 40 | net: cadence_gem: Disable TSU feature bit | 36 | hw/arm/sbsa-ref : Fix SMMUv3 Initialisation |
| 41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | 37 | hw/arm/sbsa-ref : allocate IRQs for SMMUv3 |
| 42 | net: cadence_gem: Add macro with max number of descriptor words | ||
| 43 | net: cadence_gem: Add support for extended descriptors | ||
| 44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
| 45 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
| 46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 47 | target/arm: Add the Cortex-A72 | ||
| 48 | 38 | ||
| 49 | Jerome Forissier (1): | 39 | Peter Maydell (1): |
| 50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 40 | target/arm: Make '-cpu max' have a 48-bit PA |
| 51 | 41 | ||
| 52 | Peter Maydell (2): | 42 | Philippe Mathieu-Daudé (3): |
| 53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 43 | hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer |
| 54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | 44 | hw/arm/fsl-imx25: Fix a typo |
| 45 | hw/char/bcm2835_aux: Allow less than 32-bit accesses | ||
| 55 | 46 | ||
| 56 | Richard Henderson (4): | 47 | docs/system/arm/cpu-features.rst | 11 ++++ |
| 57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | 48 | include/hw/arm/fsl-imx25.h | 2 +- |
| 58 | target/arm: Define fields of ISAR registers | 49 | include/hw/arm/virt.h | 5 ++ |
| 59 | target/arm: Align cortex-r5 id_isar0 | 50 | linux-headers/linux/kvm.h | 6 ++- |
| 60 | target/arm: Fix cortex-a7 id_isar0 | 51 | target/arm/cpu.h | 4 ++ |
| 52 | target/arm/kvm_arm.h | 94 ++++++++++++++++++++++++++------- | ||
| 53 | hw/arm/sbsa-ref.c | 3 +- | ||
| 54 | hw/arm/virt.c | 111 ++++++++++++++++++++++++++++----------- | ||
| 55 | hw/char/bcm2835_aux.c | 4 +- | ||
| 56 | hw/ssi/npcm7xx_fiu.c | 12 ++--- | ||
| 57 | target/arm/cpu.c | 8 +++ | ||
| 58 | target/arm/cpu64.c | 4 ++ | ||
| 59 | target/arm/kvm.c | 16 ++++++ | ||
| 60 | target/arm/kvm64.c | 64 ++++++++++++++++++++-- | ||
| 61 | target/arm/monitor.c | 2 +- | ||
| 62 | tests/qtest/arm-cpu-features.c | 25 +++++++-- | ||
| 63 | hw/ssi/trace-events | 2 +- | ||
| 64 | tests/qtest/meson.build | 3 +- | ||
| 65 | 18 files changed, 304 insertions(+), 72 deletions(-) | ||
| 61 | 66 | ||
| 62 | include/hw/net/cadence_gem.h | 7 +- | ||
| 63 | target/arm/cpu.h | 95 ++++++++++++++- | ||
| 64 | hw/arm/virt.c | 4 + | ||
| 65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | ||
| 66 | target/arm/arm-powerctl.c | 10 ++ | ||
| 67 | target/arm/cpu.c | 7 +- | ||
| 68 | target/arm/cpu64.c | 66 +++++++++- | ||
| 69 | target/arm/helper.c | 27 +++-- | ||
| 70 | target/arm/op_helper.c | 6 +- | ||
| 71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | ||
| 72 | 10 files changed, 402 insertions(+), 70 deletions(-) | ||
| 73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | ||
| 74 | diff view generated by jsdifflib |