[Qemu-devel] [PULL 00/17] target-arm queue
[PULL v2 00/29] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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v2: added Property array terminator (which caused crashes on
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caused new clang sanitizer warnings.
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various non-x86 host architectures).
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-- PMM
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The following changes since commit ae3aa5da96f4ccf0c2a28851449d92db9fcfad71:
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge remote-tracking branch 'remotes/berrange/tags/socket-next-pull-request' into staging (2020-05-21 16:47:28 +0100)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200521-1
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to fafe7229272f39500c14845bc7ea60a8504a5a20:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 (2020-05-21 22:05:27 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* tests/acceptance: Add a test for the canon-a1100 machine
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* docs/system: Document some of the Arm development boards
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* target/arm: Define fields of ISAR registers
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* linux-user: make BKPT insn cause SIGTRAP, not be a syscall
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* target/arm: Align cortex-r5 id_isar0
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* target/arm: Remove unused GEN_NEON_INTEGER_OP macro
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* target/arm: Fix cortex-a7 id_isar0
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* fsl-imx25, fsl-imx31, fsl-imx6, fsl-imx6ul, fsl-imx7: implement watchdog
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* net/cadence_gem: Fix various bugs, add support for new
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* hw/arm: Use qemu_log_mask() instead of hw_error() in various places
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features that will be used by the Xilinx Versal board
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* ARM: PL061: Introduce N_GPIOS
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Improve clear_vec_high() usage
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* target/arm: Add the Cortex-A72
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* target/arm: Allow user-mode code to write CPSR.E via MSR
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* linux-user/arm: Reset CPSR_E when entering a signal handler
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* target/arm: Mask PMOVSR writes based on supported counters
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* linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Amanieu d'Antras (1):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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linux-user/arm: Reset CPSR_E when entering a signal handler
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target/arm: Mask PMOVSR writes based on supported counters
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Edgar E. Iglesias (8):
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Geert Uytterhoeven (1):
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net: cadence_gem: Disable TSU feature bit
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ARM: PL061: Introduce N_GPIOS
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Jerome Forissier (1):
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Guenter Roeck (8):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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hw: Move i.MX watchdog driver to hw/watchdog
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hw/watchdog: Implement full i.MX watchdog support
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hw/arm/fsl-imx25: Wire up watchdog
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hw/arm/fsl-imx31: Wire up watchdog
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hw/arm/fsl-imx6: Connect watchdog interrupts
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hw/arm/fsl-imx6ul: Connect watchdog interrupts
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hw/arm/fsl-imx7: Instantiate various unimplemented devices
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hw/arm/fsl-imx7: Connect watchdog interrupts
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Peter Maydell (2):
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Peter Maydell (12):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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docs/system: Add 'Arm' to the Integrator/CP document title
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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docs/system: Sort Arm board index into alphabetical order
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docs/system: Document Arm Versatile Express boards
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docs/system: Document the various MPS2 models
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docs/system: Document Musca boards
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linux-user/arm: BKPT should cause SIGTRAP, not be a syscall
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linux-user/arm: Remove bogus SVC 0xf0002 handling
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linux-user/arm: Handle invalid arm-specific syscalls correctly
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linux-user/arm: Fix identification of syscall numbers
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target/arm: Remove unused GEN_NEON_INTEGER_OP macro
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target/arm: Allow user-mode code to write CPSR.E via MSR
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linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
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Richard Henderson (4):
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Philippe Mathieu-Daudé (4):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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hw/arm/integratorcp: Replace hw_error() by qemu_log_mask()
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target/arm: Define fields of ISAR registers
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hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask()
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target/arm: Align cortex-r5 id_isar0
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hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()
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target/arm: Fix cortex-a7 id_isar0
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hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
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include/hw/net/cadence_gem.h | 7 +-
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Richard Henderson (2):
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target/arm/cpu.h | 95 ++++++++++++++-
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target/arm: Use tcg_gen_gvec_mov for clear_vec_high
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hw/arm/virt.c | 4 +
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target/arm: Use clear_vec_high more effectively
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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Thomas Huth (1):
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tests/acceptance: Add a test for the canon-a1100 machine
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docs/system/arm/integratorcp.rst | 4 +-
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docs/system/arm/mps2.rst | 29 +++
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docs/system/arm/musca.rst | 31 +++
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docs/system/arm/vexpress.rst | 60 ++++++
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docs/system/target-arm.rst | 20 +-
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include/hw/arm/fsl-imx25.h | 5 +
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include/hw/arm/fsl-imx31.h | 4 +
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include/hw/arm/fsl-imx6.h | 2 +-
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include/hw/arm/fsl-imx6ul.h | 2 +-
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include/hw/arm/fsl-imx7.h | 23 ++-
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include/hw/misc/imx2_wdt.h | 33 ----
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include/hw/watchdog/wdt_imx2.h | 90 +++++++++
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target/arm/cpu.h | 2 +-
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hw/arm/fsl-imx25.c | 10 +
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hw/arm/fsl-imx31.c | 6 +
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hw/arm/fsl-imx6.c | 9 +
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hw/arm/fsl-imx6ul.c | 10 +
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hw/arm/fsl-imx7.c | 35 ++++
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hw/arm/integratorcp.c | 23 ++-
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hw/arm/pxa2xx_gpio.c | 7 +-
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hw/char/xilinx_uartlite.c | 5 +-
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hw/display/pxa2xx_lcd.c | 8 +-
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hw/dma/pxa2xx_dma.c | 14 +-
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hw/gpio/pl061.c | 12 +-
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hw/misc/imx2_wdt.c | 90 ---------
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hw/timer/exynos4210_mct.c | 12 +-
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hw/watchdog/wdt_imx2.c | 304 +++++++++++++++++++++++++++++
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linux-user/arm/cpu_loop.c | 145 ++++++++------
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linux-user/arm/signal.c | 15 +-
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target/arm/translate-a64.c | 63 +++---
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target/arm/translate.c | 23 ---
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MAINTAINERS | 6 +
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hw/arm/Kconfig | 5 +
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hw/misc/Makefile.objs | 1 -
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hw/watchdog/Kconfig | 3 +
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hw/watchdog/Makefile.objs | 1 +
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tests/acceptance/machine_arm_canona1100.py | 35 ++++
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37 files changed, 855 insertions(+), 292 deletions(-)
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create mode 100644 docs/system/arm/mps2.rst
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create mode 100644 docs/system/arm/musca.rst
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create mode 100644 docs/system/arm/vexpress.rst
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delete mode 100644 include/hw/misc/imx2_wdt.h
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create mode 100644 include/hw/watchdog/wdt_imx2.h
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delete mode 100644 hw/misc/imx2_wdt.c
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create mode 100644 hw/watchdog/wdt_imx2.c
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create mode 100644 tests/acceptance/machine_arm_canona1100.py
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