| 1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | v2: |
|---|---|---|---|
| 2 | caused new clang sanitizer warnings. | 2 | * dropped target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[] |
| 3 | * renamed CLOCK_SECOND to CLOCK_PERIOD_1SEC | ||
| 3 | 4 | ||
| 4 | -- PMM | ||
| 5 | 5 | ||
| 6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 6 | The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062: |
| 7 | 7 | ||
| 8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | 8 | Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into staging (2020-04-29 15:07:33 +0100) |
| 9 | 9 | ||
| 10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 11 | 11 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200430-1 |
| 13 | 13 | ||
| 14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 14 | for you to fetch changes up to 6f7b6947a6639fff15c6a0956adf0f5ec004b789: |
| 15 | 15 | ||
| 16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 16 | hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes (2020-04-30 15:35:41 +0100) |
| 17 | 17 | ||
| 18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 19 | target-arm queue: |
| 20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 20 | * xlnx-zdma: Fix endianness handling of descriptor loading |
| 21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 21 | * nrf51: Fix last GPIO CNF address |
| 22 | * target/arm: Define fields of ISAR registers | 22 | * gicv3: Use gicr_typer in arm_gicv3_icc_reset |
| 23 | * target/arm: Align cortex-r5 id_isar0 | 23 | * msf2: Add EMAC block to SmartFusion2 SoC |
| 24 | * target/arm: Fix cortex-a7 id_isar0 | 24 | * New clock modelling framework |
| 25 | * net/cadence_gem: Fix various bugs, add support for new | 25 | * hw/arm: versal: Setup the ADMA with 128bit bus-width |
| 26 | features that will be used by the Xilinx Versal board | 26 | * Cadence: gem: fix wraparound in 64bit descriptors |
| 27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | 27 | * cadence_gem: clear RX control descriptor |
| 28 | * target/arm: Add the Cortex-A72 | 28 | * target/arm: Vectorize integer comparison vs zero |
| 29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 29 | * hw/arm/virt: dt: add kaslr-seed property |
| 30 | * target/arm: Mask PMOVSR writes based on supported counters | 30 | * hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes |
| 31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 33 | 31 | ||
| 34 | ---------------------------------------------------------------- | 32 | ---------------------------------------------------------------- |
| 35 | Aaron Lindsay (2): | 33 | Cameron Esfahani (1): |
| 36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 34 | nrf51: Fix last GPIO CNF address |
| 37 | target/arm: Mask PMOVSR writes based on supported counters | ||
| 38 | 35 | ||
| 39 | Edgar E. Iglesias (8): | 36 | Damien Hedde (7): |
| 40 | net: cadence_gem: Disable TSU feature bit | 37 | hw/core/clock-vmstate: define a vmstate entry for clock state |
| 41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | 38 | qdev: add clock input&output support to devices. |
| 42 | net: cadence_gem: Add macro with max number of descriptor words | 39 | qdev-clock: introduce an init array to ease the device construction |
| 43 | net: cadence_gem: Add support for extended descriptors | 40 | hw/misc/zynq_slcr: add clock generation for uarts |
| 44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | 41 | hw/char/cadence_uart: add clock support |
| 45 | net: cadence_gem: Implement support for 64bit descriptor addresses | 42 | hw/arm/xilinx_zynq: connect uart clocks to slcr |
| 46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | 43 | qdev-monitor: print the device's clock with info qtree |
| 47 | target/arm: Add the Cortex-A72 | ||
| 48 | 44 | ||
| 49 | Jerome Forissier (1): | 45 | Edgar E. Iglesias (7): |
| 50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 46 | dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness |
| 47 | dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness | ||
| 48 | hw/arm: versal: Setup the ADMA with 128bit bus-width | ||
| 49 | device_tree: Allow name wildcards in qemu_fdt_node_path() | ||
| 50 | device_tree: Constify compat in qemu_fdt_node_path() | ||
| 51 | hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102 | ||
| 52 | hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes | ||
| 53 | |||
| 54 | Jerome Forissier (2): | ||
| 55 | hw/arm/virt: dt: move creation of /secure-chosen to create_fdt() | ||
| 56 | hw/arm/virt: dt: add kaslr-seed property | ||
| 57 | |||
| 58 | Keqian Zhu (2): | ||
| 59 | bugfix: Use gicr_typer in arm_gicv3_icc_reset | ||
| 60 | Typo: Correct the name of CPU hotplug memory region | ||
| 51 | 61 | ||
| 52 | Peter Maydell (2): | 62 | Peter Maydell (2): |
| 53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 63 | hw/core/clock: introduce clock object |
| 54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | 64 | docs/clocks: add device's clock documentation |
| 55 | 65 | ||
| 56 | Richard Henderson (4): | 66 | Philippe Mathieu-Daudé (2): |
| 57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | 67 | target/arm: Restrict the Address Translate write operation to TCG accel |
| 58 | target/arm: Define fields of ISAR registers | 68 | target/arm/cpu: Update coding style to make checkpatch.pl happy |
| 59 | target/arm: Align cortex-r5 id_isar0 | ||
| 60 | target/arm: Fix cortex-a7 id_isar0 | ||
| 61 | 69 | ||
| 62 | include/hw/net/cadence_gem.h | 7 +- | 70 | Ramon Fried (2): |
| 63 | target/arm/cpu.h | 95 ++++++++++++++- | 71 | Cadence: gem: fix wraparound in 64bit descriptors |
| 64 | hw/arm/virt.c | 4 + | 72 | net: cadence_gem: clear RX control descriptor |
| 65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | ||
| 66 | target/arm/arm-powerctl.c | 10 ++ | ||
| 67 | target/arm/cpu.c | 7 +- | ||
| 68 | target/arm/cpu64.c | 66 +++++++++- | ||
| 69 | target/arm/helper.c | 27 +++-- | ||
| 70 | target/arm/op_helper.c | 6 +- | ||
| 71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | ||
| 72 | 10 files changed, 402 insertions(+), 70 deletions(-) | ||
| 73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | ||
| 74 | 73 | ||
| 74 | Richard Henderson (1): | ||
| 75 | target/arm: Vectorize integer comparison vs zero | ||
| 76 | |||
| 77 | Subbaraya Sundeep (3): | ||
| 78 | hw/net: Add Smartfusion2 emac block | ||
| 79 | msf2: Add EMAC block to SmartFusion2 SoC | ||
| 80 | tests/boot_linux_console: Add ethernet test to SmartFusion2 | ||
| 81 | |||
| 82 | Thomas Huth (1): | ||
| 83 | target/arm: Make cpu_register() available for other files | ||
| 84 | |||
| 85 | hw/core/Makefile.objs | 2 + | ||
| 86 | hw/net/Makefile.objs | 1 + | ||
| 87 | tests/Makefile.include | 1 + | ||
| 88 | include/hw/arm/msf2-soc.h | 2 + | ||
| 89 | include/hw/char/cadence_uart.h | 1 + | ||
| 90 | include/hw/clock.h | 225 +++++++++++++ | ||
| 91 | include/hw/gpio/nrf51_gpio.h | 2 +- | ||
| 92 | include/hw/net/msf2-emac.h | 53 +++ | ||
| 93 | include/hw/qdev-clock.h | 159 +++++++++ | ||
| 94 | include/hw/qdev-core.h | 12 + | ||
| 95 | include/sysemu/device_tree.h | 5 +- | ||
| 96 | target/arm/cpu-qom.h | 9 +- | ||
| 97 | target/arm/helper.h | 27 +- | ||
| 98 | target/arm/translate.h | 5 + | ||
| 99 | device_tree.c | 4 +- | ||
| 100 | hw/acpi/cpu.c | 2 +- | ||
| 101 | hw/arm/msf2-soc.c | 26 +- | ||
| 102 | hw/arm/virt.c | 20 +- | ||
| 103 | hw/arm/xilinx_zynq.c | 57 +++- | ||
| 104 | hw/arm/xlnx-versal.c | 2 + | ||
| 105 | hw/arm/xlnx-zcu102.c | 39 ++- | ||
| 106 | hw/char/cadence_uart.c | 73 +++- | ||
| 107 | hw/core/clock-vmstate.c | 25 ++ | ||
| 108 | hw/core/clock.c | 130 ++++++++ | ||
| 109 | hw/core/qdev-clock.c | 185 +++++++++++ | ||
| 110 | hw/core/qdev.c | 12 + | ||
| 111 | hw/dma/xlnx-zdma.c | 25 +- | ||
| 112 | hw/intc/arm_gicv3_kvm.c | 4 +- | ||
| 113 | hw/misc/zynq_slcr.c | 172 +++++++++- | ||
| 114 | hw/net/cadence_gem.c | 16 +- | ||
| 115 | hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++ | ||
| 116 | qdev-monitor.c | 9 + | ||
| 117 | target/arm/cpu.c | 19 +- | ||
| 118 | target/arm/cpu64.c | 8 +- | ||
| 119 | target/arm/helper.c | 17 + | ||
| 120 | target/arm/neon_helper.c | 24 -- | ||
| 121 | target/arm/translate-a64.c | 64 +--- | ||
| 122 | target/arm/translate.c | 256 ++++++++++++-- | ||
| 123 | target/arm/vec_helper.c | 25 ++ | ||
| 124 | MAINTAINERS | 2 + | ||
| 125 | docs/devel/clocks.rst | 391 ++++++++++++++++++++++ | ||
| 126 | docs/devel/index.rst | 1 + | ||
| 127 | hw/char/trace-events | 3 + | ||
| 128 | hw/core/trace-events | 7 + | ||
| 129 | tests/acceptance/boot_linux_console.py | 15 +- | ||
| 130 | 45 files changed, 2533 insertions(+), 193 deletions(-) | ||
| 131 | create mode 100644 include/hw/clock.h | ||
| 132 | create mode 100644 include/hw/net/msf2-emac.h | ||
| 133 | create mode 100644 include/hw/qdev-clock.h | ||
| 134 | create mode 100644 hw/core/clock-vmstate.c | ||
| 135 | create mode 100644 hw/core/clock.c | ||
| 136 | create mode 100644 hw/core/qdev-clock.c | ||
| 137 | create mode 100644 hw/net/msf2-emac.c | ||
| 138 | create mode 100644 docs/devel/clocks.rst | ||
| 139 | diff view generated by jsdifflib |