[Qemu-devel] [PULL 00/17] target-arm queue
[PULL 0/6] target-arm queue
1
v2: dropped a couple of cadence_gem changes to ID regs that
1
A handful of bugfixes before rc1 tomorrow...
2
caused new clang sanitizer warnings.
3
2
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
6
The following changes since commit f9fe8450fa7cdc6268e05c93fa258f583f4514b7:
7
7
8
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
8
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request' into staging (2020-03-30 11:32:01 +0100)
9
9
10
are available in the Git repository at:
10
are available in the Git repository at:
11
11
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200330
13
13
14
for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
14
for you to fetch changes up to 88828bf133b64b7a860c166af3423ef1a47c5d3b:
15
15
16
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
16
target/arm: fix incorrect current EL bug in aarch32 exception emulation (2020-03-30 13:55:32 +0100)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
20
* hw/arm/orangepi: check for potential NULL pointer when calling blk_is_available
21
* target/arm: Fix aarch64_sve_change_el wrt EL0
21
* hw/misc/allwinner-h3-dramc: enforce 64-bit multiply when calculating row mirror address
22
* target/arm: Define fields of ISAR registers
22
* docs/conf.py: Raise ConfigError for bad Sphinx Python version
23
* target/arm: Align cortex-r5 id_isar0
23
* hw/arm/xlnx-zynqmp.c: Avoid memory leak in error-return path
24
* target/arm: Fix cortex-a7 id_isar0
24
* hw/arm/xlnx-zynqmp.c: Add missing error-propagation code
25
* net/cadence_gem: Fix various bugs, add support for new
25
* target/arm: fix incorrect current EL bug in aarch32 exception emulation
26
features that will be used by the Xilinx Versal board
27
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
28
* target/arm: Add the Cortex-A72
29
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
30
* target/arm: Mask PMOVSR writes based on supported counters
31
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
32
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
33
26
34
----------------------------------------------------------------
27
----------------------------------------------------------------
35
Aaron Lindsay (2):
28
Changbin Du (1):
36
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
29
target/arm: fix incorrect current EL bug in aarch32 exception emulation
37
target/arm: Mask PMOVSR writes based on supported counters
38
30
39
Edgar E. Iglesias (8):
31
Niek Linnenbank (2):
40
net: cadence_gem: Disable TSU feature bit
32
hw/arm/orangepi: check for potential NULL pointer when calling blk_is_available
41
net: cadence_gem: Use uint32_t for 32bit descriptor words
33
hw/misc/allwinner-h3-dramc: enforce 64-bit multiply when calculating row mirror address
42
net: cadence_gem: Add macro with max number of descriptor words
43
net: cadence_gem: Add support for extended descriptors
44
net: cadence_gem: Add support for selecting the DMA MemoryRegion
45
net: cadence_gem: Implement support for 64bit descriptor addresses
46
target-arm: powerctl: Enable HVC when starting CPUs to EL2
47
target/arm: Add the Cortex-A72
48
34
49
Jerome Forissier (1):
35
Peter Maydell (3):
50
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
36
docs/conf.py: Raise ConfigError for bad Sphinx Python version
37
hw/arm/xlnx-zynqmp.c: Avoid memory leak in error-return path
38
hw/arm/xlnx-zynqmp.c: Add missing error-propagation code
51
39
52
Peter Maydell (2):
40
hw/arm/orangepi.c | 2 +-
53
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
41
hw/arm/xlnx-zynqmp.c | 27 ++++++++++++++++++++++++++-
54
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
42
hw/misc/allwinner-h3-dramc.c | 4 ++--
43
target/arm/helper.c | 5 ++++-
44
docs/conf.py | 9 +++++----
45
5 files changed, 38 insertions(+), 9 deletions(-)
55
46
56
Richard Henderson (4):
57
target/arm: Fix aarch64_sve_change_el wrt EL0
58
target/arm: Define fields of ISAR registers
59
target/arm: Align cortex-r5 id_isar0
60
target/arm: Fix cortex-a7 id_isar0
61
62
include/hw/net/cadence_gem.h | 7 +-
63
target/arm/cpu.h | 95 ++++++++++++++-
64
hw/arm/virt.c | 4 +
65
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
66
target/arm/arm-powerctl.c | 10 ++
67
target/arm/cpu.c | 7 +-
68
target/arm/cpu64.c | 66 +++++++++-
69
target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
71
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
72
10 files changed, 402 insertions(+), 70 deletions(-)
73
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
74
diff view generated by jsdifflib
New patch
[PULL 1/6] hw/arm/orangepi: check for potential NULL pointer when calling blk_is_available
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
2
3
The Orange Pi PC initialization function needs to verify that the SD card
4
block backend is usable before calling the Boot ROM setup routine. When
5
calling blk_is_available() the input parameter should not be NULL.
6
This commit ensures that blk_is_available is only called with non-NULL input.
7
8
Reported-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
10
Message-id: 20200322205439.15231-1-nieklinnenbank@gmail.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/orangepi.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/orangepi.c
20
+++ b/hw/arm/orangepi.c
21
@@ -XXX,XX +XXX,XX @@ static void orangepi_init(MachineState *machine)
22
machine->ram);
23
24
/* Load target kernel or start using BootROM */
25
- if (!machine->kernel_filename && blk_is_available(blk)) {
26
+ if (!machine->kernel_filename && blk && blk_is_available(blk)) {
27
/* Use Boot ROM to copy data from SD card to SRAM */
28
allwinner_h3_bootrom_setup(h3, blk);
29
}
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
New patch
[PULL 2/6] hw/misc/allwinner-h3-dramc: enforce 64-bit multiply when calculating row mirror address
1
From: Niek Linnenbank <nieklinnenbank@gmail.com>
1
2
3
The allwinner_h3_dramc_map_rows function simulates row addressing behavior
4
when bootloader software attempts to detect the amount of available SDRAM.
5
6
Currently the line that calculates the 64-bit address of the mirrored row
7
uses a signed 32-bit multiply operation that in theory could result in the
8
upper 32-bit be all 1s. This commit ensures that the row mirror address
9
is calculated using only 64-bit operations.
10
11
Reported-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
13
Message-id: 20200323192944.5967-1-nieklinnenbank@gmail.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/misc/allwinner-h3-dramc.c | 4 ++--
18
1 file changed, 2 insertions(+), 2 deletions(-)
19
20
diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/misc/allwinner-h3-dramc.c
23
+++ b/hw/misc/allwinner-h3-dramc.c
24
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,
25
26
} else if (row_bits_actual) {
27
/* Row bits not matching ram_size, install the rows mirror */
28
- hwaddr row_mirror = s->ram_addr + ((1 << (row_bits_actual +
29
- bank_bits)) * page_size);
30
+ hwaddr row_mirror = s->ram_addr + ((1ULL << (row_bits_actual +
31
+ bank_bits)) * page_size);
32
33
memory_region_set_enabled(&s->row_mirror_alias, true);
34
memory_region_set_address(&s->row_mirror_alias, row_mirror);
35
--
36
2.20.1
37
38
diff view generated by jsdifflib
New patch
[PULL 3/6] docs/conf.py: Raise ConfigError for bad Sphinx Python version
1
Raise ConfigError rather than VersionRequirementError when we detect
2
that the Python being used by Sphinx is too old.
1
3
4
Currently the way we flag the Python version problem up to the user
5
causes Sphinx to print an unnecessary Python stack trace as well as
6
the information about the problem; in most versions of Sphinx this is
7
unavoidable.
8
9
The upstream Sphinx developers kindly added a feature to allow
10
conf.py to report errors to the user without the backtrace:
11
https://github.com/sphinx-doc/sphinx/commit/be608ca2313fc08eb842f3dc19d0f5d2d8227d08
12
but the exception type they chose for this was ConfigError.
13
14
Switch to ConfigError, which won't make any difference with currently
15
deployed Sphinx versions, but will be prettier one day when the user
16
is using a Sphinx version with the new feature.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: John Snow <jsnow@redhat.com>
20
Message-id: 20200313163616.30674-1-peter.maydell@linaro.org
21
---
22
docs/conf.py | 9 +++++----
23
1 file changed, 5 insertions(+), 4 deletions(-)
24
25
diff --git a/docs/conf.py b/docs/conf.py
26
index XXXXXXX..XXXXXXX 100644
27
--- a/docs/conf.py
28
+++ b/docs/conf.py
29
@@ -XXX,XX +XXX,XX @@
30
import os
31
import sys
32
import sphinx
33
-from sphinx.errors import VersionRequirementError
34
+from sphinx.errors import ConfigError
35
36
# Make Sphinx fail cleanly if using an old Python, rather than obscurely
37
# failing because some code in one of our extensions doesn't work there.
38
-# Unfortunately this doesn't display very neatly (there's an unavoidable
39
-# Python backtrace) but at least the information gets printed...
40
+# In newer versions of Sphinx this will display nicely; in older versions
41
+# Sphinx will also produce a Python backtrace but at least the information
42
+# gets printed...
43
if sys.version_info < (3,5):
44
- raise VersionRequirementError(
45
+ raise ConfigError(
46
"QEMU requires a Sphinx that uses Python 3.5 or better\n")
47
48
# The per-manual conf.py will set qemu_docdir for a single-manual build;
49
--
50
2.20.1
51
52
diff view generated by jsdifflib
New patch
[PULL 4/6] hw/arm/xlnx-zynqmp.c: Avoid memory leak in error-return path
1
In xlnx_zynqmp_realize() if the attempt to realize the SD
2
controller object fails then the error-return path will leak
3
the 'bus_name' string. Fix this by deferring the allocation
4
until after the realize has succeeded.
1
5
6
Fixes: Coverity CID 1421911
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200324134947.15384-2-peter.maydell@linaro.org
12
---
13
hw/arm/xlnx-zynqmp.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
16
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/xlnx-zynqmp.c
19
+++ b/hw/arm/xlnx-zynqmp.c
20
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
21
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
22
23
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
24
- char *bus_name = g_strdup_printf("sd-bus%d", i);
25
+ char *bus_name;
26
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
27
Object *sdhci = OBJECT(&s->sdhci[i]);
28
29
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
30
sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
31
32
/* Alias controller SD bus to the SoC itself */
33
+ bus_name = g_strdup_printf("sd-bus%d", i);
34
object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
35
&error_abort);
36
g_free(bus_name);
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
New patch
[PULL 5/6] hw/arm/xlnx-zynqmp.c: Add missing error-propagation code
1
In some places in xlnx_zynqmp_realize() we were putting an
2
error into our local Error*, but forgetting to check for
3
failure and pass it back to the caller. Add the missing code.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20200324134947.15384-3-peter.maydell@linaro.org
10
---
11
hw/arm/xlnx-zynqmp.c | 24 ++++++++++++++++++++++++
12
1 file changed, 24 insertions(+)
13
14
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/xlnx-zynqmp.c
17
+++ b/hw/arm/xlnx-zynqmp.c
18
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
19
* - eMMC Specification Version 4.51
20
*/
21
object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
22
+ if (err) {
23
+ error_propagate(errp, err);
24
+ return;
25
+ }
26
object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
27
+ if (err) {
28
+ error_propagate(errp, err);
29
+ return;
30
+ }
31
object_property_set_uint(sdhci, UHS_I, "uhs", &err);
32
+ if (err) {
33
+ error_propagate(errp, err);
34
+ return;
35
+ }
36
object_property_set_bool(sdhci, true, "realized", &err);
37
if (err) {
38
error_propagate(errp, err);
39
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
40
gchar *bus_name;
41
42
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
43
+ if (err) {
44
+ error_propagate(errp, err);
45
+ return;
46
+ }
47
48
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
49
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
50
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
51
}
52
53
object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
54
+ if (err) {
55
+ error_propagate(errp, err);
56
+ return;
57
+ }
58
sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
59
sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
60
sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
61
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
62
63
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
64
object_property_set_uint(OBJECT(&s->gdma[i]), 128, "bus-width", &err);
65
+ if (err) {
66
+ error_propagate(errp, err);
67
+ return;
68
+ }
69
object_property_set_bool(OBJECT(&s->gdma[i]), true, "realized", &err);
70
if (err) {
71
error_propagate(errp, err);
72
--
73
2.20.1
74
75
diff view generated by jsdifflib
New patch
[PULL 6/6] target/arm: fix incorrect current EL bug in aarch32 exception emulation
1
From: Changbin Du <changbin.du@gmail.com>
1
2
3
The arm_current_el() should be invoked after mode switching. Otherwise, we
4
get a wrong current EL value, since current EL is also determined by
5
current mode.
6
7
Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry")
8
Signed-off-by: Changbin Du <changbin.du@gmail.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200328140232.17278-1-changbin.du@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/helper.c | 5 ++++-
14
1 file changed, 4 insertions(+), 1 deletion(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
21
22
/* Change the CPU state so as to actually take the exception. */
23
switch_mode(env, new_mode);
24
- new_el = arm_current_el(env);
25
26
/*
27
* For exceptions taken to AArch32 we must clear the SS bit in both
28
@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
29
env->condexec_bits = 0;
30
/* Switch to the new mode, and to the correct instruction set. */
31
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
32
+
33
+ /* This must be after mode switching. */
34
+ new_el = arm_current_el(env);
35
+
36
/* Set new mode endianness */
37
env->uncached_cpsr &= ~CPSR_E;
38
if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
39
--
40
2.20.1
41
42
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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