[Qemu-devel] [PULL 00/17] target-arm queue
[PULL v4 00/20] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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v1->v2: add system/index to docs/index.rst
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caused new clang sanitizer warnings.
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v2->v3: fix format string issues for OSX
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v3->v4: actually fix format string issues, somehow
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I failed to actually put the change into git :-(
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-- PMM
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The following changes since commit b7c359c748a2e3ccb97a184b9739feb2cd48de2f:
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request' into staging (2020-01-23 14:38:43 +0000)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200123-4
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to e9d20b55b2e4c8400143554f0e83e4e1fcb9bd0f:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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hw/arm/exynos4210: Connect serial port DMA busy signals with pl330 (2020-01-23 16:34:15 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* fix bug in PAuth emulation
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* add PMU to Cortex-R5, Cortex-R5F
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* target/arm: Define fields of ISAR registers
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* qemu-nbd: Convert documentation to rST
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* target/arm: Align cortex-r5 id_isar0
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* qemu-block-drivers: Convert documentation to rST
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* target/arm: Fix cortex-a7 id_isar0
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* Fix Exynos4210 UART DMA support
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* net/cadence_gem: Fix various bugs, add support for new
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* Various minor code cleanups
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features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Andrew Jones (1):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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target/arm/arch_dump: Add SVE notes
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target/arm: Mask PMOVSR writes based on supported counters
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Edgar E. Iglesias (8):
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Clement Deschamps (1):
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net: cadence_gem: Disable TSU feature bit
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target/arm: add PMU feature to cortex-r5 and cortex-r5f
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Jerome Forissier (1):
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Guenter Roeck (8):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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dma/pl330: Convert to support tracing
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hw/core/or-irq: Increase limit of or-lines to 48
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hw/arm/exynos4210: Fix DMA initialization
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hw/char/exynos4210_uart: Convert to support tracing
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hw/char/exynos4210_uart: Implement post_load function
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hw/char/exynos4210_uart: Implement Rx FIFO level triggers and timeouts
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hw/char/exynos4210_uart: Add receive DMA support
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hw/arm/exynos4210: Connect serial port DMA busy signals with pl330
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Peter Maydell (2):
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Keqian Zhu (2):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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hw/acpi: Remove extra indent in ACPI GED hotplug cb
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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hw/arm: Use helper function to trigger hotplug handler plug
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Richard Henderson (4):
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Peter Maydell (3):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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qemu-nbd: Convert invocation documentation to rST
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target/arm: Define fields of ISAR registers
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docs: Create stub system manual
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target/arm: Align cortex-r5 id_isar0
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qemu-block-drivers: Convert to rST
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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Philippe Mathieu-Daudé (1):
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/misc/stm32f4xx_syscfg: Fix copy/paste error
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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Richard Henderson (3):
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tests/tcg/aarch64: Fix compilation parameters for pauth-%
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tests/tcg/aarch64: Add pauth-3
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tests/tcg/aarch64: Add pauth-4
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Vincent Dehors (1):
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target/arm: Fix PAuth sbox functions
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Makefile | 37 +-
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tests/tcg/aarch64/Makefile.softmmu-target | 5 +-
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tests/tcg/aarch64/Makefile.target | 3 +-
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include/elf.h | 1 +
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include/hw/arm/exynos4210.h | 4 +
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include/hw/or-irq.h | 2 +-
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target/arm/cpu.h | 25 +
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hw/acpi/generic_event_device.c | 2 +-
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hw/arm/exynos4210.c | 77 ++-
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hw/arm/virt.c | 6 +-
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hw/char/exynos4210_uart.c | 245 +++++---
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hw/dma/pl330.c | 88 +--
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hw/misc/stm32f4xx_syscfg.c | 2 +-
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target/arm/arch_dump.c | 124 +++-
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target/arm/cpu.c | 1 +
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target/arm/kvm64.c | 24 -
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target/arm/pauth_helper.c | 4 +-
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tests/tcg/aarch64/pauth-1.c | 2 -
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tests/tcg/aarch64/pauth-2.c | 2 -
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tests/tcg/aarch64/pauth-4.c | 25 +
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tests/tcg/aarch64/system/pauth-3.c | 40 ++
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MAINTAINERS | 1 +
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docs/index.html.in | 1 +
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docs/index.rst | 2 +-
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docs/interop/conf.py | 4 +-
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docs/interop/index.rst | 1 +
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docs/interop/qemu-nbd.rst | 263 ++++++++
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docs/interop/qemu-option-trace.rst.inc | 30 +
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docs/qemu-block-drivers.texi | 889 ---------------------------
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docs/system/conf.py | 22 +
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docs/system/index.rst | 17 +
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docs/system/qemu-block-drivers.rst | 985 ++++++++++++++++++++++++++++++
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hw/char/trace-events | 20 +
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hw/dma/trace-events | 24 +
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qemu-doc.texi | 18 -
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qemu-nbd.texi | 214 -------
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qemu-option-trace.texi | 4 +
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qemu-options.hx | 2 +-
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38 files changed, 1898 insertions(+), 1318 deletions(-)
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create mode 100644 tests/tcg/aarch64/pauth-4.c
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create mode 100644 tests/tcg/aarch64/system/pauth-3.c
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create mode 100644 docs/interop/qemu-nbd.rst
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create mode 100644 docs/interop/qemu-option-trace.rst.inc
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delete mode 100644 docs/qemu-block-drivers.texi
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create mode 100644 docs/system/conf.py
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create mode 100644 docs/system/index.rst
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create mode 100644 docs/system/qemu-block-drivers.rst
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delete mode 100644 qemu-nbd.texi
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Patchew 2.1-devel-b67e4c2

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