| 1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | Changes v1->v2: dropped rth's patchset as it causes an |
|---|---|---|---|
| 2 | caused new clang sanitizer warnings. | 2 | assert with the qemu-armeb binary. |
| 3 | 3 | ||
| 4 | I expect I'll do another pullreq at the end of the week. | ||
| 5 | |||
| 6 | thanks | ||
| 4 | -- PMM | 7 | -- PMM |
| 5 | 8 | ||
| 6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 9 | The following changes since commit f9bec781379dd7ccf9d01b4b6a79a9ec82c192e5: |
| 7 | 10 | ||
| 8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | 11 | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20191022' into staging (2019-10-22 13:45:09 +0100) |
| 9 | 12 | ||
| 10 | are available in the Git repository at: | 13 | are available in the Git repository at: |
| 11 | 14 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 15 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191022-1 |
| 13 | 16 | ||
| 14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 17 | for you to fetch changes up to f9c1fe62a16f32c3d6fe34c2856475052b7efdaf: |
| 15 | 18 | ||
| 16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 19 | hw/arm/digic4: Inline digic4_board_setup_ram() function (2019-10-22 16:50:38 +0100) |
| 17 | 20 | ||
| 18 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 22 | target-arm queue: |
| 20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 23 | * Fix sign-extension for SMLAL* instructions |
| 21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 24 | * aspeed: Add an AST2600 eval board |
| 22 | * target/arm: Define fields of ISAR registers | 25 | * Various ptimer device conversions to new transaction API |
| 23 | * target/arm: Align cortex-r5 id_isar0 | 26 | * Add a dummy Samsung SDHCI controller model to exynos4 boards |
| 24 | * target/arm: Fix cortex-a7 id_isar0 | 27 | * Minor refactorings of RAM creation for some arm boards |
| 25 | * net/cadence_gem: Fix various bugs, add support for new | ||
| 26 | features that will be used by the Xilinx Versal board | ||
| 27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 28 | * target/arm: Add the Cortex-A72 | ||
| 29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | ||
| 30 | * target/arm: Mask PMOVSR writes based on supported counters | ||
| 31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 33 | 28 | ||
| 34 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
| 35 | Aaron Lindsay (2): | 30 | Cédric Le Goater (1): |
| 36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 31 | aspeed: Add an AST2600 eval board |
| 37 | target/arm: Mask PMOVSR writes based on supported counters | ||
| 38 | 32 | ||
| 39 | Edgar E. Iglesias (8): | 33 | Guenter Roeck (1): |
| 40 | net: cadence_gem: Disable TSU feature bit | 34 | hw/timer/exynos4210_mct: Initialize ptimer before starting it |
| 41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | ||
| 42 | net: cadence_gem: Add macro with max number of descriptor words | ||
| 43 | net: cadence_gem: Add support for extended descriptors | ||
| 44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
| 45 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
| 46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 47 | target/arm: Add the Cortex-A72 | ||
| 48 | 35 | ||
| 49 | Jerome Forissier (1): | 36 | Peter Maydell (7): |
| 50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 37 | hw/timer/arm_mptimer.c: Undo accidental rename of arm_mptimer_init() |
| 38 | hw/timer/puv3_ost.c: Switch to transaction-based ptimer API | ||
| 39 | hw/timer/sh_timer: Switch to transaction-based ptimer API | ||
| 40 | hw/timer/lm32_timer: Switch to transaction-based ptimer API | ||
| 41 | hw/timer/altera_timer.c: Switch to transaction-based ptimer API | ||
| 42 | hw/watchdog/etraxfs_timer.c: Switch to transaction-based ptimer API | ||
| 43 | hw/m68k/mcf5208.c: Switch to transaction-based ptimer API | ||
| 51 | 44 | ||
| 52 | Peter Maydell (2): | 45 | Philippe Mathieu-Daudé (9): |
| 53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 46 | hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions |
| 54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | 47 | hw/sd/sdhci: Add dummy Samsung SDHCI controller |
| 48 | hw/arm/exynos4210: Use the Samsung s3c SDHCI controller | ||
| 49 | hw/arm/xilinx_zynq: Use the IEC binary prefix definitions | ||
| 50 | hw/arm/mps2: Use the IEC binary prefix definitions | ||
| 51 | hw/arm/collie: Create the RAM in the board | ||
| 52 | hw/arm/omap2: Create the RAM in the board | ||
| 53 | hw/arm/omap1: Create the RAM in the board | ||
| 54 | hw/arm/digic4: Inline digic4_board_setup_ram() function | ||
| 55 | 55 | ||
| 56 | Richard Henderson (4): | 56 | Richard Henderson (1): |
| 57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | 57 | target/arm: Fix sign-extension for SMLAL* |
| 58 | target/arm: Define fields of ISAR registers | ||
| 59 | target/arm: Align cortex-r5 id_isar0 | ||
| 60 | target/arm: Fix cortex-a7 id_isar0 | ||
| 61 | 58 | ||
| 62 | include/hw/net/cadence_gem.h | 7 +- | 59 | hw/arm/strongarm.h | 4 +-- |
| 63 | target/arm/cpu.h | 95 ++++++++++++++- | 60 | include/hw/arm/aspeed.h | 1 + |
| 64 | hw/arm/virt.c | 4 + | 61 | include/hw/arm/omap.h | 10 +++---- |
| 65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | 62 | include/hw/sd/sdhci.h | 2 ++ |
| 66 | target/arm/arm-powerctl.c | 10 ++ | 63 | hw/arm/aspeed.c | 23 ++++++++++++++++ |
| 67 | target/arm/cpu.c | 7 +- | 64 | hw/arm/collie.c | 8 ++++-- |
| 68 | target/arm/cpu64.c | 66 +++++++++- | 65 | hw/arm/digic_boards.c | 9 ++----- |
| 69 | target/arm/helper.c | 27 +++-- | 66 | hw/arm/exynos4210.c | 2 +- |
| 70 | target/arm/op_helper.c | 6 +- | 67 | hw/arm/mps2-tz.c | 3 ++- |
| 71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | 68 | hw/arm/mps2.c | 3 ++- |
| 72 | 10 files changed, 402 insertions(+), 70 deletions(-) | 69 | hw/arm/nseries.c | 10 ++++--- |
| 73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | 70 | hw/arm/omap1.c | 12 ++++----- |
| 71 | hw/arm/omap2.c | 13 ++++----- | ||
| 72 | hw/arm/omap_sx1.c | 8 ++++-- | ||
| 73 | hw/arm/palm.c | 8 ++++-- | ||
| 74 | hw/arm/strongarm.c | 7 +---- | ||
| 75 | hw/arm/xilinx_zynq.c | 3 ++- | ||
| 76 | hw/m68k/mcf5208.c | 9 ++++--- | ||
| 77 | hw/sd/sdhci.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++- | ||
| 78 | hw/timer/altera_timer.c | 13 ++++++--- | ||
| 79 | hw/timer/arm_mptimer.c | 4 +-- | ||
| 80 | hw/timer/etraxfs_timer.c | 23 +++++++++------- | ||
| 81 | hw/timer/exynos4210_mct.c | 2 +- | ||
| 82 | hw/timer/lm32_timer.c | 13 ++++++--- | ||
| 83 | hw/timer/puv3_ost.c | 9 ++++--- | ||
| 84 | hw/timer/sh_timer.c | 13 ++++++--- | ||
| 85 | target/arm/translate.c | 4 ++- | ||
| 86 | 27 files changed, 198 insertions(+), 86 deletions(-) | ||
| 74 | 87 | diff view generated by jsdifflib |