| 1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | A last collection of patches to squeeze in before rc0. |
|---|---|---|---|
| 2 | caused new clang sanitizer warnings. | 2 | The patches from me are all bugfixes. Philippe's are just |
| 3 | code-movement, but I wanted to get these into 4.1 because | ||
| 4 | that kind of patch is so painful to have to rebase. | ||
| 5 | (The diffstat is huge but it's just code moving from file to file.) | ||
| 3 | 6 | ||
| 7 | v2: fix up for clash with the qapi refactor which only | ||
| 8 | showed up in a build-from-clean. | ||
| 9 | |||
| 10 | thanks | ||
| 4 | -- PMM | 11 | -- PMM |
| 5 | 12 | ||
| 6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | ||
| 7 | 13 | ||
| 8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | 14 | The following changes since commit c3e1d838cfa5aac1a6210c8ddf182d0ef7d95dd8: |
| 15 | |||
| 16 | Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190704-pull-request' into staging (2019-07-04 16:43:13 +0100) | ||
| 9 | 17 | ||
| 10 | are available in the Git repository at: | 18 | are available in the Git repository at: |
| 11 | 19 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 20 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190704-1 |
| 13 | 21 | ||
| 14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 22 | for you to fetch changes up to 89a11ff756410aecb87d2c774df6e45dbf4105c1: |
| 15 | 23 | ||
| 16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 24 | target/arm: Correct VMOV_imm_dp handling of short vectors (2019-07-04 17:25:30 +0100) |
| 17 | 25 | ||
| 18 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 27 | target-arm queue: |
| 20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 28 | * more code-movement to separate TCG-only functions into their own files |
| 21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 29 | * Correct VMOV_imm_dp handling of short vectors |
| 22 | * target/arm: Define fields of ISAR registers | 30 | * Execute Thumb instructions when their condbits are 0xf |
| 23 | * target/arm: Align cortex-r5 id_isar0 | 31 | * armv7m_systick: Forbid non-privileged accesses |
| 24 | * target/arm: Fix cortex-a7 id_isar0 | 32 | * Use _ra versions of cpu_stl_data() in v7M helpers |
| 25 | * net/cadence_gem: Fix various bugs, add support for new | 33 | * v8M: Check state of exception being returned from |
| 26 | features that will be used by the Xilinx Versal board | 34 | * v8M: Forcibly clear negative-priority exceptions on deactivate |
| 27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 28 | * target/arm: Add the Cortex-A72 | ||
| 29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | ||
| 30 | * target/arm: Mask PMOVSR writes based on supported counters | ||
| 31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 33 | 35 | ||
| 34 | ---------------------------------------------------------------- | 36 | ---------------------------------------------------------------- |
| 35 | Aaron Lindsay (2): | 37 | Peter Maydell (6): |
| 36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 38 | arm v8M: Forcibly clear negative-priority exceptions on deactivate |
| 37 | target/arm: Mask PMOVSR writes based on supported counters | 39 | target/arm: v8M: Check state of exception being returned from |
| 40 | target/arm: Use _ra versions of cpu_stl_data() in v7M helpers | ||
| 41 | hw/timer/armv7m_systick: Forbid non-privileged accesses | ||
| 42 | target/arm: Execute Thumb instructions when their condbits are 0xf | ||
| 43 | target/arm: Correct VMOV_imm_dp handling of short vectors | ||
| 38 | 44 | ||
| 39 | Edgar E. Iglesias (8): | 45 | Philippe Mathieu-Daudé (3): |
| 40 | net: cadence_gem: Disable TSU feature bit | 46 | target/arm: Move debug routines to debug_helper.c |
| 41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | 47 | target/arm: Restrict semi-hosting to TCG |
| 42 | net: cadence_gem: Add macro with max number of descriptor words | 48 | target/arm/helper: Move M profile routines to m_helper.c |
| 43 | net: cadence_gem: Add support for extended descriptors | ||
| 44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
| 45 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
| 46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 47 | target/arm: Add the Cortex-A72 | ||
| 48 | 49 | ||
| 49 | Jerome Forissier (1): | 50 | target/arm/Makefile.objs | 5 +- |
| 50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 51 | target/arm/cpu.h | 7 + |
| 52 | hw/intc/armv7m_nvic.c | 54 +- | ||
| 53 | hw/timer/armv7m_systick.c | 26 +- | ||
| 54 | target/arm/cpu.c | 9 +- | ||
| 55 | target/arm/debug_helper.c | 311 +++++ | ||
| 56 | target/arm/helper.c | 2646 +-------------------------------------- | ||
| 57 | target/arm/m_helper.c | 2679 ++++++++++++++++++++++++++++++++++++++++ | ||
| 58 | target/arm/op_helper.c | 295 ----- | ||
| 59 | target/arm/translate-vfp.inc.c | 2 +- | ||
| 60 | target/arm/translate.c | 15 +- | ||
| 61 | 11 files changed, 3096 insertions(+), 2953 deletions(-) | ||
| 62 | create mode 100644 target/arm/debug_helper.c | ||
| 63 | create mode 100644 target/arm/m_helper.c | ||
| 51 | 64 | ||
| 52 | Peter Maydell (2): | ||
| 53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 55 | |||
| 56 | Richard Henderson (4): | ||
| 57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | ||
| 58 | target/arm: Define fields of ISAR registers | ||
| 59 | target/arm: Align cortex-r5 id_isar0 | ||
| 60 | target/arm: Fix cortex-a7 id_isar0 | ||
| 61 | |||
| 62 | include/hw/net/cadence_gem.h | 7 +- | ||
| 63 | target/arm/cpu.h | 95 ++++++++++++++- | ||
| 64 | hw/arm/virt.c | 4 + | ||
| 65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | ||
| 66 | target/arm/arm-powerctl.c | 10 ++ | ||
| 67 | target/arm/cpu.c | 7 +- | ||
| 68 | target/arm/cpu64.c | 66 +++++++++- | ||
| 69 | target/arm/helper.c | 27 +++-- | ||
| 70 | target/arm/op_helper.c | 6 +- | ||
| 71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | ||
| 72 | 10 files changed, 402 insertions(+), 70 deletions(-) | ||
| 73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | ||
| 74 | diff view generated by jsdifflib |