[Qemu-devel] [PULL 00/17] target-arm queue
[Qemu-devel] [PULL 0/2] target-arm queue
1
v2: dropped a couple of cadence_gem changes to ID regs that
1
Two last-minute regression fixes that I thought we might as well
2
caused new clang sanitizer warnings.
2
squeeze in before rc1.
3
3
4
thanks
4
-- PMM
5
-- PMM
5
6
6
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
7
The following changes since commit d37bfe142382fa8258531c47b4519387c77cd169:
7
8
8
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
9
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc1-v2' into staging (2019-03-26 10:27:20 +0000)
9
10
10
are available in the Git repository at:
11
are available in the Git repository at:
11
12
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190326
13
14
14
for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
15
for you to fetch changes up to c99ef792dc9ec6d8a5061428faf396ea9ceb8f57:
15
16
16
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
17
gdbstub: fix vCont packet handling when no thread is specified (2019-03-26 12:53:26 +0000)
17
18
18
----------------------------------------------------------------
19
----------------------------------------------------------------
19
target-arm queue:
20
target-arm queue:
20
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
21
* Set SIMDMISC and FPMISC for 32-bit -cpu max
21
* target/arm: Fix aarch64_sve_change_el wrt EL0
22
(fixes regression from 3.1)
22
* target/arm: Define fields of ISAR registers
23
* fix vCont packet handling when no thread is specified
23
* target/arm: Align cortex-r5 id_isar0
24
* target/arm: Fix cortex-a7 id_isar0
25
* net/cadence_gem: Fix various bugs, add support for new
26
features that will be used by the Xilinx Versal board
27
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
28
* target/arm: Add the Cortex-A72
29
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
30
* target/arm: Mask PMOVSR writes based on supported counters
31
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
32
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
33
24
34
----------------------------------------------------------------
25
----------------------------------------------------------------
35
Aaron Lindsay (2):
26
Luc Michel (1):
36
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
27
gdbstub: fix vCont packet handling when no thread is specified
37
target/arm: Mask PMOVSR writes based on supported counters
38
28
39
Edgar E. Iglesias (8):
29
Richard Henderson (1):
40
net: cadence_gem: Disable TSU feature bit
30
target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max
41
net: cadence_gem: Use uint32_t for 32bit descriptor words
42
net: cadence_gem: Add macro with max number of descriptor words
43
net: cadence_gem: Add support for extended descriptors
44
net: cadence_gem: Add support for selecting the DMA MemoryRegion
45
net: cadence_gem: Implement support for 64bit descriptor addresses
46
target-arm: powerctl: Enable HVC when starting CPUs to EL2
47
target/arm: Add the Cortex-A72
48
31
49
Jerome Forissier (1):
32
gdbstub.c | 14 ++++++++++++--
50
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
33
target/arm/cpu.c | 5 +++++
34
2 files changed, 17 insertions(+), 2 deletions(-)
51
35
52
Peter Maydell (2):
53
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
54
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
55
56
Richard Henderson (4):
57
target/arm: Fix aarch64_sve_change_el wrt EL0
58
target/arm: Define fields of ISAR registers
59
target/arm: Align cortex-r5 id_isar0
60
target/arm: Fix cortex-a7 id_isar0
61
62
include/hw/net/cadence_gem.h | 7 +-
63
target/arm/cpu.h | 95 ++++++++++++++-
64
hw/arm/virt.c | 4 +
65
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
66
target/arm/arm-powerctl.c | 10 ++
67
target/arm/cpu.c | 7 +-
68
target/arm/cpu64.c | 66 +++++++++-
69
target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
71
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
72
10 files changed, 402 insertions(+), 70 deletions(-)
73
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
74
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 1/2] target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Fixes: https://bugs.launchpad.net/bugs/1821430
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20190325161338.6536-1-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.c | 5 +++++
11
1 file changed, 5 insertions(+)
12
13
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.c
16
+++ b/target/arm/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
18
t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
19
cpu->isar.id_isar6 = t;
20
21
+ t = cpu->isar.mvfr2;
22
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
23
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
24
+ cpu->isar.mvfr2 = t;
25
+
26
t = cpu->id_mmfr4;
27
t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
28
cpu->id_mmfr4 = t;
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 2/2] gdbstub: fix vCont packet handling when no thread is specified
1
From: Luc Michel <luc.michel@greensocs.com>
1
2
3
The vCont packet accepts a series of actions, each being applied on a
4
given thread ID. Giving no thread ID for an action is valid and means
5
"all threads".
6
7
This commit fixes vCont packets being incorrectly rejected when no
8
thread ID was given for an action.
9
10
In multiprocess mode, the GDB Remote Protocol specification is unclear
11
on what "all threads" means. We choose to apply the action on all
12
threads of all attached processes.
13
14
This commit is based on the initial fix by Lucien Murray-Pitts.
15
16
Fixes: e40e5204af8388
17
Reported-by: Lucien Murray-Pitts <lucienmp_antispam@yahoo.com>
18
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
19
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20190325110452.6756-1-luc.michel@greensocs.com
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
24
gdbstub.c | 14 ++++++++++++--
25
1 file changed, 12 insertions(+), 2 deletions(-)
26
27
diff --git a/gdbstub.c b/gdbstub.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/gdbstub.c
30
+++ b/gdbstub.c
31
@@ -XXX,XX +XXX,XX @@ static int gdb_handle_vcont(GDBState *s, const char *p)
32
uint32_t pid, tid;
33
GDBProcess *process;
34
CPUState *cpu;
35
+ GDBThreadIdKind kind;
36
#ifdef CONFIG_USER_ONLY
37
int max_cpus = 1; /* global variable max_cpus exists only in system mode */
38
39
@@ -XXX,XX +XXX,XX @@ static int gdb_handle_vcont(GDBState *s, const char *p)
40
goto out;
41
}
42
43
- if (*p++ != ':') {
44
+ if (*p == '\0' || *p == ';') {
45
+ /*
46
+ * No thread specifier, action is on "all threads". The
47
+ * specification is unclear regarding the process to act on. We
48
+ * choose all processes.
49
+ */
50
+ kind = GDB_ALL_PROCESSES;
51
+ } else if (*p++ == ':') {
52
+ kind = read_thread_id(p, &p, &pid, &tid);
53
+ } else {
54
res = -ENOTSUP;
55
goto out;
56
}
57
58
- switch (read_thread_id(p, &p, &pid, &tid)) {
59
+ switch (kind) {
60
case GDB_READ_THREAD_ERR:
61
res = -EINVAL;
62
goto out;
63
--
64
2.20.1
65
66
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.