| 1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | v2: drop a couple of RTH's patches that he wants to rework. |
|---|---|---|---|
| 2 | caused new clang sanitizer warnings. | ||
| 3 | 2 | ||
| 4 | -- PMM | 3 | The following changes since commit 0266c739abbed804deabb4ccde2aa449466ac3b4: |
| 5 | 4 | ||
| 6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 5 | Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' into staging (2019-02-14 18:33:00 +0000) |
| 7 | |||
| 8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | ||
| 9 | 6 | ||
| 10 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 11 | 8 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190215 |
| 13 | 10 | ||
| 14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 11 | for you to fetch changes up to 0f8b09b22234460cb5b8766a25066cf6b5f06842: |
| 15 | 12 | ||
| 16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 13 | gdbstub: Send a reply to the vKill packet. (2019-02-15 09:56:41 +0000) |
| 17 | 14 | ||
| 18 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 16 | target-arm queue: |
| 20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 17 | * gdbstub: Send a reply to the vKill packet |
| 21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 18 | * Improve codegen for neon min/max and saturating arithmetic |
| 22 | * target/arm: Define fields of ISAR registers | 19 | * Fix a bug in clearing FPSCR exception status bits |
| 23 | * target/arm: Align cortex-r5 id_isar0 | 20 | * hw/arm/armsse: Fix miswiring of expansion IRQs |
| 24 | * target/arm: Fix cortex-a7 id_isar0 | 21 | * hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 |
| 25 | * net/cadence_gem: Fix various bugs, add support for new | 22 | * MAINTAINERS: Remove Peter Crosthwaite from various entries |
| 26 | features that will be used by the Xilinx Versal board | 23 | * arm: Allow system registers for KVM guests to be changed by QEMU code |
| 27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | 24 | * linux-user: support HWCAP_CPUID which exposes ID registers to user code |
| 28 | * target/arm: Add the Cortex-A72 | 25 | * Fix bug in 128-bit cmpxchg for BE Arm guests |
| 29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 26 | * Implement (no-op) HACR_EL2 |
| 30 | * target/arm: Mask PMOVSR writes based on supported counters | 27 | * Fix CRn to be 14 for PMEVTYPER/PMEVCNTR |
| 31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 33 | 28 | ||
| 34 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
| 35 | Aaron Lindsay (2): | 30 | Aaron Lindsay OS (1): |
| 36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 31 | target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR |
| 37 | target/arm: Mask PMOVSR writes based on supported counters | ||
| 38 | 32 | ||
| 39 | Edgar E. Iglesias (8): | 33 | Alex Bennée (5): |
| 40 | net: cadence_gem: Disable TSU feature bit | 34 | target/arm: relax permission checks for HWCAP_CPUID registers |
| 41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | 35 | target/arm: expose CPUID registers to userspace |
| 42 | net: cadence_gem: Add macro with max number of descriptor words | 36 | target/arm: expose MPIDR_EL1 to userspace |
| 43 | net: cadence_gem: Add support for extended descriptors | 37 | target/arm: expose remaining CPUID registers as RAZ |
| 44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | 38 | linux-user/elfload: enable HWCAP_CPUID for AArch64 |
| 45 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
| 46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 47 | target/arm: Add the Cortex-A72 | ||
| 48 | 39 | ||
| 49 | Jerome Forissier (1): | 40 | Catherine Ho (1): |
| 50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 41 | target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be |
| 51 | 42 | ||
| 52 | Peter Maydell (2): | 43 | Peter Maydell (5): |
| 53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 44 | target/arm: Implement HACR_EL2 |
| 54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | 45 | arm: Allow system registers for KVM guests to be changed by QEMU code |
| 46 | MAINTAINERS: Remove Peter Crosthwaite from various entries | ||
| 47 | hw/intc/armv7m_nvic: Allow byte accesses to SHPR1 | ||
| 48 | hw/arm/armsse: Fix miswiring of expansion IRQs | ||
| 55 | 49 | ||
| 56 | Richard Henderson (4): | 50 | Richard Henderson (12): |
| 57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | 51 | target/arm: Rely on optimization within tcg_gen_gvec_or |
| 58 | target/arm: Define fields of ISAR registers | 52 | target/arm: Use vector minmax expanders for aarch64 |
| 59 | target/arm: Align cortex-r5 id_isar0 | 53 | target/arm: Use vector minmax expanders for aarch32 |
| 60 | target/arm: Fix cortex-a7 id_isar0 | 54 | target/arm: Use tcg integer min/max primitives for neon |
| 55 | target/arm: Remove neon min/max helpers | ||
| 56 | target/arm: Fix vfp_gdb_get/set_reg vs FPSCR | ||
| 57 | target/arm: Fix arm_cpu_dump_state vs FPSCR | ||
| 58 | target/arm: Split out flags setting from vfp compares | ||
| 59 | target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] | ||
| 60 | target/arm: Split out FPSCR.QC to a vector field | ||
| 61 | target/arm: Use vector operations for saturation | ||
| 62 | target/arm: Add missing clear_tail calls | ||
| 61 | 63 | ||
| 62 | include/hw/net/cadence_gem.h | 7 +- | 64 | Sandra Loosemore (1): |
| 63 | target/arm/cpu.h | 95 ++++++++++++++- | 65 | gdbstub: Send a reply to the vKill packet. |
| 64 | hw/arm/virt.c | 4 + | ||
| 65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | ||
| 66 | target/arm/arm-powerctl.c | 10 ++ | ||
| 67 | target/arm/cpu.c | 7 +- | ||
| 68 | target/arm/cpu64.c | 66 +++++++++- | ||
| 69 | target/arm/helper.c | 27 +++-- | ||
| 70 | target/arm/op_helper.c | 6 +- | ||
| 71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | ||
| 72 | 10 files changed, 402 insertions(+), 70 deletions(-) | ||
| 73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | ||
| 74 | 66 | ||
| 67 | target/arm/cpu.h | 50 +++++++++- | ||
| 68 | target/arm/helper.h | 45 ++++++--- | ||
| 69 | target/arm/translate.h | 4 + | ||
| 70 | gdbstub.c | 1 + | ||
| 71 | hw/arm/armsse.c | 2 +- | ||
| 72 | hw/intc/armv7m_nvic.c | 4 +- | ||
| 73 | linux-user/elfload.c | 1 + | ||
| 74 | target/arm/helper-a64.c | 4 +- | ||
| 75 | target/arm/helper.c | 228 ++++++++++++++++++++++++++++++++++++--------- | ||
| 76 | target/arm/kvm32.c | 20 +--- | ||
| 77 | target/arm/kvm64.c | 2 + | ||
| 78 | target/arm/machine.c | 2 +- | ||
| 79 | target/arm/neon_helper.c | 14 +-- | ||
| 80 | target/arm/translate-a64.c | 77 ++++++--------- | ||
| 81 | target/arm/translate-sve.c | 6 +- | ||
| 82 | target/arm/translate.c | 219 ++++++++++++++++++++++++++++++++++--------- | ||
| 83 | target/arm/vec_helper.c | 134 +++++++++++++++++++++++++- | ||
| 84 | MAINTAINERS | 4 - | ||
| 85 | 18 files changed, 622 insertions(+), 195 deletions(-) | ||
| 86 | diff view generated by jsdifflib |