[Qemu-devel] [PULL 00/17] target-arm queue
[Qemu-devel] [PULL v2 00/48] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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v1->v2 changes: fix a clang warning about bitfields;
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caused new clang sanitizer warnings.
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drop a patch from Julia that I accidentally included
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(it will likely be in a future series).
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-- PMM
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The following changes since commit a8d2b0685681e2f291faaa501efbbd76875f8ec8:
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190118' into staging (2019-01-18 16:56:15 +0000)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190121
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to 0d4bfd7df809863b1f45fad35229fb9419527d06:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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target/arm: Implement PMSWINC (2019-01-21 10:38:56 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* hw/char/stm32f2xx_usart: Do not update data register when device is disabled
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
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* target/arm: Define fields of ISAR registers
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* target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
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* target/arm: Align cortex-r5 id_isar0
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* ftgmac100: implement the new MDIO interface on Aspeed SoC
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* target/arm: Fix cortex-a7 id_isar0
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* implement the ARMv8.3-PAuth extension
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* net/cadence_gem: Fix various bugs, add support for new
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* improve emulation of the ARM PMU
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features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Aaron Lindsay (13):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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migration: Add post_save function to VMStateDescription
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target/arm: Mask PMOVSR writes based on supported counters
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target/arm: Reorganize PMCCNTR accesses
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target/arm: Swap PMU values before/after migrations
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target/arm: Filter cycle counter based on PMCCFILTR_EL0
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target/arm: Allow AArch32 access for PMCCFILTR
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target/arm: Implement PMOVSSET
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target/arm: Define FIELDs for ID_DFR0
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target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
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target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
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target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
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target/arm: PMU: Add instruction and cycle events
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target/arm: PMU: Set PMCR.N to 4
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target/arm: Implement PMSWINC
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Edgar E. Iglesias (8):
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Alexander Graf (1):
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net: cadence_gem: Disable TSU feature bit
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target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Jerome Forissier (1):
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Cédric Le Goater (1):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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ftgmac100: implement the new MDIO interface on Aspeed SoC
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Peter Maydell (2):
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Eric Auger (1):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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Richard Henderson (4):
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Philippe Mathieu-Daudé (1):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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hw/char/stm32f2xx_usart: Do not update data register when device is disabled
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target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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Richard Henderson (31):
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target/arm/cpu.h | 95 ++++++++++++++-
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target/arm: Add state for the ARMv8.3-PAuth extension
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hw/arm/virt.c | 4 +
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target/arm: Add SCTLR bits through ARMv8.5
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm: Add PAuth active bit to tbflags
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target/arm/arm-powerctl.c | 10 ++
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target/arm: Introduce raise_exception_ra
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target/arm/cpu.c | 7 +-
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target/arm: Add PAuth helpers
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target/arm/cpu64.c | 66 +++++++++-
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target/arm: Decode PAuth within system hint space
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target/arm/helper.c | 27 +++--
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target/arm: Rearrange decode in disas_data_proc_1src
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target/arm/op_helper.c | 6 +-
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target/arm: Decode PAuth within disas_data_proc_1src
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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target/arm: Decode PAuth within disas_data_proc_2src
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10 files changed, 402 insertions(+), 70 deletions(-)
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target/arm: Move helper_exception_return to helper-a64.c
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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target/arm: Add new_pc argument to helper_exception_return
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target/arm: Rearrange decode in disas_uncond_b_reg
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target/arm: Decode PAuth within disas_uncond_b_reg
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target/arm: Decode Load/store register (pac)
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target/arm: Move cpu_mmu_index out of line
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target/arm: Introduce arm_mmu_idx
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target/arm: Introduce arm_stage1_mmu_idx
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target/arm: Create ARMVAParameters and helpers
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target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
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target/arm: Export aa64_va_parameters to internals.h
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target/arm: Add aa64_va_parameters_both
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target/arm: Decode TBID from TCR
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target/arm: Reuse aa64_va_parameters for setting tbflags
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target/arm: Implement pauth_strip
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target/arm: Implement pauth_auth
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target/arm: Implement pauth_addpac
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target/arm: Implement pauth_computepac
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target/arm: Add PAuth system registers
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target/arm: Enable PAuth for -cpu max
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target/arm: Enable PAuth for user-only
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target/arm: Tidy TBI handling in gen_a64_set_pc
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target/arm/Makefile.objs | 1 +
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include/hw/acpi/acpi-defs.h | 2 +
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include/migration/vmstate.h | 1 +
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target/arm/cpu.h | 244 +++++----
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target/arm/helper-a64.h | 14 +
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target/arm/helper.h | 1 -
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target/arm/internals.h | 77 +++
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target/arm/translate.h | 5 +-
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hw/arm/virt-acpi-build.c | 1 +
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hw/char/stm32f2xx_usart.c | 3 +-
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hw/net/ftgmac100.c | 80 ++-
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migration/vmstate.c | 13 +-
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target/arm/cpu.c | 19 +-
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target/arm/cpu64.c | 68 ++-
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target/arm/helper-a64.c | 155 ++++++
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target/arm/helper.c | 1222 +++++++++++++++++++++++++++++++++----------
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target/arm/machine.c | 24 +
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target/arm/op_helper.c | 174 +-----
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target/arm/pauth_helper.c | 497 ++++++++++++++++++
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target/arm/translate-a64.c | 537 ++++++++++++++++---
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docs/devel/migration.rst | 9 +-
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21 files changed, 2515 insertions(+), 632 deletions(-)
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create mode 100644 target/arm/pauth_helper.c
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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