1
v2: dropped a couple of cadence_gem changes to ID regs that
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Last arm patches for rc3...
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caused new clang sanitizer warnings.
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2
3
thanks
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-- PMM
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-- PMM
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5
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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The following changes since commit 72138f9bf5d8c316043b0d2cc7a674f70930cf95:
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging (2018-11-26 11:46:04 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181126
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13
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to 58102ce7fbb2362aa53984aabcf684d164da2d9d:
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15
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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net: cadence_gem: Remove incorrect assert() (2018-11-26 13:41:42 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* some updates to MAINTAINERS file entries
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* cadence_gem: Remove an incorrect assert()
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* target/arm: Define fields of ISAR registers
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* target/arm: Align cortex-r5 id_isar0
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* target/arm: Fix cortex-a7 id_isar0
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* net/cadence_gem: Fix various bugs, add support for new
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features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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22
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Edgar E. Iglesias (1):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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net: cadence_gem: Remove incorrect assert()
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target/arm: Mask PMOVSR writes based on supported counters
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26
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Edgar E. Iglesias (8):
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Eric Auger (1):
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net: cadence_gem: Disable TSU feature bit
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MAINTAINERS: Add an ARM SMMU section
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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29
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Jerome Forissier (1):
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Thomas Huth (1):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
31
MAINTAINERS: Assign some more files in the hw/arm/ directory
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32
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Peter Maydell (2):
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hw/net/cadence_gem.c | 1 -
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
34
MAINTAINERS | 23 +++++++++++++++++++++++
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
35
2 files changed, 23 insertions(+), 1 deletion(-)
55
36
56
Richard Henderson (4):
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target/arm: Fix aarch64_sve_change_el wrt EL0
58
target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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diff view generated by jsdifflib
New patch
1
From: Thomas Huth <thuth@redhat.com>
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2
3
I apparently missed some more files and even a complete machine (the
4
"imx25-pdk") in my previous patch... but now we should hopefully have
5
a completely coverage for all available ARM boards.
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7
Fixes: 95a5db3ae5698b49c63144610ad02913e780c828
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Signed-off-by: Thomas Huth <thuth@redhat.com>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Message-id: 1542782568-20059-1-git-send-email-thuth@redhat.com
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
13
MAINTAINERS | 16 ++++++++++++++++
14
1 file changed, 16 insertions(+)
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diff --git a/MAINTAINERS b/MAINTAINERS
17
index XXXXXXX..XXXXXXX 100644
18
--- a/MAINTAINERS
19
+++ b/MAINTAINERS
20
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
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S: Odd Fixes
22
F: hw/arm/gumstix.c
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24
+i.MX25 PDK
25
+M: Peter Maydell <peter.maydell@linaro.org>
26
+R: Jean-Christophe Dubois <jcd@tribudubois.net>
27
+L: qemu-arm@nongnu.org
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+S: Odd Fixes
29
+F: hw/arm/fsl-imx25.c
30
+F: hw/arm/imx25_pdk.c
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+F: hw/misc/imx25_ccm.c
32
+F: include/hw/arm/fsl-imx25.h
33
+F: include/hw/misc/imx25_ccm.h
34
+
35
i.MX31 (kzm)
36
M: Peter Chubb <peter.chubb@nicta.com.au>
37
M: Peter Maydell <peter.maydell@linaro.org>
38
@@ -XXX,XX +XXX,XX @@ R: Andrew Baumann <Andrew.Baumann@microsoft.com>
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R: Philippe Mathieu-Daudé <f4bug@amsat.org>
40
L: qemu-arm@nongnu.org
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S: Odd Fixes
42
+F: hw/arm/raspi.c
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F: hw/arm/raspi_platform.h
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F: hw/*/bcm283*
45
F: include/hw/arm/raspi*
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@@ -XXX,XX +XXX,XX @@ F: hw/arm/spitz.c
47
F: hw/arm/tosa.c
48
F: hw/arm/z2.c
49
F: hw/*/pxa2xx*
50
+F: hw/display/tc6393xb.c
51
+F: hw/gpio/max7310.c
52
+F: hw/gpio/zaurus.c
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F: hw/misc/mst_fpga.c
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F: include/hw/arm/pxa.h
55
+F: include/hw/arm/sharpsl.h
56
57
SABRELITE / i.MX6
58
M: Peter Maydell <peter.maydell@linaro.org>
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--
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2.19.1
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diff view generated by jsdifflib
New patch
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
Add a new ARM SMMU section and set Eric Auger as the maintainer
4
for ARM SMMU emulation sources.
5
6
Signed-off-by: Eric Auger <eric.auger@redhat.com>
7
Message-id: 20181122180143.14237-1-eric.auger@redhat.com
8
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
11
MAINTAINERS | 7 +++++++
12
1 file changed, 7 insertions(+)
13
14
diff --git a/MAINTAINERS b/MAINTAINERS
15
index XXXXXXX..XXXXXXX 100644
16
--- a/MAINTAINERS
17
+++ b/MAINTAINERS
18
@@ -XXX,XX +XXX,XX @@ F: disas/arm.c
19
F: disas/arm-a64.cc
20
F: disas/libvixl/
21
22
+ARM SMMU
23
+M: Eric Auger <eric.auger@redhat.com>
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+L: qemu-arm@nongnu.org
25
+S: Maintained
26
+F: hw/arm/smmu*
27
+F: include/hw/arm/smmu*
28
+
29
CRIS
30
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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S: Maintained
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--
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2.19.1
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diff view generated by jsdifflib