1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | Last arm patches for rc3... |
---|---|---|---|
2 | caused new clang sanitizer warnings. | ||
3 | 2 | ||
3 | thanks | ||
4 | -- PMM | 4 | -- PMM |
5 | 5 | ||
6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 6 | The following changes since commit 72138f9bf5d8c316043b0d2cc7a674f70930cf95: |
7 | 7 | ||
8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | 8 | Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging (2018-11-26 11:46:04 +0000) |
9 | 9 | ||
10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181126 |
13 | 13 | ||
14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 14 | for you to fetch changes up to 58102ce7fbb2362aa53984aabcf684d164da2d9d: |
15 | 15 | ||
16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 16 | net: cadence_gem: Remove incorrect assert() (2018-11-26 13:41:42 +0000) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 20 | * some updates to MAINTAINERS file entries |
21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 21 | * cadence_gem: Remove an incorrect assert() |
22 | * target/arm: Define fields of ISAR registers | ||
23 | * target/arm: Align cortex-r5 id_isar0 | ||
24 | * target/arm: Fix cortex-a7 id_isar0 | ||
25 | * net/cadence_gem: Fix various bugs, add support for new | ||
26 | features that will be used by the Xilinx Versal board | ||
27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
28 | * target/arm: Add the Cortex-A72 | ||
29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | ||
30 | * target/arm: Mask PMOVSR writes based on supported counters | ||
31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
33 | 22 | ||
34 | ---------------------------------------------------------------- | 23 | ---------------------------------------------------------------- |
35 | Aaron Lindsay (2): | 24 | Edgar E. Iglesias (1): |
36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 25 | net: cadence_gem: Remove incorrect assert() |
37 | target/arm: Mask PMOVSR writes based on supported counters | ||
38 | 26 | ||
39 | Edgar E. Iglesias (8): | 27 | Eric Auger (1): |
40 | net: cadence_gem: Disable TSU feature bit | 28 | MAINTAINERS: Add an ARM SMMU section |
41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | ||
42 | net: cadence_gem: Add macro with max number of descriptor words | ||
43 | net: cadence_gem: Add support for extended descriptors | ||
44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
45 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
47 | target/arm: Add the Cortex-A72 | ||
48 | 29 | ||
49 | Jerome Forissier (1): | 30 | Thomas Huth (1): |
50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 31 | MAINTAINERS: Assign some more files in the hw/arm/ directory |
51 | 32 | ||
52 | Peter Maydell (2): | 33 | hw/net/cadence_gem.c | 1 - |
53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 34 | MAINTAINERS | 23 +++++++++++++++++++++++ |
54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | 35 | 2 files changed, 23 insertions(+), 1 deletion(-) |
55 | 36 | ||
56 | Richard Henderson (4): | ||
57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | ||
58 | target/arm: Define fields of ISAR registers | ||
59 | target/arm: Align cortex-r5 id_isar0 | ||
60 | target/arm: Fix cortex-a7 id_isar0 | ||
61 | |||
62 | include/hw/net/cadence_gem.h | 7 +- | ||
63 | target/arm/cpu.h | 95 ++++++++++++++- | ||
64 | hw/arm/virt.c | 4 + | ||
65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | ||
66 | target/arm/arm-powerctl.c | 10 ++ | ||
67 | target/arm/cpu.c | 7 +- | ||
68 | target/arm/cpu64.c | 66 +++++++++- | ||
69 | target/arm/helper.c | 27 +++-- | ||
70 | target/arm/op_helper.c | 6 +- | ||
71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | ||
72 | 10 files changed, 402 insertions(+), 70 deletions(-) | ||
73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | ||
74 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Thomas Huth <thuth@redhat.com> | ||
1 | 2 | ||
3 | I apparently missed some more files and even a complete machine (the | ||
4 | "imx25-pdk") in my previous patch... but now we should hopefully have | ||
5 | a completely coverage for all available ARM boards. | ||
6 | |||
7 | Fixes: 95a5db3ae5698b49c63144610ad02913e780c828 | ||
8 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
10 | Message-id: 1542782568-20059-1-git-send-email-thuth@redhat.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | MAINTAINERS | 16 ++++++++++++++++ | ||
14 | 1 file changed, 16 insertions(+) | ||
15 | |||
16 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/MAINTAINERS | ||
19 | +++ b/MAINTAINERS | ||
20 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | ||
21 | S: Odd Fixes | ||
22 | F: hw/arm/gumstix.c | ||
23 | |||
24 | +i.MX25 PDK | ||
25 | +M: Peter Maydell <peter.maydell@linaro.org> | ||
26 | +R: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
27 | +L: qemu-arm@nongnu.org | ||
28 | +S: Odd Fixes | ||
29 | +F: hw/arm/fsl-imx25.c | ||
30 | +F: hw/arm/imx25_pdk.c | ||
31 | +F: hw/misc/imx25_ccm.c | ||
32 | +F: include/hw/arm/fsl-imx25.h | ||
33 | +F: include/hw/misc/imx25_ccm.h | ||
34 | + | ||
35 | i.MX31 (kzm) | ||
36 | M: Peter Chubb <peter.chubb@nicta.com.au> | ||
37 | M: Peter Maydell <peter.maydell@linaro.org> | ||
38 | @@ -XXX,XX +XXX,XX @@ R: Andrew Baumann <Andrew.Baumann@microsoft.com> | ||
39 | R: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
40 | L: qemu-arm@nongnu.org | ||
41 | S: Odd Fixes | ||
42 | +F: hw/arm/raspi.c | ||
43 | F: hw/arm/raspi_platform.h | ||
44 | F: hw/*/bcm283* | ||
45 | F: include/hw/arm/raspi* | ||
46 | @@ -XXX,XX +XXX,XX @@ F: hw/arm/spitz.c | ||
47 | F: hw/arm/tosa.c | ||
48 | F: hw/arm/z2.c | ||
49 | F: hw/*/pxa2xx* | ||
50 | +F: hw/display/tc6393xb.c | ||
51 | +F: hw/gpio/max7310.c | ||
52 | +F: hw/gpio/zaurus.c | ||
53 | F: hw/misc/mst_fpga.c | ||
54 | F: include/hw/arm/pxa.h | ||
55 | +F: include/hw/arm/sharpsl.h | ||
56 | |||
57 | SABRELITE / i.MX6 | ||
58 | M: Peter Maydell <peter.maydell@linaro.org> | ||
59 | -- | ||
60 | 2.19.1 | ||
61 | |||
62 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Eric Auger <eric.auger@redhat.com> | ||
1 | 2 | ||
3 | Add a new ARM SMMU section and set Eric Auger as the maintainer | ||
4 | for ARM SMMU emulation sources. | ||
5 | |||
6 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
7 | Message-id: 20181122180143.14237-1-eric.auger@redhat.com | ||
8 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | MAINTAINERS | 7 +++++++ | ||
12 | 1 file changed, 7 insertions(+) | ||
13 | |||
14 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/MAINTAINERS | ||
17 | +++ b/MAINTAINERS | ||
18 | @@ -XXX,XX +XXX,XX @@ F: disas/arm.c | ||
19 | F: disas/arm-a64.cc | ||
20 | F: disas/libvixl/ | ||
21 | |||
22 | +ARM SMMU | ||
23 | +M: Eric Auger <eric.auger@redhat.com> | ||
24 | +L: qemu-arm@nongnu.org | ||
25 | +S: Maintained | ||
26 | +F: hw/arm/smmu* | ||
27 | +F: include/hw/arm/smmu* | ||
28 | + | ||
29 | CRIS | ||
30 | M: Edgar E. Iglesias <edgar.iglesias@gmail.com> | ||
31 | S: Maintained | ||
32 | -- | ||
33 | 2.19.1 | ||
34 | |||
35 | diff view generated by jsdifflib |