| 1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | v2: fix compile failure on arm hosts... |
|---|---|---|---|
| 2 | caused new clang sanitizer warnings. | ||
| 3 | 2 | ||
| 3 | thanks | ||
| 4 | -- PMM | 4 | -- PMM |
| 5 | 5 | ||
| 6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 6 | The following changes since commit 6db87aae61bc6ac0a8cd9bc2e05d7ebfbcfd3657: |
| 7 | 7 | ||
| 8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | 8 | Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-12 17:11:22 +0000) |
| 9 | 9 | ||
| 10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
| 11 | 11 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181113 |
| 13 | 13 | ||
| 14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 14 | for you to fetch changes up to 436c0cbbeb38dd97c02fe921a7cb253a18afdd86: |
| 15 | 15 | ||
| 16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 16 | target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature (2018-11-13 10:47:59 +0000) |
| 17 | 17 | ||
| 18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 19 | target/arm queue: |
| 20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 20 | * Remove no-longer-needed workaround for small SAU regions for v8M |
| 21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 21 | * Remove antique TODO comment |
| 22 | * target/arm: Define fields of ISAR registers | 22 | * MAINTAINERS: Add an entry for the 'collie' machine |
| 23 | * target/arm: Align cortex-r5 id_isar0 | 23 | * hw/arm/sysbus-fdt: Only call match_fn callback if the type matches |
| 24 | * target/arm: Fix cortex-a7 id_isar0 | 24 | * Fix infinite recursion in tlbi_aa64_vmalle1_write() |
| 25 | * net/cadence_gem: Fix various bugs, add support for new | 25 | * ARM KVM: fix various bugs in handling of guest debugging |
| 26 | features that will be used by the Xilinx Versal board | 26 | * Correctly implement handling of HCR_EL2.{VI, VF} |
| 27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | 27 | * Hyp mode R14 is shared with User and System |
| 28 | * target/arm: Add the Cortex-A72 | 28 | * Give Cortex-A15 and -A7 the EL2 feature |
| 29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | ||
| 30 | * target/arm: Mask PMOVSR writes based on supported counters | ||
| 31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 33 | 29 | ||
| 34 | ---------------------------------------------------------------- | 30 | ---------------------------------------------------------------- |
| 35 | Aaron Lindsay (2): | 31 | Alex Bennée (6): |
| 36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 32 | target/arm64: properly handle DBGVR RESS bits |
| 37 | target/arm: Mask PMOVSR writes based on supported counters | 33 | target/arm64: hold BQL when calling do_interrupt() |
| 34 | target/arm64: kvm debug set target_el when passing exception to guest | ||
| 35 | tests/guest-debug: fix scoping of failcount | ||
| 36 | arm: use symbolic MDCR_TDE in arm_debug_target_el | ||
| 37 | arm: fix aa64_generate_debug_exceptions to work with EL2 | ||
| 38 | 38 | ||
| 39 | Edgar E. Iglesias (8): | 39 | Eric Auger (1): |
| 40 | net: cadence_gem: Disable TSU feature bit | 40 | hw/arm/sysbus-fdt: Only call match_fn callback if the type matches |
| 41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | ||
| 42 | net: cadence_gem: Add macro with max number of descriptor words | ||
| 43 | net: cadence_gem: Add support for extended descriptors | ||
| 44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
| 45 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
| 46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 47 | target/arm: Add the Cortex-A72 | ||
| 48 | 41 | ||
| 49 | Jerome Forissier (1): | 42 | Peter Maydell (7): |
| 50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 43 | target/arm: Remove workaround for small SAU regions |
| 44 | target/arm: Remove antique TODO comment | ||
| 45 | Revert "target/arm: Implement HCR.VI and VF" | ||
| 46 | target/arm: Track the state of our irq lines from the GIC explicitly | ||
| 47 | target/arm: Correctly implement handling of HCR_EL2.{VI, VF} | ||
| 48 | target/arm: Hyp mode R14 is shared with User and System | ||
| 49 | target/arm/cpu: Give Cortex-A15 and -A7 the EL2 feature | ||
| 51 | 50 | ||
| 52 | Peter Maydell (2): | 51 | Richard Henderson (1): |
| 53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 52 | target/arm: Fix typo in tlbi_aa64_vmalle1_write |
| 54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 55 | 53 | ||
| 56 | Richard Henderson (4): | 54 | Thomas Huth (1): |
| 57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | 55 | MAINTAINERS: Add an entry for the 'collie' machine |
| 58 | target/arm: Define fields of ISAR registers | ||
| 59 | target/arm: Align cortex-r5 id_isar0 | ||
| 60 | target/arm: Fix cortex-a7 id_isar0 | ||
| 61 | 56 | ||
| 62 | include/hw/net/cadence_gem.h | 7 +- | 57 | target/arm/cpu.h | 44 +++++++++++------ |
| 63 | target/arm/cpu.h | 95 ++++++++++++++- | 58 | target/arm/internals.h | 34 +++++++++++++ |
| 64 | hw/arm/virt.c | 4 + | 59 | hw/arm/sysbus-fdt.c | 12 +++-- |
| 65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | 60 | target/arm/cpu.c | 67 ++++++++++++++++++++++++- |
| 66 | target/arm/arm-powerctl.c | 10 ++ | 61 | target/arm/helper.c | 101 +++++++++++++------------------------- |
| 67 | target/arm/cpu.c | 7 +- | 62 | target/arm/kvm32.c | 4 +- |
| 68 | target/arm/cpu64.c | 66 +++++++++- | 63 | target/arm/kvm64.c | 20 +++++++- |
| 69 | target/arm/helper.c | 27 +++-- | 64 | target/arm/machine.c | 51 +++++++++++++++++++ |
| 70 | target/arm/op_helper.c | 6 +- | 65 | target/arm/op_helper.c | 4 +- |
| 71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | 66 | MAINTAINERS | 7 +++ |
| 72 | 10 files changed, 402 insertions(+), 70 deletions(-) | 67 | tests/guest-debug/test-gdbstub.py | 1 + |
| 73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | 68 | 11 files changed, 249 insertions(+), 96 deletions(-) |
| 74 | 69 | diff view generated by jsdifflib |