[Qemu-devel] [PULL 00/17] target-arm queue
[Qemu-devel] [PULL 0/5] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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Handful of bugfix patches for arm for rc0; also
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caused new clang sanitizer warnings.
2
one milkymist patch, thrown in since I was putting
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the pullreq together anyway.
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4
5
thanks
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-- PMM
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-- PMM
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7
6
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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The following changes since commit 03c1ca1c51783603d42eb0f91d35961f0f4b4947:
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20181105' into staging (2018-11-06 09:10:46 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181106
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15
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to 23463e0e4aeb2f0a9c60549a2c163f4adc0b8512:
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17
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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target/arm: Fix ATS1Hx instructions (2018-11-06 11:32:14 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* Remove can't-happen if() from handle_vec_simd_shli()
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* hw/arm/exynos4210: Zero memory allocated for Exynos4210State
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* target/arm: Define fields of ISAR registers
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* Set S and PTW in 64-bit PAR format
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* target/arm: Align cortex-r5 id_isar0
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* Fix ATS1Hx instructions
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* target/arm: Fix cortex-a7 id_isar0
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* milkymist: Check for failure trying to load BIOS image
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* net/cadence_gem: Fix various bugs, add support for new
26
features that will be used by the Xilinx Versal board
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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27
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Peter Maydell (5):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
30
target/arm: Remove can't-happen if() from handle_vec_simd_shli()
37
target/arm: Mask PMOVSR writes based on supported counters
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milkymist: Check for failure trying to load BIOS image
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hw/arm/exynos4210: Zero memory allocated for Exynos4210State
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target/arm: Set S and PTW in 64-bit PAR format
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target/arm: Fix ATS1Hx instructions
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35
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Edgar E. Iglesias (8):
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hw/arm/exynos4210.c | 2 +-
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net: cadence_gem: Disable TSU feature bit
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hw/lm32/milkymist.c | 5 ++++-
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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target/arm/helper.c | 14 ++++++++------
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net: cadence_gem: Add macro with max number of descriptor words
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target/arm/translate-a64.c | 8 +++-----
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net: cadence_gem: Add support for extended descriptors
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4 files changed, 16 insertions(+), 13 deletions(-)
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Jerome Forissier (1):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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Peter Maydell (2):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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Richard Henderson (4):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 1/5] target/arm: Remove can't-happen if() from handle_vec_simd_shli()
1
In handle_vec_simd_shli() we have a check:
2
if (size > 3 && !is_q) {
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unallocated_encoding(s);
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return;
5
}
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However this can never be true, because we calculate
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int size = 32 - clz32(immh) - 1;
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where immh is a 4 bit field which we know cannot be all-zeroes.
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So the clz32() return must be in {28,29,30,31} and the resulting
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size is in {0,1,2,3}, and "size > 3" is never true.
1
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This unnecessary code confuses Coverity's analysis:
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in CID 1396476 it thinks we might later index off the
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end of an array because the condition implies that we
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might have a size > 3.
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Remove the code, and instead assert that the size is in [0..3],
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since the decode that enforces that is somewhat distant from
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this function.
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Tested-by: Alex Bennée <alex.bennee@linaro.org>
25
Message-id: 20181030162517.21816-1-peter.maydell@linaro.org
26
---
27
target/arm/translate-a64.c | 8 +++-----
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1 file changed, 3 insertions(+), 5 deletions(-)
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diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
31
index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/translate-a64.c
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+++ b/target/arm/translate-a64.c
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@@ -XXX,XX +XXX,XX @@ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
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int immhb = immh << 3 | immb;
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int shift = immhb - (8 << size);
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38
- if (extract32(immh, 3, 1) && !is_q) {
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- unallocated_encoding(s);
40
- return;
41
- }
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+ /* Range of size is limited by decode: immh is a non-zero 4 bit field */
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+ assert(size >= 0 && size <= 3);
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45
- if (size > 3 && !is_q) {
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+ if (extract32(immh, 3, 1) && !is_q) {
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unallocated_encoding(s);
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return;
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}
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--
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2.19.1
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diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 2/5] milkymist: Check for failure trying to load BIOS image
1
Check the return value from load_image_targphys(), which tells us
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whether our attempt to load the BIOS image into RAM failed.
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(Spotted by Coverity, CID 1190305.)
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Acked-by: Michael Walle <michael@walle.cc>
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Message-id: 20181030170032.1844-1-peter.maydell@linaro.org
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---
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hw/lm32/milkymist.c | 5 ++++-
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1 file changed, 4 insertions(+), 1 deletion(-)
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diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c
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index XXXXXXX..XXXXXXX 100644
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--- a/hw/lm32/milkymist.c
16
+++ b/hw/lm32/milkymist.c
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@@ -XXX,XX +XXX,XX @@ milkymist_init(MachineState *machine)
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bios_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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if (bios_filename) {
21
- load_image_targphys(bios_filename, BIOS_OFFSET, BIOS_SIZE);
22
+ if (load_image_targphys(bios_filename, BIOS_OFFSET, BIOS_SIZE) < 0) {
23
+ error_report("could not load bios '%s'", bios_filename);
24
+ exit(1);
25
+ }
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}
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reset_info->bootstrap_pc = BIOS_OFFSET;
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--
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2.19.1
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32
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 3/5] hw/arm/exynos4210: Zero memory allocated for Exynos4210State
1
In exynos4210_init() we allocate memory for an Exynos4210State
2
struct. Generally devices can assume that the memory allocated
3
for their state struct is zero-initialized; we broke that
4
assumption here by using g_new(). Use g_new0() instead.
5
(In particular, some code assumes that the various irq arrays
6
in the Exynos4210Irq sub-struct are zero-initialized.)
1
7
8
In the longer term, this code should be QOMified, and then
9
the struct memory will be allocated elsewhere and by functions
10
which always zero-initalize it; but for 3.1 this is a
11
simple fix.
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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Message-id: 20181105151132.13884-1-peter.maydell@linaro.org
17
---
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hw/arm/exynos4210.c | 2 +-
19
1 file changed, 1 insertion(+), 1 deletion(-)
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21
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
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index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/exynos4210.c
24
+++ b/hw/arm/exynos4210.c
25
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
26
27
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
28
{
29
- Exynos4210State *s = g_new(Exynos4210State, 1);
30
+ Exynos4210State *s = g_new0(Exynos4210State, 1);
31
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
32
SysBusDevice *busdev;
33
DeviceState *dev;
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--
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2.19.1
36
37
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 4/5] target/arm: Set S and PTW in 64-bit PAR format
1
In do_ats_write() we construct a PAR value based on the result
2
of the translation. A comment says "S2WLK and FSTAGE are always
3
zero, because we don't implement virtualization".
4
Since we do in fact now implement virtualization, add the missing
5
code that sets these bits based on the reported ARMMMUFaultInfo.
1
6
7
(These bits are named PTW and S in ARMv8, so we follow that
8
convention in the new comments in this patch.)
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10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20181016093703.10637-2-peter.maydell@linaro.org
14
---
15
target/arm/helper.c | 10 ++++++----
16
1 file changed, 6 insertions(+), 4 deletions(-)
17
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
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index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.c
21
+++ b/target/arm/helper.c
22
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
23
24
par64 |= 1; /* F */
25
par64 |= (fsr & 0x3f) << 1; /* FS */
26
- /* Note that S2WLK and FSTAGE are always zero, because we don't
27
- * implement virtualization and therefore there can't be a stage 2
28
- * fault.
29
- */
30
+ if (fi.stage2) {
31
+ par64 |= (1 << 9); /* S */
32
+ }
33
+ if (fi.s1ptw) {
34
+ par64 |= (1 << 8); /* PTW */
35
+ }
36
}
37
} else {
38
/* fsr is a DFSR/IFSR value for the short descriptor
39
--
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2.19.1
41
42
diff view generated by jsdifflib
New patch
[Qemu-devel] [PULL 5/5] target/arm: Fix ATS1Hx instructions
1
ATS1HR and ATS1HW (which allow AArch32 EL2 to do address translations
2
on the EL2 translation regime) were implemented in commit 14db7fe09a2c8.
3
However, we got them wrong: these should do stage 1 address translations
4
as defined for NS-EL2, which is ARMMMUIdx_S1E2. We were incorrectly
5
making them perform stage 2 translations.
1
6
7
A few years later in commit 1313e2d7e2cd we forgot entirely that
8
we'd implemented ATS1Hx, and added a comment that ATS1Hx were
9
"not supported yet". Remove the comment; there is no extra code
10
needed to handle these operations in do_ats_write(), because
11
arm_s1_regime_using_lpae_format() returns true for ARMMMUIdx_S1E2,
12
which forces 64-bit PAR format.
13
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
Message-id: 20181016093703.10637-3-peter.maydell@linaro.org
17
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
18
---
19
target/arm/helper.c | 4 ++--
20
1 file changed, 2 insertions(+), 2 deletions(-)
21
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
25
+++ b/target/arm/helper.c
26
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
27
*
28
* (Note that HCR.DC makes HCR.VM behave as if it is 1.)
29
*
30
- * ATS1Hx always uses the 64bit format (not supported yet).
31
+ * ATS1Hx always uses the 64bit format.
32
*/
33
format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
34
35
@@ -XXX,XX +XXX,XX @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
36
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
37
uint64_t par64;
38
39
- par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
40
+ par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2);
41
42
A32_BANKED_CURRENT_REG_SET(env, par, par64);
43
}
44
--
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2.19.1
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47
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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