[Qemu-devel] [PULL 00/17] target-arm queue
[Qemu-devel] [PULL v2 00/44] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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v1->v2 changes: drop the "convert FEATURE_THUMB2EE" patch as
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caused new clang sanitizer warnings.
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it broke compilation on arm hosts (conversion of KVM related
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code had been forgotten)
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thanks
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-- PMM
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-- PMM
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22' into staging (2018-10-23 17:20:23 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181024
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to 93f379b0c43617b1361f742f261479eaed4959cb:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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target/arm: Only flush tlb if ASID changes (2018-10-24 07:51:37 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* ssi-sd: Make devices picking up backends unavailable with -device
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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* Add support for VCPU event states
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* target/arm: Define fields of ISAR registers
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* Move towards making ID registers the source of truth for
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* target/arm: Align cortex-r5 id_isar0
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whether a guest CPU implements a feature, rather than having
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* target/arm: Fix cortex-a7 id_isar0
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parallel ID registers and feature bit flags
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* net/cadence_gem: Fix various bugs, add support for new
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* Implement various HCR hypervisor trap/config bits
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features that will be used by the Xilinx Versal board
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* Get IL bit correct for v7 syndrome values
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* Report correct syndrome for FP/SIMD traps to Hyp mode
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* target/arm: Add the Cortex-A72
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* hw/arm/boot: Increase compliance with kernel arm64 boot protocol
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* Refactor A32 Neon to use generic vector infrastructure
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* target/arm: Mask PMOVSR writes based on supported counters
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* Fix a bug in A32 VLD2 "(multiple 2-element structures)" insn
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* net: cadence_gem: Report features correctly in ID register
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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* Avoid some unnecessary TLB flushes on TTBR register writes
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Dongjiu Geng (1):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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target/arm: Add support for VCPU event states
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target/arm: Mask PMOVSR writes based on supported counters
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Edgar E. Iglesias (8):
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Edgar E. Iglesias (2):
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net: cadence_gem: Disable TSU feature bit
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net: cadence_gem: Announce availability of priority queues
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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net: cadence_gem: Announce 64bit addressing support
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net: cadence_gem: Add macro with max number of descriptor words
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Jerome Forissier (1):
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Markus Armbruster (1):
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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ssi-sd: Make devices picking up backends unavailable with -device
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Peter Maydell (2):
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Peter Maydell (10):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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target/arm: Improve debug logging of AArch32 exception return
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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target/arm: Make switch_mode() file-local
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target/arm: Implement HCR.FB
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target/arm: Implement HCR.DC
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target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set
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target/arm: Implement HCR.VI and VF
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target/arm: Implement HCR.PTW
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target/arm: New utility function to extract EC from syndrome
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target/arm: Get IL bit correct for v7 syndrome values
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target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode
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Richard Henderson (4):
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Richard Henderson (29):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm: Move some system registers into a substructure
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target/arm: Define fields of ISAR registers
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target/arm: V8M should not imply V7VE
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target/arm: Align cortex-r5 id_isar0
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target/arm: Convert v8 extensions from feature bits to isar tests
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target/arm: Fix cortex-a7 id_isar0
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target/arm: Convert division from feature bits to isar0 tests
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target/arm: Convert jazelle from feature bit to isar1 test
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target/arm: Convert sve from feature bit to aa64pfr0 test
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target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test
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target/arm: Hoist address increment for vector memory ops
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target/arm: Don't call tcg_clear_temp_count
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target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R
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target/arm: Promote consecutive memory ops for aa64
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target/arm: Mark some arrays const
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target/arm: Use gvec for NEON VDUP
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target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)
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target/arm: Use gvec for NEON_3R_LOGIC insns
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target/arm: Use gvec for NEON_3R_VADD_VSUB insns
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target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG
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target/arm: Use gvec for NEON_3R_VMUL
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target/arm: Use gvec for VSHR, VSHL
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target/arm: Use gvec for VSRA
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target/arm: Use gvec for VSRI, VSLI
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target/arm: Use gvec for NEON_3R_VML
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target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE
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target/arm: Use gvec for NEON VLD all lanes
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target/arm: Reorg NEON VLD/VST all elements
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target/arm: Promote consecutive memory ops for aa32
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target/arm: Reorg NEON VLD/VST single element to one lane
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target/arm: Remove writefn from TTBR0_EL3
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target/arm: Only flush tlb if ASID changes
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include/hw/net/cadence_gem.h | 7 +-
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Stewart Hildebrand (1):
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/boot: Increase compliance with kernel arm64 boot protocol
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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target/arm/cpu.h | 221 ++++++-
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target/arm/internals.h | 45 +-
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target/arm/kvm_arm.h | 24 +
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target/arm/translate.h | 21 +
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hw/arm/boot.c | 18 +
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hw/intc/armv7m_nvic.c | 12 +-
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hw/net/cadence_gem.c | 9 +-
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hw/sd/ssi-sd.c | 2 +
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linux-user/aarch64/signal.c | 4 +-
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linux-user/elfload.c | 58 +-
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linux-user/syscall.c | 10 +-
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target/arm/cpu.c | 238 +++----
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target/arm/cpu64.c | 148 +++--
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target/arm/helper.c | 395 ++++++++----
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target/arm/kvm.c | 60 ++
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target/arm/kvm32.c | 13 +
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target/arm/kvm64.c | 15 +-
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target/arm/machine.c | 25 +-
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target/arm/op_helper.c | 2 +-
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target/arm/translate-a64.c | 715 ++++-----------------
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target/arm/translate.c | 1451 ++++++++++++++++++++++++++++---------------
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21 files changed, 2013 insertions(+), 1473 deletions(-)
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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