| 1 | v2: dropped a couple of cadence_gem changes to ID regs that | 1 | A random mix of items here, nothing very major. v2 is just |
|---|---|---|---|
| 2 | caused new clang sanitizer warnings. | 2 | squashing in the fix for the clang unused-function error. |
| 3 | 3 | ||
| 4 | thanks | ||
| 4 | -- PMM | 5 | -- PMM |
| 5 | 6 | ||
| 6 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | ||
| 7 | 7 | ||
| 8 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | 8 | The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b: |
| 9 | 9 | ||
| 10 | are available in the Git repository at: | 10 | Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000) |
| 11 | 11 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1 | 12 | are available in the git repository at: |
| 13 | 13 | ||
| 14 | for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b: | 14 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207-1 |
| 15 | 15 | ||
| 16 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100) | 16 | for you to fetch changes up to aecfbbc97a2e52bbee34a53c32f961a182046a95: |
| 17 | |||
| 18 | stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:55:15 +0000) | ||
| 17 | 19 | ||
| 18 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 21 | target-arm: |
| 20 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 22 | * new "unimplemented" device for stubbing out devices in a |
| 21 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 23 | system model so accesses can be logged |
| 22 | * target/arm: Define fields of ISAR registers | 24 | * stellaris: document the SoC memory map |
| 23 | * target/arm: Align cortex-r5 id_isar0 | 25 | * arm: create instruction syndromes for AArch32 data aborts |
| 24 | * target/arm: Fix cortex-a7 id_isar0 | 26 | * arm: Correctly handle watchpoints for BE32 CPUs |
| 25 | * net/cadence_gem: Fix various bugs, add support for new | 27 | * Fix Thumb-1 BE32 execution and disassembly |
| 26 | features that will be used by the Xilinx Versal board | 28 | * arm: Add cfgend parameter for ARM CPU selection |
| 27 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | 29 | * sd: sdhci: check data length during dma_memory_read |
| 28 | * target/arm: Add the Cortex-A72 | 30 | * aspeed: add a watchdog controller |
| 29 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 31 | * integratorcp: adding vmstate for save/restore |
| 30 | * target/arm: Mask PMOVSR writes based on supported counters | ||
| 31 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 32 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 33 | 32 | ||
| 34 | ---------------------------------------------------------------- | 33 | ---------------------------------------------------------------- |
| 35 | Aaron Lindsay (2): | 34 | Cédric Le Goater (2): |
| 36 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 35 | wdt: Add Aspeed watchdog device model |
| 37 | target/arm: Mask PMOVSR writes based on supported counters | 36 | aspeed: add a watchdog controller |
| 38 | 37 | ||
| 39 | Edgar E. Iglesias (8): | 38 | Julian Brown (4): |
| 40 | net: cadence_gem: Disable TSU feature bit | 39 | hw/arm/integratorcp: Support specifying features via -cpu |
| 41 | net: cadence_gem: Use uint32_t for 32bit descriptor words | 40 | target/arm: Add cfgend parameter for ARM CPU selection. |
| 42 | net: cadence_gem: Add macro with max number of descriptor words | 41 | Fix Thumb-1 BE32 execution and disassembly. |
| 43 | net: cadence_gem: Add support for extended descriptors | 42 | arm: Correctly handle watchpoints for BE32 CPUs |
| 44 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
| 45 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
| 46 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 47 | target/arm: Add the Cortex-A72 | ||
| 48 | 43 | ||
| 49 | Jerome Forissier (1): | 44 | Pavel Dovgalyuk (1): |
| 50 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 45 | integratorcp: adding vmstate for save/restore |
| 51 | 46 | ||
| 52 | Peter Maydell (2): | 47 | Peter Maydell (5): |
| 53 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 48 | target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode |
| 54 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | 49 | target/arm: A32, T32: Create Instruction Syndromes for Data Aborts |
| 50 | stellaris: Document memory map and which SoC devices are unimplemented | ||
| 51 | hw/misc: New "unimplemented" sysbus device | ||
| 52 | stellaris: Use the 'unimplemented' device for parts we don't implement | ||
| 55 | 53 | ||
| 56 | Richard Henderson (4): | 54 | Prasad J Pandit (1): |
| 57 | target/arm: Fix aarch64_sve_change_el wrt EL0 | 55 | sd: sdhci: check data length during dma_memory_read |
| 58 | target/arm: Define fields of ISAR registers | ||
| 59 | target/arm: Align cortex-r5 id_isar0 | ||
| 60 | target/arm: Fix cortex-a7 id_isar0 | ||
| 61 | 56 | ||
| 62 | include/hw/net/cadence_gem.h | 7 +- | 57 | hw/misc/Makefile.objs | 2 + |
| 63 | target/arm/cpu.h | 95 ++++++++++++++- | 58 | hw/watchdog/Makefile.objs | 1 + |
| 64 | hw/arm/virt.c | 4 + | 59 | include/disas/bfd.h | 7 ++ |
| 65 | hw/net/cadence_gem.c | 185 ++++++++++++++++++++--------- | 60 | include/hw/arm/aspeed_soc.h | 2 + |
| 66 | target/arm/arm-powerctl.c | 10 ++ | 61 | include/hw/misc/unimp.h | 39 +++++++ |
| 67 | target/arm/cpu.c | 7 +- | 62 | include/hw/watchdog/wdt_aspeed.h | 32 ++++++ |
| 68 | target/arm/cpu64.c | 66 +++++++++- | 63 | include/qom/cpu.h | 3 + |
| 69 | target/arm/helper.c | 27 +++-- | 64 | target/arm/arm_ldst.h | 10 +- |
| 70 | target/arm/op_helper.c | 6 +- | 65 | target/arm/cpu.h | 7 ++ |
| 71 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | 66 | target/arm/internals.h | 5 + |
| 72 | 10 files changed, 402 insertions(+), 70 deletions(-) | 67 | target/arm/translate.h | 14 +++ |
| 73 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | 68 | disas.c | 1 + |
| 69 | exec.c | 1 + | ||
| 70 | hw/arm/aspeed_soc.c | 13 +++ | ||
| 71 | hw/arm/integratorcp.c | 78 +++++++++++++- | ||
| 72 | hw/arm/stellaris.c | 48 +++++++++ | ||
| 73 | hw/misc/unimp.c | 107 +++++++++++++++++++ | ||
| 74 | hw/sd/sdhci.c | 2 +- | ||
| 75 | hw/watchdog/wdt_aspeed.c | 225 +++++++++++++++++++++++++++++++++++++++ | ||
| 76 | qom/cpu.c | 6 ++ | ||
| 77 | target/arm/cpu.c | 39 +++++++ | ||
| 78 | target/arm/op_helper.c | 22 ++++ | ||
| 79 | target/arm/translate-a64.c | 14 --- | ||
| 80 | target/arm/translate.c | 193 ++++++++++++++++++++++++--------- | ||
| 81 | 24 files changed, 801 insertions(+), 70 deletions(-) | ||
| 82 | create mode 100644 include/hw/misc/unimp.h | ||
| 83 | create mode 100644 include/hw/watchdog/wdt_aspeed.h | ||
| 84 | create mode 100644 hw/misc/unimp.c | ||
| 85 | create mode 100644 hw/watchdog/wdt_aspeed.c | ||
| 74 | 86 | diff view generated by jsdifflib |