v2: dropped a couple of cadence_gem changes to ID regs that
caused new clang sanitizer warnings.
-- PMM
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
----------------------------------------------------------------
target-arm queue:
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
* target/arm: Fix aarch64_sve_change_el wrt EL0
* target/arm: Define fields of ISAR registers
* target/arm: Align cortex-r5 id_isar0
* target/arm: Fix cortex-a7 id_isar0
* net/cadence_gem: Fix various bugs, add support for new
features that will be used by the Xilinx Versal board
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
* target/arm: Add the Cortex-A72
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
* target/arm: Mask PMOVSR writes based on supported counters
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
----------------------------------------------------------------
Aaron Lindsay (2):
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
target/arm: Mask PMOVSR writes based on supported counters
Edgar E. Iglesias (8):
net: cadence_gem: Disable TSU feature bit
net: cadence_gem: Use uint32_t for 32bit descriptor words
net: cadence_gem: Add macro with max number of descriptor words
net: cadence_gem: Add support for extended descriptors
net: cadence_gem: Add support for selecting the DMA MemoryRegion
net: cadence_gem: Implement support for 64bit descriptor addresses
target-arm: powerctl: Enable HVC when starting CPUs to EL2
target/arm: Add the Cortex-A72
Jerome Forissier (1):
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
Peter Maydell (2):
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
Richard Henderson (4):
target/arm: Fix aarch64_sve_change_el wrt EL0
target/arm: Define fields of ISAR registers
target/arm: Align cortex-r5 id_isar0
target/arm: Fix cortex-a7 id_isar0
include/hw/net/cadence_gem.h | 7 +-
target/arm/cpu.h | 95 ++++++++++++++-
hw/arm/virt.c | 4 +
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
target/arm/arm-powerctl.c | 10 ++
target/arm/cpu.c | 7 +-
target/arm/cpu64.c | 66 +++++++++-
target/arm/helper.c | 27 +++--
target/arm/op_helper.c | 6 +-
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
10 files changed, 402 insertions(+), 70 deletions(-)
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci